RW612 / Murata Type 2FR EVK – SRAM-resident code corrupted after boot Hello NXP Team, I am debugging a Murata Type 2FR EVK (RW612) where the application programs successfully into the external QSPI flash but does not run correctly. Hardware: Murata Type 2FR EVK (LBES0ZZ2FR) MCU: RW612 Cortex-M33 External Flash: Winbond W25Q128, 16 MB Debugger: SEGGER J-Link, S/N 69657567 SWD at 100 kHz Board powered through USB-C SWD: J11 pin 2 = SWDIO, pin 4 = SWCLK, pin 3 = GND J-Link successfully detects the RW612 and programs the external flash without errors. Software: MCUXpresso IDE 25.6.136 RW612 SDK Started with the rdrw612bga_wifi_cli example. Modified the FlexSPI flash configuration for W25Q128 and changed QSPI linker size from 8 MB to 16 MB. Build completes with 0 errors/warnings. Problem: After boot, the CPU eventually stops at:   PC = 0x20005840 ip4_input() at lwip/src/core/ipv4/ip4.c:556   The function ip4_input() is located in SRAM at 0x200056D4, but its contents appear corrupted:   0x200056D4: 0x4007EEBE 0xBC640C88 ...     However, the corresponding code in QSPI flash appears valid. The linker map shows that .data contains RAM-resident code:   LMA: 0x080F674C VMA: 0x20000000 Size: 0x1A0E4   and the startup section table specifies:   0x080F674C → 0x20000000, length 0x1A0E4   ResetISR() calls SystemInit() followed by data_init() to perform this initialization. I have also confirmed that SRAM itself is readable/writable through the debugger. My main question: why is the RAM-resident code becoming corrupted even though the QSPI source image appears valid? Could this be related to RW612 startup/RAM initialization, FlexSPI configuration, cache/MPU configuration, boot configuration, or a Type2FR-specific memory configuration? Also, is using a SEGGER J-Link instead of MCU-Link Pro expected to cause any issue with this boot/debug flow? I can provide the .map, linker script, startup_rw612.c, flash_config.c, and debug logs if required. Thank you. Evaluation Board Re: RW612 / Murata Type 2FR EVK – SRAM-resident code corrupted after boot Hi Daniel, Thank you for the response. We were previously using SDK 26.06, but our project was configured for a rdrw612bga board rather than the FRDM-RW612 configuration you recommended. Regarding the migration guide, yes, we have already gone through it: [NXP FRDM-RW612 Module Migration Guide](https://github.com/NXP-APPCODEHUB/an-frdmrw612-module-migration-guide) We followed the migration approach for the Murata Type 2FR, including updating the flash configuration for the W25Q128 (16 MB) and the corresponding linker configuration. However, we are facing an issue where the application programs successfully and starts executing, but eventually stops in `ip4_input()` at `0x20005840`. We also found that the code intended to execute from SRAM appears corrupted, while the corresponding code in QSPI flash appears valid. Based on your recommendation, we will now proceed using the **26.06 SDK with the FRDM-RW612 configuration** and follow the migration approach from that baseline. We will update the thread with our results. Thanks again for your guidance. Regards, Sakshee Re: RW612 / Murata Type 2FR EVK – SRAM-resident code corrupted after boot Hi, Could you please tell me what SDK version are you using? I recommend you to use the 26.06 for the FRDM-RW612, not the RD. By the way, did you already took a look into this? Regards, Daniel.

件名：MPC5605のメモリ読み取りに関する問題（アドレス：0x00100010） こんにちは、 MPC5605を使用しているECUに問題が発生しています。 EOLメモリダンプ操作中、ツールボックスはCPUの直接バイトアクセスを使ってメモリを読み込みます。 *((uint8_t *)address) CANのログより: 「`テキスト」 0x00100008から8バイトを読み込みました -> 成功 0x00100010から8バイトを読み取ると、ECUが応答しなくなりリセットされる。 「`」 MPC5606BKリファレンスマニュアル『16234_MPC5606BRM』、リバノリファレンス2を確認しました: - 表3-1、49ページでは、`0x00100000 - 0x001FFFFF`が**予約済み**と表示されています。 - 871～872ページでは、フラッシュメモリマップとフラッシュエミュレーションマッピングについて説明しています。 もう少し詳しく教えていただけますか: 1. 「0x00100010」はMPC5605にとって有効で読みやすいアドレスか? 2. 予約済みアドレスの場合、ソフトウェアが直接読み取った場合どうなりますか?CANは例外やリセットを引き起こすことはできますか? 3. 正確なMPC5605メモリマップにはどのリファレンス・マニュアルセクションを使うべきか? また、ECUハードウェアからMPC5605の完全な部品番号とシリコンリビジョンも収集しています。 よろしくお願いします、 カシラジャン C 開発ボード Re: Subject: MPC5605 memory-read issue at 0x00100010 こんにちは、 アドレス0x00100010は、MPC560xBメモリマップで予約済みとしてマークされている0x00100000-0x001FFFFFの範囲に属します。予約済み地域はアプリケーションソフトウェアでアクセスしてはなりません。そのような場所へのアクセスはバス関連の例外やデバイス固有の故障応答を引き起こす可能性があり、例外が処理されない場合、通信の喪失やリセットにつながることがあります。 第3章 メモリーマップ petervlna_0-1789455244473.pngpetervlna_0-1789455244473.png よろしくお願いいたします。 ピーター

I get an undefine value 0x00000033 when I read the DCMLCC register Hello When I read the DCMLCC register of the S32K314, the returned value is 0x00000033, DCMRLC:0b011, DCMCLC:0b011. The datasheet does not provide definitions for these values. What do these values mean? I tried obtaining the value of DCMLCS and got 0x06186084. Does this mean my chip has simply not been pushed to any lifecycle stage and is a normal value? DCMCLC.jpegDCMCLC.jpeg DCMRLC.jpegDCMRLC.jpeg Lika Re: I get an undefine value 0x00000033 when I read the DCMLCC register Okay, thank you very much. Re: I get an undefine value 0x00000033 when I read the DCMLCC register Hi Lika, We apologize for any inconvenience this may cause. This issue has been reported to the documentation department. 0b011 means CUST_DEL Best Regards, Robin

Gui-guider 2.0的一些建议 希望Gui-guider 2.0在设置中增加一个选项来控制开启或者关闭生成的文件中时间戳. 然后生成的每一个页面(screen)都会有相应的gg_event_screen.c,哪怕我的页面没有使用注册任何事件, 希望在没有注册任何事件的时候不要生成事件的任何内容. 另外希望能有一个机制能选择把一些没有显示的图片或者资源打包进项目,虽然目前可以在幽灵页上放图片和字体的方式包含进工程项目,但是不太优雅. 关于字体,目前在设置中有一个控制所有字体的默认生成范围的设置,希望未来能控制所有字体的生成的范围. 致谢 回复： Gui-guider 2.0的一些建议 Hi @Xu_556678 , 非常感谢您的反馈，这些建议对我们非常宝贵，我们将在未来release中考虑进行相应的优化和改进。 希望GUI Guider 能够帮助到您的工作，未来如有任何问题和建议都欢迎您反馈。 Best Regards, Wenbin Re: Gui-guider 2.0的一些建议 嗨@Xu_556678 ， 我想就您的一些请求，特别是关于图像和字体的生成，提供一些变通方案。 虽然将它们添加到虚拟页面中理论上可以让 GUI Guider 自动生成图像和字体，但您也可以将它们添加到“资源”面板，然后单击“转换”： EdwinHz_1-1789494348483.pngEdwinHz_1-1789494348483.png 此图像变流器功能允许您为任何受支持的图像生成输出文件。默认路径设置为“自定义”文件夹，但您可以将其更改为自动生成其他图像的同一文件夹，以便将它们全部放在一起。虽然这在技术上是一个手动过程，但其优点是您可以选择多个图像并一次性全部转换，因此如果您一次性处理所有图像，则只需执行此过程一次。这样，你就可以跳过目前这种变通方法，即创建一个幽灵屏幕，这种方法只会为根本不会使用的屏幕添加额外的代码。 EdwinHz_2-1789494766306.pngEdwinHz_2-1789494766306.png 此外，可以通过字体转换器对单个字体的生成范围进行精细控制。按照上述步骤操作，只是将图像替换为字体。弹出的窗口面板将显示一个选项，用于指定所选字体的范围，从而可以针对特定字体生成特定范围。 EdwinHz_3-1789494865236.pngEdwinHz_3-1789494865236.png 希望这些信息对您当前的 GUI 引导程序开发有所帮助。 如果您还有任何疑问或要求，请务必与我们联系！ BR， 埃德温。

I get an undefine value 0x00000033 when I read the DCMLCC register 您好 当我读取S32K314的 DCMLCC register时，返回的值为0x00000033,DCMRLC:0b011, DCMCLC:0b011,手册中并未给出这些值的定义，请问这个值代表什么意思。我尝试获取了DCMLCS的值，得到0x06186084，这是否说明我的芯片只是未被推进到任何生命周期，属于一个正常值？ DCMCLC.jpegDCMCLC.jpeg DCMRLC.jpegDCMRLC.jpeg Lika Re: I get an undefine value 0x00000033 when I read the DCMLCC register 好的，非常感谢 Re: I get an undefine value 0x00000033 when I read the DCMLCC register Hi Lika, 抱歉给您带来不便。 这个问题已经上报文档部门了。 0b011 意味着 CUST_DEL  Best Regards, Robin

Subject: MPC5605 memory-read issue at 0x00100010 Hello, We have an issue with an ECU using MPC5605. During an EOL memory-dump operation, our toolbox reads memory using a direct CPU byte access: *((uint8_t *)address) From the CAN log: ```text Read 8 bytes from 0x00100008 -> successful Read 8 bytes from 0x00100010 -> ECU stops responding and resets ``` We checked the MPC5606BK Reference Manual, `16234_MPC5606BRM`, Rev. 2: - Table 3-1, page 49, shows `0x00100000 - 0x001FFFFF` as **Reserved**. - Pages 871-872 describe the flash-memory map and flash-emulation mapping. Could you please clarify: 1. Is `0x00100010` a valid/readable address for MPC5605? 2. If it is a reserved address, what happens when software reads it directly? Can it cause an exception or reset? 3. Which reference manual section should we use for the exact MPC5605 memory map? We are also collecting the full MPC5605 part number and silicon revision from the ECU hardware. Best regards, kasirajan C Development Board Re: Subject: MPC5605 memory-read issue at 0x00100010 Hello, Address 0x00100010 belongs to the range 0x00100000-0x001FFFFF, which is marked as Reserved in the MPC560xB memory map. Reserved regions must not be accessed by application software. Accessing such locations may generate a bus-related exception or other device-specific fault response, which can result in loss of communication or a reset if the exception is not handled. Chapter 3 Memory Map petervlna_0-1789455244473.pngpetervlna_0-1789455244473.png Best regards, Peter

MPC5775B – Application to RAppID Bootloader transition Hello NXP Team, I am using MPC5775B with RAppID Bootloader for CAN flashing. I do not have the RAppID FBL source code, so I cannot modify the existing FBL. Is there a supported mechanism for the running application to request the existing RAppID FBL to enter programming mode? If yes, what is the required Application → FBL entry sequence for MPC5775B? Does this require a specific reset/boot mechanism, or does RAppID provide another way to request FBL from the application? Re: MPC5775B – Application to RAppID Bootloader transition Hello, There is no built-in, documented API in the RAppID FBL for the running application to programmatically request FBL entry. The RAppID bootloader for MPC57xx is a closed-binary, flash-resident bootloader (distributed as a pre-compiled .rbf file) with no source code provided and no modification possible. The standard mechanism to trigger it is a reset + boot-time flag check, not a runtime call from the application. Best regards, Peter Re: MPC5775B – Application to RAppID Bootloader transition Thanks Peter. Understood that the mechanism is a reset followed by a boot-time flag check. Since we do not have the RAppID FBL source code, could you please clarify what boot-time flag/condition the RAppID FBL for MPC5775B checks, and how the application can set/request it before reset? Is this a specific RAM address/magic value, reset-cause condition, configuration field, or another mechanism? If there is an application-side procedure or documentation for setting this flag, could you please share it?

ドライバードキュメントの未確認ヘッダー情報 私はS32DS内でS32K116向けのプロジェクトを開発しています。 今ではRTDがIPドライバとMCAL/AUTOSARの区別でどのように機能するかを理解しました。 リソースの制約があるため、今のところプロジェクトはIPドライバに限定します。 また、コンポーネントビュー内でIPドライバーコンポーネントを右クリックするとドキュメントが見つかることもわかりました。 しかし、説明された関数を使う際に各ドライバにどのヘッダーを含めるべきかはドキュメント内に記載されていません。 どうやってその情報を知ることができるんですか？これについて明記されている別の文書やリストはありますか？ Re: driver documentation missing header information こんにちは 通常、各IPドライバーのトップレベルのパブリックヘッダーは命名規則 _Ip.hに従います（例えば。Flexcan_Ip.h、Lpspi_Ip.h、Clock_Ip.h、Adc_Sar_Ip.h)。そのヘッダーはソースアプリケーションコードに含めるものです。 また、RTD内の例を参照して、どのヘッダーファイルを含めるべきかを確認できます: Julin_AragnM_1-1789513358457.pngJulin_AragnM_1-1789513358457.png FlexCAN -> FlexCAN_Ip.h プラットフォーム/割り込みコントローラ -> IntCtrl_Ip.h Port/Siul2 -> Siul2_Port_Ip.h ディオ/シウル2 -> Siul2_Dio_Ip.h RTDのインストールパス内で以下のヘッダーファイルを探せます:「C:\NXP\S32DS.3.x.x\S32DS\software\PlatformSDK_S32K1_S32M24\RTD\ _TS_...\include\」 よろしくお願いします、 ジュリアン

KE18F512VLH16 ECC RAM Single Bit Correction I have a follow up question related to @sean_dvorscak's post the other day (KE1 ECC RAM Single Bit Corrrection). @Celeste_Liu replied, ->> If implementing an optional scrub, please align the access according to the actual access size or scrub granularity, not blindly to the raw MCM_LMFAR value. Also don't use a fixed 4-byte access unless you first align the address appropriately and confirm the access size is valid. Can MCM_LMFATR[PEFSIZE] be used to determine the access size? If so, can this be used in tandem with MCM_LMFAR to implement a read-correct-writeback operation? For example, if MCM_LMFATR[PEFSIZE] is 3'b000 indicating an 8-bit access, can I perform an 8-bit read from the address indicated by MCM_LMFAR then perform an 8-bit write to the same address to correct the error. Similarly, if MCM_LMFATR[PEFSIZE] is 3'b010 indicating a 32-bit access, can I perform a 32-bit write to the address indicated by MCM_LMFAR without worrying about alignment? Re: KE18F512VLH16 ECC RAM Single Bit Correction Hello @rseigle77 , I have seen your post. Let me spend some time investigating this issue, and I will get back to you once I have more information. BR Celeste Re: KE18F512VLH16 ECC RAM Single Bit Correction Hello @rseigle77 , Regarding your question, I need to escalate it to our internal team for further investigation. According to our process, please provide the end application name. Thanks for your cooperation. BR Celeste Re: KE18F512VLH16 ECC RAM Single Bit Correction Hi @Celeste_Liu  - P7 is the name of the end application. Re: KE18F512VLH16 ECC RAM Single Bit Correction Hi @Celeste_Liu, is there any update on this?

MX95: raw video write throughput limited to ~50MB/s Hi, we're seeing a throughput/frame-rate issue when writing raw camera frames to a file: the actual capture rate drops well below the target frame rate once we write frames to storage, even though pure capture (without writing) runs at full frame rate. We'd like to understand the cause. The following is our environment configuration. - Board: i.MX95 19x19 LPDDR5 EVK - BSP: TechNexion Yocto 5.3 (Whinlatter), kernel 6.18.2 - Camera: TechNexion TEVS-AR0234 (MIPI CSI-2) - Capture device confirmed via media-ctl: tevs → csidev-4ad30000.csi → formatter@20 → crossbar → mxc_isi.0 → /dev/video0 ## Test 1: Capture only, no write (baseline) Sensor locked to 30fps via: v4l2-ctl -d /dev/v4l-subdev19 --set-subdev-fps pad=0,stream=0,fps=30 gst-launch-1.0 -e libcamerasrc ! video/x-raw,width=1920,height=1080,format=YUY2,framerate=30/1 ! fpsdisplaysink video-sink=fakesink text-overlay=false sync=false Result: stable 29.98fps, no dropped frames. ## Test 2: Write raw frames to file gst-launch-1.0 -e libcamerasrc ! video/x-raw,width=1920,height=1080,format=YUY2,framerate=30/1 ! filesink location=/tmp/test.yuv Result: ~11.7fps (measured by file size / capture duration), with GStreamer logs showing repeated warnings: WARN NxpNeoPipe neo_pipeline.cpp:3175 Image0 frame loss! expected X received Y where the gap between expected/received grows over time when fps is not locked, but stays small (1-2 frames) once sensor fps is locked to match the target. Same test repeated with `v4l2src device=/dev/video0` instead of `libcamerasrc`: same ~11.7-11.8fps result. Same test repeated at 1280x720: ~28.8fps (~53 MB/s), which converts to a similar MB/s ceiling as the 1920x1080 test above (~52 MB/s). We would like to know if a write speed limit of approximately 50 MB/s—when writing raw frames captured from `/dev/video0` (mxc-isi) to storage—is expected behavior for the current BSP/kernel version, or if we might be missing a configuration setting. We are happy to provide full logs, `media-ctl` topology output, and device tree information if needed. Yocto Project Re: MX95: raw video write throughput limited to ~50MB/s Hi,  @JosephAtNXP thank you for your prompt response. I’d like to confirm whether the root cause lies in the following factor. Additionally, would using Real-Time Yocto be helpful in this case? The captured frames are stored in a DMA buffer allocated via the Contiguous Memory Allocator (CMA). DMA writes from the ISP hardware to this memory have never been a bottleneck (local tmpfs write speeds reached up to 819 MB/s using dd, ruling out storage media limitations). The bottleneck occurs during the step where the CPU reads the contents of this buffer. This is further corroborated by the fact that the VPU hardware encoder can directly read the same buffer via DMA without any performance impact. This strongly indicates that the bottleneck stems from the memory's cache attribute configuration or the cost of maintaining cache coherency (e.g., cache invalidation) during each buffer dequeue operation, rather than bus bandwidth or storage device speed limitations. Re: MX95: raw video write throughput limited to ~50MB/s Hi, Thank you for your interest in NXP Semiconductor products, This is expected behavior as you can see in Linux Users Guide. In addition, writing frames to the file system generates a huge amount of data that is not absorbable in real time. In that case, because of the delay induced on the application to recycle its buffers, periodic frame loss is expected to occur. A workaround could be to use hardware video encoding before storing the captured frames. Regards

RW612 / Murata Type 2FR EVK – 启动后 SRAM 驻留代码损坏。 您好，NXP团队， 我正在调试一台Murata Type 2FR EVK (RW612)开发板，应用程序已成功写入外部 QSPI 闪存，但无法正常运行。 硬件： Murata Type 2FR EVK (LBES0ZZ2FR) MCU：RW612 Cortex-M33 外置闪存：Winbond W25Q128，16 MB 调试器：SEGGER J-Link，S/N 69657567 100 kHz 的短波放电 板通过 USB-C 供电。 SWD：J11 引脚 2 = SWDIO，引脚 4 = SWCLK，引脚 3 = GND J-Link 成功检测到 RW612 并对外部闪存进行编程，没有出现任何错误。 软件： MCUXpresso IDE 25.6.136 RW612 SDK 从 rdrw612bga_wifi_cli 示例开始。 修改了 W25Q128 的 FlexSPI 闪存配置，并将 QSPI 链接器大小从 8 MB 更改为 16 MB。 构建完成，未发现任何错误/警告。 问题： 启动后，CPU最终会停止运行：   PC = 0x20005840 ip4_input() at lwip/src/core/ipv4/ip4.c:556   函数 ip4_input() 位于 SRAM 的 0x200056D4 地址，但其内容似乎已损坏：   0x200056D4: 0x4007EEBE 0xBC640C88 ...     但是，QSPI闪存中的相应代码似乎是有效的。 链接器映射显示 .data包含驻留内存的代码：   LMA: 0x080F674C VMA: 0x20000000 Size: 0x1A0E4   启动部分表格规定：   0x080F674C → 0x20000000, length 0x1A0E4   ResetISR() 会调用 SystemInit()，然后调用 data_init() 来执行此初始化操作。 我还通过调试器确认了 SRAM 本身是可读/可写的。 我的主要问题是：为什么即使 QSPI 源映像看起来有效，RAM 驻留代码也会损坏？ 这是否与RW612 启动/RAM 初始化、FlexSPI 配置、缓存/MPU 配置、启动配置或 Type2FR 特定内存配置有关？ 另外，使用SEGGER J-Link 而不是 MCU-Link Pro是否会对启动/调试流程造成任何问题？ 我可以提供.map文件，链接器脚本，startup_rw612.c，flash_config.c，如有需要，请提供调试日志。 谢谢！ 评估板 Re: RW612 / Murata Type 2FR EVK – SRAM-resident code corrupted after boot 嗨，丹尼尔， 谢谢你的回复。 我们之前使用的是 SDK 26.06，但我们的项目配置的是 rdrw612bga 板，而不是您推荐的 FRDM-RW612 配置。 关于迁移指南，是的，我们已经看过了： [NXP FRDM-RW612 模块迁移指南]( https://github.com/NXP-APPCODEHUB/an-frdmrw612-module-migration-guide ) 我们遵循 Murata Type 2FR 的迁移方法，包括更新 W25Q128 (16 MB) 的闪存配置和相应的链接器配置。 但是，我们遇到了一个问题，即应用程序成功启动并开始执行，但最终在 `ip4_input()` 的 `0x20005840` 处停止。我们还发现，原本打算从 SRAM 执行的代码似乎已损坏，而 QSPI 闪存中的相应代码似乎有效。 根据您的建议，我们现在将使用 **26.06 SDK 和 FRDM-RW612 配置**，并按照该基线进行迁移。我们将在此帖中更新我们的结果。 再次感谢您的指导。 问候， 萨克希 Re: RW612 / Murata Type 2FR EVK – SRAM-resident code corrupted after boot 您好， 请问您使用的是哪个SDK版本？ 我建议你使用 FRDM-RW612 的 26.06 版本，而不是 RD 版本。 对了，你已经调查过这个问题了吗？ 问候， 丹尼尔。

MX95：原始视频写入吞吐量限制在约 50MB/s。 您好，我们在将原始相机帧写入文件时遇到了吞吐量/帧速率问题：一旦我们将帧写入存储设备，实际捕获速率就会远低于目标帧速率，即使纯粹的捕获（不写入）以全帧速率运行。我们想了解原因。以下是我们的环境配置。 - 主板：i.MX95 19x19 LPDDR5 EVK - BSP：TechNexion Yocto 5.3 (Whinlatter)，内核 6.18.2 - 摄像头：TechNexion TEVS-AR0234 (MIPI CSI-2) - 通过 media-ctl 确认捕获设备：tevs → csidev-4ad30000.csi → formatter@20 → crossbar → mxc_isi.0→ /dev/video0 ## 测试 1：仅捕获，不写入（基线） 传感器通过以下方式锁定为 30fps： v4l2-ctl -d /dev/v4l-subdev19 --set-subdev-fps pad=0,stream=0,fps=30 gst-launch-1.0-e libcamerasrc！video/x-raw,width=1920,height=1080,format=YUY2,framerate=30/1 !fpsdisplaysink video-sink=fakesink text-overlay=false sync=false 结果：稳定29.98fps，无丢帧。 ## 测试 2：将原始帧写入文件 gst-launch-1.0-e libcamerasrc！video/x-raw,width=1920,height=1080,format=YUY2,framerate=30/1 !文件接收器位置=/tmp/test.yuv 结果：帧率约为 11.7fps（按文件大小/捕获持续时间计算），GStreamer 日志显示反复出现警告： 警告 NxpNeoPipe neo_pipeline.cpp:3175图像0帧丢失！预期 X 实际收到 Y 当帧率未锁定时，预期帧率与实际帧率之间的差距会随着时间的推移而增大；但一旦传感器帧率锁定以匹配目标帧率，该差距就会保持较小（1-2 帧）。 使用 `v4l2src device=/dev/video0` 代替 `libcamerasrc` 重复相同的测试：结果相同，约为 11.7-11.8fps。 在 1280x720 分辨率下重复相同的测试：~28.8fps（~53 MB/s），这转换为与上述 1920x1080 测试类似的 MB/s 上限（~52 MB/s）。 我们想知道，当从 `/dev/video0` (mxc-isi) 捕获的原始帧写入存储时，写入速度限制约为 50 MB/s 是否是当前 BSP/内核版本的预期行为，或者我们是否可能缺少配置设置。如有需要，我们很乐意提供完整的日志、`media-ctl`拓扑输出和设备树信息。 Yocto Project Re: MX95: raw video write throughput limited to ~50MB/s 您好， @JosephAtNXP，感谢您的及时回复。 我想确认一下，根本原因是否在于以下因素。另外，在这种情况下使用实时 Yocto 是否会有帮助？ 捕获的帧存储在通过连续内存分配器 (CMA) 分配的 DMA 缓冲区中。从 ISP 硬件到此内存的 DMA 写入从未成为瓶颈（使用 dd 命令，本地 tmpfs 写入速度高达 819 MB/s，排除了存储介质的限制）。 瓶颈出现在CPU 读取此缓冲区内容的步骤中。VPU 硬件编码器可以通过 DMA 直接读取同一个缓冲区，而不会对性能造成任何影响，这一事实进一步证实了这一点。这有力地表明，瓶颈源于内存缓存属性配置或每次缓冲区出队操作期间维护缓存一致性的成本（例如，缓存失效），而不是总线带宽或存储设备速度的限制。 Re: MX95: raw video write throughput limited to ~50MB/s 您好， 感谢您对恩智浦半导体产品的关注， 这是预期行为，您可以在 Linux 用户指南中看到相关说明。 此外，将帧写入文件系统会产生大量无法实时吸收的数据。在这种情况下，由于应用程序回收缓冲区需要时间，因此会出现周期性丢帧现象。 一种变通方法是在存储捕获的帧之前使用硬件视频编码。 此致

驱动程序文档缺少标题信息 我正在为 S32DS 中的 S32K116 开发一个项目。 到现在为止，我已经弄清楚了 RTD 在 IP 驱动程序与 MCAL/AUTOSAR 之间的工作原理。 由于资源可能有限，我目前将项目范围限定在 IP 驱动程序上。 我还发现，在“组件”视图中右键单击 IP 驱动程序元器件，就可以找到有关该元器件的文档。 但是，我发现文档中并没有列出在使用所描述的功能时，每个驱动程序应该包含哪些标头。 我怎么可能知道这些信息？是否有其他文件或清单对此有明确规定？ Re: driver documentation missing header information 你好 通常，每个 IP 驱动程序的顶级公共标头都遵循以下命名约定： _Ip.h（例如。Flexcan_Ip.h，Lpspi_Ip.h，Clock_Ip.h，Adc_Sar_Ip.h）。该头部信息需要包含在您的应用程序源代码中。 您还可以查看 RTD 中提供的示例，了解需要包含哪些头文件： Julin_AragnM_1-1789513358457.pngJulin_AragnM_1-1789513358457.png FlexCAN -> FlexCAN_Ip.h 平台/中断控制器 -> IntCtrl_Ip.h Port/Siul2 -> Siul2_Port_Ip.h Dio/Siul2 -> Siul2_Dio_Ip.h 您可以在 RTD 安装路径中查找这些头文件："C:\NXP\S32DS.3.x.x\S32DS\software\PlatformSDK_S32K1_S32M24\RTD\ _TS_...\include\" 此致， 朱利安

driver documentation missing header information I am developing a project for a S32K116 inside S32DS. By now I figured out how the RTD works regarding to IP Drivers vs MCAL/AUTOSAR. I will limit my project to the IP Drivers for now due to possible resource constraints. I also figured out that I can find documentation about an IP Driver component by rightclicking on it inside the Components view.  However, I found that it is not listed inside the documentation which headers to include for each driver when using one of the described functions. How am I supposed to know that information? Is there a different document or list where this is specified? Re: driver documentation missing header information Hello  USually, the top-level public header for each IP driver follows the naming convention _Ip.h (e.g. Flexcan_Ip.h, Lpspi_Ip.h, Clock_Ip.h, Adc_Sar_Ip.h). That header is what you include in your source application code. You can also look at the examples provided inside the RTD for which header files to include: Julin_AragnM_1-1789513358457.pngJulin_AragnM_1-1789513358457.png FlexCAN -> FlexCAN_Ip.h Platform/Interrupt Controller -> IntCtrl_Ip.h Port/Siul2 -> Siul2_Port_Ip.h Dio/Siul2 -> Siul2_Dio_Ip.h You can look for these header files inside the RTD installation path: "C:\NXP\S32DS.3.x.x\S32DS\software\PlatformSDK_S32K1_S32M24\RTD\ _TS_...\include\" Best regards, Julián

KE18F512VLH16 ECC RAM シングルビット訂正 先日@sean_dvorscakさんが投稿された記事（ KE1 ECC RAM シングルビット訂正）に関連して、追加の質問があります。 @Celeste_Liuは答えた。 ->> オプションのスクラブを実装する場合は、アクセスを実際のアクセスサイズやスクラブの粒度に基づいてアライメントし、生の MCM_LMFAR 値に盲目的に合わせないでください。また、アドレスを適切にアラインメントし、アクセスサイズが有効であることを確認しない限り、固定4バイトのアクセスは使わないでください。 MCM_LMFATR[PEFSIZE]を使ってアクセスサイズを判定できますか?もしそうなら、これをMCM_LMFARと組み合わせて読み取り・正解・書き込み操作を実装することは可能でしょうか?例えば、MCM_LMFATR[PEFSIZE]が3'b000で8ビットアクセスを示している場合、MCM_LMFARで示されたアドレスから8ビットの読み込みを行い、同じアドレスに8ビットの書き込みをして誤りを訂正することは可能でしょうか?同様に、MCM_LMFATR[PEFSIZE]が3'b010で32ビットアクセスを示している場合、アライメントを気にせずにMCM_LMFARで示されたアドレスに32ビット書き込みを行うことはできますか? Re: KE18F512VLH16 ECC RAM Single Bit Correction こんにちは、@rseigle77 さん。 あなたの投稿を拝見しました。この件について少し調査させてください。詳しい情報が分かり次第、改めてご連絡いたします。 BR セレステ Re: KE18F512VLH16 ECC RAM Single Bit Correction こんにちは@Celeste_Liu - P7は最終アプリケーションの名前です。 Re: KE18F512VLH16 ECC RAM Single Bit Correction こんにちは、@rseigle77 さん。 ご質問につきましては、社内の担当チームに調査を依頼する必要があります。当社の手続きに従い、 最終的な申請 名を記載してください。 ご協力ありがとうございました。 BR セレステ Re: KE18F512VLH16 ECC RAM Single Bit Correction こんにちは、 @Celeste_Liu さん、この件について何か進展はありますか？

MPC5775B – アプリケーションからRAppIDへのブートローダー移行 こんにちは、NXPチームの皆さん。私はCANフラッシングに RAppIDブートローダーを組み合わせたCAN フラッシングをMPC5775Bしています。 RAppID FBLのソースコードは持っていないので、既存のFBLを修正することはできません。 実行中のアプリケーションが既存のRAppID FBLにプログラミングモードに入るよう要求するサポートされたメカニズムはありますか? もしそうなら、MPC5775Bに必要なアプリケーション→FBLエントリシーケンスは何ですか? これには特定のリセットや起動機構が必要なのでしょうか、それともRAppIDはアプリケーションからFBLを要求する別の方法を提供しているのでしょうか? Re: MPC5775B – Application to RAppID Bootloader transition こんにちは、 RAppID FBLには、実行中のアプリケーションがプログラム的にFBLエントリを要求するための組み込みかつ文書化されたAPIはありません。MPC57xx用のRAppIDブートローダーは、クローズドバイナリでフラッシュ常駐ブートローダー(事前コンパイル済みの.rbfとして配布)ですソースコードが提供されておらず、変更も不可能なファイル） これをトリガーする標準的なメカニズムは、アプリケーションからのランタイム呼び出しではなく、リセット+ブートタイムフラグチェックです。 よろしくお願いいたします。 ピーター Re: MPC5775B – Application to RAppID Bootloader transition ありがとう、ピーター。リセット処理に続いて起動時のフラグチェックが行われる仕組みだと理解しました。RAppID FBLのソースコードがない場合は、MPC5775BチェックのRAppID FBLにどのようなブートタイムフラグや条件があるのか、またアプリケーションがリセット前にどのように設定・要求できるのか、説明していただけますか? これは特定のRAMアドレス/マジック値、リセット原因条件、設定フィールド、または別のメカニズムでしょうか？もしこのフラグを設定するためのアプリケーション側の手順やドキュメントがあれば、ぜひ教えていただけませんか?

Some suggestions for Gui-guider 2.0 I hope Gui-guider 2.0 will add an option in the settings to control whether timestamps in the generated files are enabled or disabled. Then each generated page (screen) will have a corresponding gg_event_screen.c file, even if my page does not register any events. We want to prevent any event content from being generated when no events are registered. Additionally, I would like a mechanism to selectively include some images or resources that are not currently displayed in the project. Although it is possible to include images and fonts from the ghost page into the project, it is not very elegant. Regarding fonts, there is currently a setting in the settings to control the default generation range of all fonts. Hopefully, in the future, we can control the generation range of all fonts. Acknowledgments 回复： Gui-guider 2.0的一些建议 Hi @Xu_556678 , Thank you very much for your feedback. These suggestions are invaluable to us, and we will consider making corresponding optimizations and improvements in future releases. We hope the GUI Guider will be helpful to your work. Please feel free to provide any feedback or suggestions you may have in the future. Best Regards, Wenbin Re: Gui-guider 2.0的一些建议 Hi @Xu_556678, I would like to add an input about a workaround regarding some of your requests, specifically regarding the generation of images and fonts. While adding them to a ghost page technically works to enable GUI Guider to automatically generate the images and fonts, you can also add them to the "resource" panel, and click convert: EdwinHz_1-1789494348483.pngEdwinHz_1-1789494348483.png This Image Converter feature allows you to generate an output file for any supported images. The default path is set to the 'custom' folder, but you can change it to the same one where other images are automatically generated to keep them all together. Even though this is technically a manual process, the advantage is that you can select multiple images and convert them all at once, so if you do so with all of your images at once, you would only need to do this process once. This way, you can skip the current workaround of doing a ghost screen that only adds extra code for screens that won't even be used. EdwinHz_2-1789494766306.pngEdwinHz_2-1789494766306.png Additionally, for the granular control over the generation range of individual fonts, this can be controlled with the Font Converter. When doing the same process described above, just with a font instead of an image. The prompted window panel will show an option to specify the range of the selected font, allowing for the generation of specific ranges on specific fonts. EdwinHz_3-1789494865236.pngEdwinHz_3-1789494865236.png Hopefully this input helps on your current GUI Guider development. If you have any further inquiries or requests, definitely let us know! BR, Edwin.

How to burn HAB firmware on IMX6ULL about USB  We use IMX6ULL and want to implement the secure boot function. The current SD boot mode has been run through, the development board has written SRK, and the firmware has also been signed. Then we also executed the close operation (echo 0x02>HW_OCOTP_CFG5). After burning, the normal print information is as follows: Secure boot enabled HAB Configuration: 0xcc, HAB State: 0x99 However, when the same firmware was placed in the mfgtools tool and burned using USB, it was found that the board could not enter the burning system. The tool stops running, and the debug serial port does not have any print information. rxq_0-1789457007595.pngrxq_0-1789457007595.png The firmware in the red box,% board_file%/u-boot.imx and firmware/zImage are signed firmware. MfgTool.log records that the firmware has been imported. After the normal process Jumping to OS image, it should be the firmware that was started to import, but in fact, there is no print information on the debug serial port rxq_1-1789457333755.pngrxq_1-1789457333755.png Why is it normal for SD card to start, but not for USB？ What should we do to support USB burning? The attachment is the secure boot production process started by our SD

如何使用 USB 将 HAB 固件烧录到 IMX6ULL 上 我们使用 IMX6ULL，并且想要实现安全启动功能。 当前 SD 卡启动模式已运行完毕，开发板已写入 SRK，固件也已签名。然后我们还执行了关闭操作（echo 0x02>HW_OCOTP_CFG5）。 刻录完成后，正常的打印信息如下： 已启用安全启动 HAB 配置：0xcc，HAB 状态：0x99 然而，当将相同的固件放入 mfgtools 工具并使用 USB 进行烧录时，发现电路板无法进入烧录系统。 工具停止运行，调试串口没有任何打印信息。 rxq_0-1789457007595.pngrxq_0-1789457007595.png 红色方框中的固件、%board_file%/u-boot.imx 和 firmware/zImage 都是已签名的固件。 MfgTool.log 记录显示固件已导入。正常跳转到操作系统镜像后，应该开始导入固件，但实际上，调试串口上没有任何打印信息。 rxq_1-1789457333755.pngrxq_1-1789457333755.png 为什么SD卡可以正常启动，而USB却不行？ 我们应该如何做才能支持U盘刻录？附件是我们SD启动的安全启动生产流程。

EL2 Monitor: Simplifying Software Partitioning for Automotive Safety Systems The automotive industry is undergoing a fundamental architectural shift. Where vehicles once relied on dozens of dedicated ECUs — one function, one controller — modern designs are consolidating multiple software functions onto a single, powerful processor. This consolidation reduces cost, weight, and complexity, but it introduces a critical challenge: how do you run a safety-critical AUTOSAR brake control application on the same chip as a less-critical body control stack, and guarantee they can never interfere with each other? Full hypervisors are one answer — but they come with significant drawbacks. They are complex to integrate, expensive to license, difficult to certify to ISO 26262, and introduce latency that real-time systems cannot tolerate. NXP's EL2 Monitor (EL2M) was designed to solve exactly this problem: delivering robust, hardware-enforced software isolation with the simplicity, determinism, and safety pedigree that automotive programs demand. What Is EL2 Monitor? EL2 Monitor is a partitioning hypervisor that runs at Exception Level 2 (EL2) — the hypervisor privilege level defined by the Arm® architecture — on Arm® Cortex®-R52 cores. It sits between the hardware and the application software, acting as a lightweight isolation layer that enforces strict boundaries between software partitions running on the same processor. In simple terms: EL2 Monitor takes a single physical processor and divides it into independent, isolated software environments — called R52 partitions — each running its own RTOS instance with exclusive access to its assigned resources. A fault, crash, or security breach in one partition cannot affect any other. Unlike a full hypervisor, EL2 Monitor does not perform CPU scheduling, device virtualization, or dynamic resource management. Its scope is deliberately narrow: isolate partitions, protect shared hardware resources, and do so in a way that is statically configured, deterministic, and certifiable to ASIL D. This focused design philosophy is what makes it practical for production automotive programs. The Core Problem: The Shared GIC Distributor To understand why EL2 Monitor exists, it helps to understand a specific hardware constraint of the Arm Cortex-R52 architecture. In an R52-based Real-Time Unit (RTU), every two or four cores share a single GIC (Generic Interrupt Controller) Distributor — the hardware block that routes interrupts to cores. Without protection, any software running on one core has direct access to the GIC Distributor and could — accidentally or maliciously — reroute or disable interrupts belonging to another core's partition. This makes true isolation impossible without a dedicated software layer at EL2. EL2 Monitor fills this gap. It intercepts all GIC Distributor accesses from partitions and virtualizes them, giving each partition its own exclusive Virtual GIC Distributor while the real hardware GIC remains protected. nxf94150_1-1789390949734.png How It Works: Two Virtualization Modes   Trap & Emulate GIC Distributor accesses from EL1 software are automatically trapped to EL2, where EL2 Monitor validates and emulates them. The EL1 application is completely unaware of the virtualization — it behaves as if it has exclusive hardware access. Access operations complete in < 3 µs, making this mode suitable for standard AUTOSAR applications that require zero code changes.   Paravirtualization For performance-sensitive applications, EL2 Monitor provides ready-to-use Arm CMSIS GIC Driver APIs. The EL1 software calls these APIs directly instead of accessing GIC hardware registers. This cooperative approach achieves < 1.5 µs latency — half that of full emulation — while also reducing memory usage and development time. nxf94150_2-1789391007259.png Hardware-Enforced Memory Protection Beyond GIC virtualization, EL2 Monitor uses the EL2 Memory Protection Unit (MPU) to enforce strict memory boundaries between partitions in hardware. Each partition is assigned its own memory regions at configuration time. Even if an EL1 guest OS is compromised, it cannot access memory belonging to another partition. This is complemented by NXP's XRDC (Extended Resource Domain Controller) silicon feature, creating a layered hardware + software protection architecture that is unique to NXP's S32 platform. MRU Channel Isolation EL2 Monitor also virtualizes MRU (Messaging Resource Unit) channels within each R52 partition. Each software entity running at a lower privilege level accesses the MRU through its own dedicated virtualized instance — inter-core communication channels cannot be accessed or corrupted by other software entities. MRU handlers are serviced in < 1.5 µs. Static, Deterministic Configuration All partition assignments — CPU cores, memory regions, peripherals, interrupt routing — are defined at build time using the EB Tresos or S32CT configuration plugins. There is no runtime reconfiguration, no dynamic scheduling, and no hidden shared state. This static model makes system behavior fully predictable, simplifies safety analysis, and keeps the trusted computing base small and auditable. Safety and Quality EL2 Monitor is qualified to ASIL D per ISO 26262:2018 — the highest automotive functional safety integrity level. Development follows NXP's Software Development Process, which is Automotive SPICE 3.1 · IATF 16949:2016 · ISO 26262:2018 · ISO 21434:2021 · ISO 9001:2015 compliant. The complete package delivered to customers includes: Quality Package: SW Traceability Matrix (Req → Design → Code → Tests), Test Specs & Reports at all levels, MISRA/CERT-C/CWE Static Analysis, Code Coverage, Benchmark & Memory Reports Safety Package: Safety Manual, FMEA Software Package: Source code, Release Notes, User Manual, SBOM Development teams do not need to perform their own safety analysis of the partitioning layer — NXP provides the complete collateral, significantly reducing the certification effort for the overall system. Developer Experience: Fits Into Your Existing Workflow EB Tresos and S32CT plugins for AUTOSAR-based configuration S32 Design Studio (S32DS) for build, debug, and deployment Multi-compiler support for toolchain flexibility Sample application included to accelerate first-time integration Available via the NXP software distribution portal (Flexera) 6 on-demand training videos on nxp.com: Hello World, Configuration & Build, RTOS Integration, Download & Install, Tools & Compilers, Support Channels Supported Platforms nxf94150_3-1789392707431.png Why EL2 Monitor — and Why Now? The industry trend toward software-defined vehicles and centralized compute is accelerating. Zonal and domain controllers are replacing distributed ECU networks, and the software running on these controllers is growing in both complexity and safety criticality. The need for a reliable, certified, and cost-effective partitioning solution has never been more urgent. ASIL D certified — highest automotive safety integrity level, full collateral included Simpler than a full hypervisor — static, deterministic, minimal trusted computing base Unique NXP HW+SW stack — XRDC hardware isolation + EL2 Monitor software protection Sub-1.5 µs performance — paravirtualized GIC access Production-ready — full safety collateral, AUTOSAR toolchain integration, multi-platform Explore EL2 Monitor and discover how NXP's partitioning software can help you consolidate your automotive software architecture — safely, simply, and at no additional cost. Learn more about EL2 Monitor on nxp.com » Daniel Hermenczi Product Owner, EL2 Monitor — System Services, Automotive & Edge Solutions, NXP Semiconductors Daniel is a software project manager and product owner for EL2 Monitor and IPCF at NXP Semiconductors, driving roadmap execution and customer deliveries for automotive partitioning and inter-platform communication software. He is based in Sibiu, Romania. As vehicles consolidate more software onto fewer chips, keeping safety-critical functions truly isolated is no longer optional. EL2 Monitor delivers hardware-enforced partitioning for Arm® Cortex®-R52 — without the complexity of a full hypervisor.