SPI Bus Overview (Japanese blog)
0. Table of Contents
table of contents
What is SPI?
1.1 History and specifications
1.2 Controller/Target or Main/Subnode (Sub)
Physical/Electrical Characteristics
2.1 Number of signal lines: Signal names
2.2 Push-pull. High impedance state when not transmitting
2.3 Clock Frequency
protocol
3.1 Mode
3.2 Data Transfer
Connection Topology
4.1 Parallel connection and daisy chain with chip select
Reference materials
1. What is SPI?
1.1 History and specifications
The SPI bus is a serial bus specification proposed by Motorola (now NXP Semiconductors) in the United States. The specification is said to have been established in the mid-1980s. SPI stands for " Serial Peripheral Interface " and was developed as a four-wire serial bus used to connect processors and peripheral chips. A three-wire SPI bus is also available as a derivative specification, but the original four-wire system is the basis.
SPI has several variations in communication methods, such as signal polarity and data synchronization timing settings, so you need to be aware of this when using it.
Like I²C, SPI is used to exchange data between chips, but each has its own advantages and disadvantages, as summarized in [Table 1].
SPI is used for applications that require faster data transfer . This is due to the difference in electrical specifications: I²C drives signals using open drain, while SPI drives signals using push-pull , making it easier to achieve higher speeds. Furthermore, in terms of data transfer speed, SPI is characterized by its ability to perform full-duplex communication, which allows simultaneous transmission and reception.
On the other hand, SPI also has some disadvantages. The transfer data length and clock polarity are specified for each destination device, making it difficult to mix multiple types of devices. Also, when connecting multiple devices of the same type, a chip select signal is required for each device, which increases the number of signal lines, and when cascading devices, the data transfer length must be adjusted.
I²C
SPI
Number of lines
2 Data: SDA Clock: SCL
4 Data: SDO, SDI (MOSI, MISO) Clock: SCLK Chip select: CS
speed
~400kHz 1MHz, 3.4MHz, 5MHz depending on mode
Several hundred kHz to several tens of MHz
Communication Direction
bidirectional half duplex
Bidirectional full duplex
Connection Method
Multidrop (parallel) Multiple Controllers vs. Multiple Targets
Parallel or Daisy Chain Single Controller vs. Multiple Targets
Signal Drive
Open Drain (Pull-up resistor required)
Push-pull
Table 1: Comparison of I²C and SPI
1.2 Controller/Target or Main/Subnode (Sub)
In SPI, transfers are also made in a master-slave relationship. Until now, the terms master and slave were commonly used, but these have now been changed to controller and target.
They are also called main/subnodes (sub), retaining the initials "M/S" from the previous role names. From now on, this blog will deliberately use the terms main/subnodes (sub).
In SPI, multiple mains cannot exist. Communication always takes place between one main and one or more targets.
2. Physical/Electrical Characteristics
2.1 Number of signal lines: Signal names
The SPI bus is a four-wire synchronous serial interface. A synchronous serial interface is a method of sending and receiving data in synchronization with a clock signal, using one of the signal lines as the clock.
There are two signal lines for data. One is used for data from the main to the sub and the other is used for data from the sub to the main. The other is a signal called chip select. SPI does not have a way to specify an address to specify the transfer target. Therefore, the chip select signal is used to specify the target device [Figure 1].
Signal names may be called by a variety of names. The following signal names are those used by OSHWA :
SDO : Data output
SDI : Data input
SCK : Serial clock
CS : Chip Select: CS
In the above example, the names SDO and SDI are based on the direction of data input/output on each chip. In this case, the names of the pins are clear, but it is inconvenient to indicate the signal direction between the main and sub.
Instead, the following signal names are commonly used on circuit diagrams, etc. This blog will stick to these terms.
MOSI : Data from main to sub (Main Out Sub In)
MISO : Data from sub to main (Main In Sub Out)
SCLK : Serial clock
CS : Chip Select: CS
Of these signals, only MISO is a signal from the sub to the main, and all others are signals from the main to the sub. The signal direction does not change during communication.
スクリーンショット 2025-02-03 6.18.59.png Figure 1: Controller and target. Signal names
To save on the number of signals, for example when communication is only one way, one of the data lines may be omitted.
There are also targets that allow transmission and reception to be time-multiplexed, allowing the use of only one data line. In this case, on the main side, MOSI/MISO are shorted using a resistor to combine the signals.
2.2 Push-pull. High impedance state when not transmitting
Signals are output in a push-pull fashion. When no data is being transferred, the MOSI and MISO outputs are placed in a high-impedance state. This is to prevent interference with other communications when multiple subnodes are connected in parallel.
The signal voltage is determined by the sub-node device, so it must be adjusted accordingly. If the voltage differs between the main and sub-nodes, voltage conversion is required.
2.3 Clock Frequency
There are no specific regulations regarding clock frequencies. Clocks in the hundreds of kHz to several MHz range are typically used, with the upper limit determined by the specifications of the subnode device. Applications requiring high-rate data transfer may use clocks of several tens of MHz. In addition, in memory devices, there are also applications where multiple MOSI and MISO data lines are used to increase the transfer rate.
3. Protocol
There are no strict rules regarding the protocol that determines the data transfer procedure, and it is freely determined for each subnode device. The main microcontroller has settings to support various subnode devices.
The basic transfer procedure begins by asserting CS connected to the destination subnode. The transfer ends when CS is deasserted. CS is asserted and deasserted using a LOW and HIGH signal, but the polarity is dictated by the subnode device specifications. Many devices use MSB first for data bit ordering, but there are exceptions to this. There is also no specific rule about the number of bits used as the transfer unit. I have seen explanations that say it is 2 to 16 bits, but this is not the case as there are subnodes that use larger bit lengths as units (for example, 64 bits).
3.1 Mode
SPI has settings called " modes ," which refer to combinations of clock polarity and edge selection, and there are four modes with two settings each [Figure 2].
Clock polarity is a setting called CPOL , which determines whether SCLK is LOW or HIGH when no data is being transferred. On the main side, setting this to 0 will make it LOW, and 1 will make it HIGH. Edge selection (phase) is called CPHA . This setting determines whether data is latched (taken in) on the first or second clock edge. A setting of 0 selects the first edge, and a setting of 1 selects the second edge. CPOL and CPHA can sometimes be combined to represent modes 0 to 3 [Table 2].
In addition, please note that there are also subnodes with reversed chip select polarity.
スクリーンショット 2025-02-03 7.42.56.png Figure 2: Mode (CPOL, CPHA)
CPOL
CPHA
mode=0
0
0
mode=1
0
1
mode=2
1
0
mode=3
1
1
Table 2: Modes and CPOL, CPHA
What is the "edge that latches data"?
Data is sent and received in sync with the clock, but data changes on either the rising or falling edge of the clock. Figure 3 shows an example of data changing on the falling edge. The main side changes its MOSI output, and the subnode side changes its MISO output, in time with the falling edge of the SCLK output by the main side device. The next data changes on the next falling edge, but until then the state remains stable. The rising edge of the clock occurs exactly during this period, so data is captured from each other in time with this timing. This is the "latch edge."
スクリーンショット 2025-02-03 6.54.45.png
Figure 3: Data (MOSI/MISO) and clock (SCLK) synchronization
3.2 Data Transfer
After the chip select is asserted, data is sent and received in synchronization with the clock. When the subnode receives that its own chip select is asserted, it takes in and outputs data in synchronization with the clock.
[Figure 4] is an example of an SPI transfer. Data is exchanged in accordance with the clock while CS is asserted. Those familiar with logic circuits will see that this is achieved using a simple circuit using a shift register.
スクリーンショット 2025-02-03 7.55.53.png Figure 4: Example of SPI transfer
4. Connection Topology
4.1 Parallel connection and daisy chain with chip select
Multiple subnodes are connected as shown in [Figure 5]. A chip select is provided for each subnode, and communication is carried out by specifying the sender and receiver using each signal. Alternatively, to reduce the number of CS signals, a daisy-chain connection can be used, and communication can be carried out by treating the subnodes as a single subnode with an extended bit length [Figure 6].
As mentioned earlier, care must be taken when connecting multiple types of subnodes to the same SPI bus. As mentioned earlier, the "mode," chip select polarity, and data bit length may not be the same. For this reason, you may need to switch settings or make adjustments in the hardware each time you communicate with each subnode.
スクリーンショット 2025-02-03 8.25.09.png
Figure 5: Parallel connection
スクリーンショット 2025-02-03 8.25.21.png
Figure 6: Daisy chain connection
5. Reference materials
OSHWA Role and Signal Names [English]
Wikipedia page on "SPI" : Signal names and main/subnode names in this blog are based on this description .
Interface March 2024 issue (CQ Publishing) : Special feature "Serial communication from scratch [UART/I2C/SPI with Pico]"
NXP System Management I²C, I3C, SPI Selector Guide
NXP Community Blog: I3C: The Next Serial Bus
NXP Community Blog: An Overview of the I²C Bus
[Originally published in Interface, March 2024 issue (CQ Publishing), "Building I2C & SPI from Scratch ④... SPI Communication Standards," pp. 71-73. The section explaining the communication specifications has been excerpted and revised for this blog post.]
Change history: 2025-02-03: First Edition 2025-02-25: Added a link to the "NXP System Management I²C, I3C, SPI Selector Guide" in section "5. Reference Materials". 2025-05-01: Corrected the table of contents (deleted items), corrected the item name in Section 2.2. 2026-07-24: Fixed broken links in "2.1 Number of Signal Lines: Signal Names" and "5. Reference Materials" to "OSHWA Role Names and Signal Names".
=========================
We are currently unable to respond to comments in the "Comment" section of this post. We apologize for the inconvenience, but when making inquiries, please refer to `` Technical Questions to NXP - How to Contact Us( Japanese Blog) ''. (If you are already an NXP distributor or have a relationship with NXP, you may ask the person in charge directly.)
SPI bus used for communication between microcontrollers/processors and peripheral devices.
Although this serial bus is so commonly used, I would like to take this opportunity to summarize its origins. communication standards Interface Japanese blog
記事全体を表示
