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******************************************************************************** * Detailed Description: * This example demonstrates how to configure CGM )clock generation module) * and supply by clock all main peripherals. * Example demonstrate FCCU fake fault injection for fault 15. * ------------------------------------------------------------------------------ * Test HW: MPC57xx EVB + MPC5777M minimodule * Maskset: 0N50N * Target : internal_FLASH * Fsys: 200 MHz PLL * ******************************************************************************** Revision History: 1.0 Nov-04-2014 b21190(Vlna Peter) Initial Version 1.1 Feb-04-2016 b21190(Vlna Peter) Fixed Clock configuration 1.2 Feb-06-2017 b21190(Vlna Peter) FCCU fake fault injection *******************************************************************************/

******************************************************************************** * Detailed Description: * This example demonstrate how to configure CGM (clock generation module) * and supply by clock all main peripherals. At maximum available frequency for system * which is 265MHz. * ------------------------------------------------------------------------------ * Test HW: MPC57xx Motherboard + MPC5775K_356DS minimodule, MPC5775K, * Maskset: 0N76P * Target : internal_FLASH * Fsys: 265 MHz PLL0 * ******************************************************************************** Revision History: 1.0 Apr-15-2015 b21190(Vlna Peter) Initial Version *******************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals. * * This example shows, how to use ADC with ETimer to dim LED diode. Voltage on * the output of the trimmer is converted to digital value which is used to * control duty cycle of the PWM generated by ETimer. * * ------------------------------------------------------------------------------ * Test HW: MPC5775K-356DS, MPC57xx Motherboard * MCU: PPC5775KMMY3A 0N76P * Terminal: * Fsys: PLL0 266MHz * Z4 Core 133MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, release mode) * EVB connection: UserLED1 connected to P19.4, connected jumper j53 * * * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * LINFlex UART mode transmit and receive with interrupts * * * ------------------------------------------------------------------------------ * Test HW: MPC5775K-356DS, MPC57xx Motherboard * MCU: PPC5775KMMY3A 0N38M * Terminal: 19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys: PLL0 266MHz * Z4 Core 133MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, release mode) * EVB connection: J14.2 to P12.6 Connect LINFlexD_0 RXD to main RS232 * J13.2 to P12.7 Connect LINFlexD_0 TXD to main RS232 * ********************************************************************************

******************************************************************************** * Detailed Description: * This example implements ADC driver and demonstrated the usage of ADC in BCTU mode. * When PIT timer exceeds the trigger is sent to BCTU and BCTU triggers ADC_0 conversion. ******************************************************************************** * Test HW: MPC57xx * Maskset: 1N81M * Target : SRAM * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Nov-20-2014 b21190(Vlna Peter) Added SWT_0 dissabling in startup 1.3 Mar-10-2016 b21190(Vlna Peter) Fixed clock configuraion for PLL 1.4 Mar-10-2016 b21190(Vlna Peter) Added ADC driver 1.5 Mar-16-2016 b21190(Vlna Peter) Added BCTU and PIT drivers *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts, blinking * one LED by core e200z4a, second by core e200z4b, third by core e200z2, * initializes and display notice via UART terminal and then terminal ECHO. * * ------------------------------------------------------------------------------ * Test HW: MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU: PPC5748GMMN6A 1N81M * Fsys: 160 MHz PLL * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on LINFlexD_2 * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts and initializes software watchdog with window mode * allowed. Window mode is set for 2.5 ms. PIT timer is set to service SWT each * 8 ms, which is inside the window. * * * ------------------------------------------------------------------------------ * Test HW: XPC560B 100LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU: PPC5604BE MLL 1M27V * Fsys: 64 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL1 to maximum allowed freq. PLL1 is system frequency, * PLL0 in initialized to 50MHz * initializes peripherals clock (MOTC_CLK is set to 5MHz) * initializes ETimer to count mode providing delay * initializes interrupts, blinking one LED by ETimer interrupt, * * * * Test HW: X-MPC5744PE257DC, MPC57xx motherboard * MCU: PPC5744PFMMM8 1N65H * Fsys: 200 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, release mode) * EVB connection: User LED 1 connected to A0 (P8.0), * * * ------------------------------------------------------------------------------

******************************************************************************** * Detailed Description: * * eMIOS0 ch0 is set to SAIC mode generating interrupt on falling edge. * The IGF ch16, connected to eMIOSch0, is set to filter low pulses <1.5us * Intergation filter type is used for falling edge with given threshold. * eMIOS interrupt is called if input signal low pulse is longer than 1.5us. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * * eMIOS ch0 (PortG P14-16)--> connect external pulse signal * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demostrates how to configure CGM )clock generation module) * and supply by clock all main peripherals. * * ------------------------------------------------------------------------------ * Test HW: Test HW: MPC57xx Motherboard + MPC5777M_512DS minimodule, MPC5777M, * Maskset: 0N75H * Target : internal_FLASH * Fsys: 200 MHz PLL * ******************************************************************************** Revision History: 1.0 Nov-04-2014 b21190(Vlna Peter) Initial Version 1.1 Feb-04-2016 b21190(Vlna Peter) Fixed Clock configuration *******************************************************************************

******************************************************************************** * Detailed Description: * * Application initializes SPI0 module as a master and SPI2 module as a slave. * Data are sent from master to slave and from slave to master. Simple * polling method is used to determine, when data were sent/received. * Received data are saved to global variables. * * ------------------------------------------------------------------------------ * Test HW: MPC5777M-512DS, MPC57xx Motherboard * MCU: PPC5777MQMVA8 0N78H * Fsys: PLL0 300MHz * PLL1 300MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, debug_ram mode, release mode) * EVB connection: P18.12 to P14.13 (CS_0) * P11.4 to P8.13 (SCK) * P11.1 to P11.5 (SOUT - SIN) * P11.8 to P12.9 (SIN - SOUT) * * ********************************************************************************

******************************************************************************** * Detailed Description: * Used flash driver: MPC5700 C55FG Flash Standard Software Driver (REV 1.1.0) * http://www.nxp.com/files/product/software/C55_JDP_SSD.exe * * This example checks four large 256KB flash blocks at address 0x0100_0000 - * 0x010F_FFFF. * Some random data are placed to this section (constant "flash_data[]"), so the * s-record is not empty. * It is necessary to use off-line MISR_C55.exe tool which calculates MISR * values for selected flash blocks. See the "MISR gen" folder included in this * project. File "core0.run" is s-record file which is used for calculation. It * contains the data (constant "flash_data[]") placed to the selected blocks. * "misr.bat" file shows how to call the calculator. * "output.txt" contains the result of this operation - the MISR values. * Once this is done, initialize the SSD drivers, unlock blocks which are going * to be checked and run the FlashArrayIntegrityCheck function. * Notice that the code must be executed from RAM. We cannot access the flash * during this operation. If the operation is successful, FlashCheckStatus will * return opResult C55_OK if the MISR values are equal. It will return * C55_ERROR_MISMATCH if the MISR values are not equal, i.e. the flash is * corrupted and the content does not correspond to s-record file. * ------------------------------------------------------------------------------ * Test HW: X-MPC5744PE257DC, MPC57xx motherboard * MCU: PPC5744PFMMM8 1N65H * Fsys: 200 MHz PLL * Debugger: Lauterbach Trace32 * Target: internal_FLASH * ********************************************************************************

******************************************************************************** * File main.c * Owner David Tosenovjan * Version 0.1 * Date May-31-2023 * Classification General Business Information ******************************************************************************** * Detailed Description: * The purpose of this example is show how to keep data in SRAM memory over SW * reset. * INIT_Derivative (file MPC5607B_HWInit.c) is modified to skip ECC RAM * initialization for SW reset source. Linker command file defines my_ram * section, a data being kept over reset are accesses as address pointer to this * location. After initialization SW resets are periodically triggered, * incrementing data on address test_address_3. * * ------------------------------------------------------------------------------ * Test HW: XPC5607B 176LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU: PPC5607BMLUAM03Y * Terminal: 19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * Fsys: 64/48 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: none * ********************************************************************************

/******************************************************************************** Detailed Description: Configures the FlexCAN 0 to transmit and receive a CAN message Baudrate to is set to 500kbps. In this config, RXFIFO is used to receive a messages. 8 filter elements are defined in the RXFIFO table. Both standard and extended IDs are used. DMA is enabled in component inspector to read RXFIFO. MB9 is moreover used to receive a message with given standard ID and MB8 is used to transmit a message upon buttons press. The callback function is installed as well and is it called each time message is received in MB9, RXFIFO or message is transmitted. * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5748G * MCU: PPC5748GSMKU6 0N78S * Target: Debug_FLASH * EVB connection: PCAN-View with PCAN-USB Pro connected to CAN port P5 * Compiler: S32DS.Power.2.1 * SDK release: S32_SDK_S32PA_RTM_3.0.3 * Debugger: OpenSDA, Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date Author Description of Changes 1.0 02-May-2023 Petr Stancik Initial version, based on SDK demo example *******************************************************************************/

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to maintain SRAM data over reset types * that is not destroying SRAM content (for instance software reset) * Changes are done in linker command files (adding new section), because * .BSS and .SBSS section are always cleared by compiler. * Another changes are done in init.s file where SIU_RSR reset flags are * tested and RAM is initialized only conditionally. * Variable 'test_variable' is maintained over SW reset and then incremented * once per reset cycle and displayed over terminal window. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and converts channel 145 * (bandgap voltage chosen as a source for the channel) and displays it into * terminal window. No external connection required excluding terminal via eSCI. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts, blinking * one LED by Core0, second by Core1 (by interrupt), initializes and display * notice via UART terminal and then terminal ECHO. * An example re-configures default clock setting to first and then second * configuration to shows necessary steps to perform this transtition. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) ********************************************************************************