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This document gives a basic insight into bit timings relationship and provide easy step-by-step guide to calculate CAN bit timing parameters for desired baudrate.
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******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and converts channel 146 * (voltage level of VDD) to check core voltage level and displays it into * terminal window. No external connection required excluding terminal via eSCI. * * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************
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******************************************************************************** * Detailed Description: * * The example shows how to initialize 3 submodules to generate 120° phase shift * between submodules. * CNTR register of each submodule is initialized with shifted value when PWM * generators are disabled using FORCE feature. * * ------------------------------------------------------------------------------ * Test HW:  MPC5744P (MPC5744P-257DS + MPC577xx motherboard) * Maskset:  1N15P * Target :  internal_FLASH, RAM * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P8.12    - A[11] .. FlexPWM A[0] output * P8.11    - A[10] .. FlexPWM B[0] output * P8.13    - A[12] .. FlexPWM A[2] output * P8.14    - A[13] .. FlexPWM B[2] output * P10.8    - C[7] .. FlexPWM A[1] output * P10.7    - C[6] .. FlexPWM B[1] output * ********************************************************************************
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This simple example shows usage of the FlexPWM module on the TRK board. If a PWM output is connected to the LED you can see its dimming.   Regards, Petr   ******************************************************************************** * Detailed Description: * * This example shows usage of FlexPWM module. * The Submodule0 is set to generate independent PWMA and PWMB signals and vary * its duty cycles. The PWMX is also enabled as output and is set for fixed 50% * duty. *   * You can remove LED_EN jumpers and connect FlexPWM A an B outputs to LEDs to see * its dimming. * * ------------------------------------------------------------------------------ * Test HW: TRK-MPC5604P * Maskset:  0M36W * Target : internal_RAM * Terminal: no * Fsys:     64 MHz with 8 MHz XOSC reference * Debugger: IDCPPCNEXUS * * TRK board connection: * * P4.10 - D[9]  .. FlexPWM X[0] output * P1.11 - A[10] .. FlexPWM B[0] output * P1.12 - A[11] .. FlexPWM A[0] output * *   ********************************************************************************
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This simple example shows the ADC setting for the scan mode and usage of Trimmer on TRK-MPC5604P board. Use Trimmer to dim the LED1.   Regards, Petr     ******************************************************************************** * Detailed Description: * * ADC testing and usage of Trimmer on TRK board * * ------------------------------------------------------------------------------ * Test HW:  TRK-MPC5604P * Maskset:  0M36W * Target :  internal_RAM * Terminal: no * Fsys:     64 MHz with 8 MHz XOSC reference * EVB connection: * * Use Trimmer to dim the LED1 * * NOTE! Be sure the ADC is powered, J21 5V jumper ON * ********************************************************************************
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******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit * ECC error in internal FLASH (user must choose it in the option at the end of * main function). * Flash over-programming is used to generate a non-correctable (or single-bit) * ECC error in FLASH. The bad data is accessed then, so the IVOR1 exception (or * ERM combined interrupt service routine) is generated and handled. * Example also offers useful macros for EIM and ERM modules. * The example displays notices in the terminal window (USBtoUART bridge J21) * (19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  eSCI_A is USBtoUART bridge (connector J21) * ********************************************************************************
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******************************************************************************** * Detailed Description: * * Application performs basic initialization, setup PLLs. * DSPI_A is configured as master using DMA to send/receive 8 words. * * Two DMA descriptors are initialized: * - TCD[32] master transmit * - TCD[33] master receive * * * EVB connection: * * Do external loopback to connect SOUT to SIN * * PM6 ... SCKA * PM7 ... SINA * PM8 ... SOUTA * PM13... PCSA0 ** * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 3N45H * Fsys: PLL1 = core_clk = 260MHz, PLL0 = 200MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * *********************************************************************************
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******************************************************************************** * Detailed Description:   * Example shows MCU's temperature measurement with the help of TSENS. * Calibration constants for TSENS are read from TSENS registers and * eQADC is set to measure Vbg and TSENS outputs. eQADC calibration is also done. * Calculated internal temperature can be displayed on the Terminal. * * See results on PC terminal (19200, 8N1, None). You should see following text * (with different values for sure) * *    fsys = 150MHz * *    TSENS temperature calculation * *    Calibration constants read from TSENS registers * *    T_LOW = 25 *    T_HIGH = 145 *    TSENS_CODE_T_LOW = 5441 *    TSENS_CODE_T_HIGH = 7305 *    VBG_CODE_T_LOW = 4010 * * *                 (TSENS_CODE_T*beta - TSENS_CODE_T_LOW)*(T_HIGH - T_LOW) *    T = T_LOW - --------------------------------------------------------- [degC] *                       (TSENS_CODE_T_HIGH - TSENS_CODE_T_LOW) * * *    VBG_CODE_T (ch45)  = 3959 => beta = 1.01288 *    TSENS_CODE_T (ch128) = 5608 * *    Temp = 31.80 degC *    * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************
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******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed * frequency * * * Mode transition to LPU_STOP is executed. CAN_0 is configured to wake up from *  LPU_STOP to LPU_RUN using message with standard IDE = 0 as a wake up *  preselected matching criteria. After wake up from LPU_STOP, user *  LED1 is blinking.   * * Modified files: mem.ld, sections.ld, startup.s, added file z2_restart.s * * * ------------------------------------------------------------------------------ * Test HW:         MPC5748G-324DS, MPC574xG Motherboard * MCU:             PPC5748GMMN6A 1N81M * Fsys:            PLL0 160MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  Default * * * ********************************************************************************
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******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminals ECHO. * * * Test HW:        X-MPC5744PE257DC, MPC57xx motherboard * MCU:              PPC5744PFMMM8 1N65H * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:             200 MHz * Debugger:      Lauterbach Trace32 *                       PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to A0 (P8.0), * ********************************************************************************
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Detailed Description:                      This config tool simplifies DCF records calculation for MPC5777C device.                 Look at HowToUse sheet for simple guideline, then work with DCF sheet                 Notes: - Macros have to be enabled!       - Programming more than 104 DCF records on Cut1.0b will result in incorrect device operation (FCCU faults, SSCM[CER] bit set, etc)       BR, Petr
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******************************************************************************** * Detailed Description: * * * This example shows synchronization between eTimer, CTU and ADC modules. * The eTimer0 module timer 2 is initialized to generate PWM signal, and rising edge * of this signal is used to generate trigger signal for CTU module. The CTU module * use one command list with 4 ADC_0 channels. Single conversion mode is used, * so ADC0 ch0, ch1, ch2 and ch3 are sampled. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P8.1  - A[0]  .. GPIO output, used to see CTU-ADC ISR period * P9.1     - B[7]  .. ADC0 AN[0] input * P9.2     - B[8]  .. ADC0 AN[1] input * P16.4 - I[3] .. CTU0 EXT TRG output * * see CTU0 EXT TRG output signal (toggle on each trigger) on P16.4 with respect of eTimer PWM signals. * ********************************************************************************
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******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start both Z7 cores, interrupts initialization, blinking three LED by interrupts, * initializes and display notice via UART terminal and then terminal ECHO. * Each core serves one interrupt and one LED. * * The example configures the device for maximum performance by initialization of * instruction/data cache and enabling of branch prediction for each core * (startup.s files). * * ------------------------------------------------------------------------------ * Test HW:         MPC5777M-512DS, MPC57xx Motherboard * MCU:             PPC5777MQMVA8 0N78H * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_2 * Fsys:               600MHz * * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  USER LED1 connected to P8.0, LED2 connected to P8.1 *                  LED3 connected to P8.2 * ********************************************************************************
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******************************************************************************** * Detailed Description: * Example configures Sigma_Delta ADC and periodically converts ANA0_SDA0 input * (EVB's potentiometer can be connected i.e. J53-1 --> PO15) and displays * results in the terminal window (USBtoUART bridge J21). Terminal settings is * 19200-8-no parity-1 stop bit-no flow control on eSCI_A. * Example uses external ADC triggering from eTPU channels, that are for purpose * of this example configured for eTPU GPIO function for all eTPU channels that * can trigger start of SDADC conversion. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *                  eSCI_A is USBtoUART bridge (connector J21) * EVB connection:  For ADC: J53-1 (EVB pot's wiper) --> PO15 (header P22) * ********************************************************************************
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******************************************************************************** * Detailed Description: * * LINFlex UART TXFIFO transmit using DMA * LINFlex UART mode with FIFO receive using DMA * * * EVB connection: * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * See results on PC terminal (baudrate 19200, Data bits 8, Stop bits 1, Parity none). * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH (debug mode, release mode without debugging information) * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************
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******************************************************************************** * Detailed Description: * The example performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, GPIO pins. * DSPI_M1 is configured as master and for DSI function to serialize eTPU channels' * outputs. eTPU to DSI routing is done by SIU configuration. * User can see SPI waveform on the scope or logic analyzer. * ------------------------------------------------------------------------------ * Test HW: MPC5746R-252DC, MPC57xx Motherboard * MCU: SPC5746RMMT5 CTQG1740 1N83M HKBGCTB * Fsys: PLL 200MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: connect following pins to scope or logic analyzer * PA7: DSPI_M1 SOUT (motherboard pin PP[7]) * PA9: DSPI_M1 SCLK (motherboard pin PP[9]) * PA13: DSPI_M1 CS0 (motherboard pin PP[13]) ********************************************************************************
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******************************************************************************** * Detailed Description: * This example shows, how to use overlay feature - how to remap SRAM over Flash. * The remapping is visible only in mirrored flash address space. Normal address * space is not affected. * To see effect of the remapping, read the comments and watch following * addresses in debugger before and after executing Overlay() function: * * SRAM over Flash test case: * 0x4003_0000 * 0x090C_0000 * * Test HW: X-MPC5744PE257DC, MPC57xx motherboard * MCU: PPC5744PFMMM8 1N65H * Fsys: 200 MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH (debug mode, release mode) * EVB connection: none * ********************************************************************************
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******************************************************************************** * Detailed Description: * * This example shows usage of FlexPWM module. * The Submodule0 is set to generate independent PWMA and PWMB signals * The PWMX is used as input for the Capture feature. * Capture logic is set to capture one rising and one falling edge in one shot mode. * Thus you can check the edge placing and calculate a generated duty cycle. * * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5744P rev.D * Maskset: 1N16P * Target : FLASH * Fsys: 200 MHz PLL1 * Debugger: Lauterbach * * * EVB connection: * * J1.3 - D[9] .. FlexPWM X[0] input * J1.5 - A[11] .. FlexPWM A[0] output * J1.7 - A[10] .. FlexPWM B[0] output * * * to measure generated pulse connect X[0] input with either A[0] or B[0] outputs. * ********************************************************************************
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* Version: 1.1 * Date: Sep-22-2021 * Classification: General Business Information * Brief: This example content a basic PMPLL initialization and * configuration of Mode Entry module and Clock Generation * module. By default active is core 2 -> e200z4 ******************************************************************************** ******************************************************************************** * Detailed Description: * ------------------------------------------------------------------------------ * Test HW: MPC57xx + S32R274RRUEVB * Maskset: 1N58R * Target : internal_FLASH * Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 * ******************************************************************************** Revision History: 1.0 Apr-02-2019 b21190(Vlna Peter) Initial Version 1.1 Sep-22-2021 b21190(Vlna Peter) FCCU fault reading
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******************************************************************************** * Detailed Description: * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N81M * Target : SRAM * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Nov-20-2014 b21190(Vlna Peter) Added SWT_0 dissabling in startup 1.3 Mar-10-2016 b21190(Vlna Peter) Fixed clock configuraion for PLL 1.4 Feb-23-2017 b21190(Vlna Peter) FCCU EOUT and bi-stable protocol 1.5 Aug-26-2021 nxa13250(Vlna Peter) modified for MPC5746C *******************************************************************************/
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