******************************************************************************** * Detailed Description: * Purpose of the example is to show how to maintain SRAM data over reset types * that is not destroying SRAM content (for instance software reset) * Changes are done in linker command files (adding new section), because * .BSS and .SBSS section are always cleared by compiler. * Another changes are done in init.s file where SIU_RSR reset flags are * tested and RAM is initialized only conditionally. * Variable 'test_variable' is maintained over SW reset and then incremented * once per reset cycle and displayed over terminal window. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and converts channel 145 * (bandgap voltage chosen as a source for the channel) and displays it into * terminal window. No external connection required excluding terminal via eSCI. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts, blinking * one LED by Core0, second by Core1 (by interrupt), initializes and display * notice via UART terminal and then terminal ECHO. * An example re-configures default clock setting to first and then second * configuration to shows necessary steps to perform this transtition. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) ********************************************************************************

******************************************************************************** * Detailed Description: * The example performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, GPIO pins. * DSPI_M1 is configured as master and for DSI function to serialize eTPU channels' * outputs. eTPU to DSI routing is done by SIU configuration. * User can see SPI waveform on the scope or logic analyzer. * ------------------------------------------------------------------------------ * Test HW: MPC5746R-252DC, MPC57xx Motherboard * MCU: SPC5746RMMT5 CTQG1740 1N83M HKBGCTB * Fsys: PLL 200MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: connect following pins to scope or logic analyzer * PA7: DSPI_M1 SOUT (motherboard pin PP[7]) * PA9: DSPI_M1 SCLK (motherboard pin PP[9]) * PA13: DSPI_M1 CS0 (motherboard pin PP[13]) ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows, how to use overlay feature - how to remap SRAM over Flash. * The remapping is visible only in mirrored flash address space. Normal address * space is not affected. * To see effect of the remapping, read the comments and watch following * addresses in debugger before and after executing Overlay() function: * * SRAM over Flash test case: * 0x4003_0000 * 0x090C_0000 * * Test HW: X-MPC5744PE257DC, MPC57xx motherboard * MCU: PPC5744PFMMM8 1N65H * Fsys: 200 MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH (debug mode, release mode) * EVB connection: none * ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows usage of FlexPWM module. * The Submodule0 is set to generate independent PWMA and PWMB signals * The PWMX is used as input for the Capture feature. * Capture logic is set to capture one rising and one falling edge in one shot mode. * Thus you can check the edge placing and calculate a generated duty cycle. * * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5744P rev.D * Maskset: 1N16P * Target : FLASH * Fsys: 200 MHz PLL1 * Debugger: Lauterbach * * * EVB connection: * * J1.3 - D[9] .. FlexPWM X[0] input * J1.5 - A[11] .. FlexPWM A[0] output * J1.7 - A[10] .. FlexPWM B[0] output * * * to measure generated pulse connect X[0] input with either A[0] or B[0] outputs. * ********************************************************************************

* Version: 1.1 * Date: Sep-22-2021 * Classification: General Business Information * Brief: This example content a basic PMPLL initialization and * configuration of Mode Entry module and Clock Generation * module. By default active is core 2 -> e200z4 ******************************************************************************** ******************************************************************************** * Detailed Description: * ------------------------------------------------------------------------------ * Test HW: MPC57xx + S32R274RRUEVB * Maskset: 1N58R * Target : internal_FLASH * Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 * ******************************************************************************** Revision History: 1.0 Apr-02-2019 b21190(Vlna Peter) Initial Version 1.1 Sep-22-2021 b21190(Vlna Peter) FCCU fault reading

******************************************************************************** * Detailed Description: * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N81M * Target : SRAM * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Nov-20-2014 b21190(Vlna Peter) Added SWT_0 dissabling in startup 1.3 Mar-10-2016 b21190(Vlna Peter) Fixed clock configuraion for PLL 1.4 Feb-23-2017 b21190(Vlna Peter) FCCU EOUT and bi-stable protocol 1.5 Aug-26-2021 nxa13250(Vlna Peter) modified for MPC5746C *******************************************************************************/

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to simulate Multi-bit or Single-bit ECC * error in FlexCAN RAM (user must choose it in the option at the end of * main function). * Example configures FlexCAN module, initializes ECC for all FlexCAN RAMs, then * it injects ECC error to the Message Buffer 9. * When corrupted data is accessed the IVOR1 exception handler is called in case * of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt * handler is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * Reported FlexCAN ECC error address is corrected according RM, section 7.12.2.3 * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW: MPC57xx_Motherboard + MPC5744P-144DC * MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys: 200 MHz PLL with 40 MHz crystal reference * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ********************************************************************************

********************************************************************************  Detailed Description:  Configures the FlexCAN_0 to transmit and receive a CAN FD message with or without  bit rate switching for data phase.  Baudrate during arbitration phase is set to 500kbps, during data phase 2Mpbs.  NOTE! Termination resistor (120Ohm) have to be placed on transceivers output  ------------------------------------------------------------------------------  Test HW: DEVKIT-MPC5748G revD1  Maskset: 0N78S  Target : FLASH  Fsys: 160 MHz PLL ******************************************************************************** Revision History: 1.0 Jun-21-2021 Petr Stancik Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * Initializes eQADC module and cyclically converts internal channel 145 (PMC * band gap). It also configures eTPUC and its timebases (TCR1) to feed STAC bus * (SRV1). This timebase is used for timestamp of the ADC conversion result. * Both values (result and timestamp) are displayed in the terminal window. * No external connection required excluding terminal via eSCI. * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC567xADAT516 Rev.D, MPC567XEVBFXMB Rev.C * MCU: PPC5676RDMVY1 3N23A * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 180MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: default ********************************************************************************

In the attachment you may find System Input / Output Pin Definition for MPC5744P (as it is common to be a embedded attachment with other MPC57xx devices). Preliminary version for next RM release

********************************************************************************  Detailed Description:  Example created as new Application project, see readme.txt for steps to do.  The purpose of this demo application is to show you the usage of the FlexCAN module  using the S32 SDK API and FreeRTOS.  In the first part, the application will setup the board clocks and pins.  Then it will configure the FlexCAN module features such as Bitrate and Message buffers  It will then create two FreeRTOS tasks, one for receiving frames and one for sending frames.  The two user buttons are used to send std message ID=0x1h with 1byte payload as 1 or 0.  Based on received std message with ID=0x2h to LEDs are toggled upon data0 byte.  Use external 12V to power a board.  Connect board with PCAN-USB to display send message and be able to receive some on DEVKIT  ------------------------------------------------------------------------------  Test HW: DEVKIT-MPC5748G rev.D1  Maskset: 0N78S  Target : FLASH  Fsys: 160 MHz PLL  Debugger: S32DS ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes and calibrates eQADC module and cyclically converts choosen * channel, displaying it into terminal window along with its time stamp value. * User could connect EVB pot's wiper to pin header W (see below) to see valid * conversion result. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: For ADC: J53-1 (EVB pot's wiper) --> PS0 - ANA17 * PS1 - ANA18 * PS2 - ANA19 * PS3 - ANA20 * ********************************************************************************

  ******************************************************************************** * Detailed Description: * Initializes and calibrates both eQADC modules and cyclically converts choosen * channels, displaying it into terminal window. * User could connect EVB pot's wiper to pin header W (see below) to see valid * conversion result. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: For ADC: J53-1 (EVB pot's wiper) --> PS0-ANA17 PW08-ANB17 * PS1-ANA18 PW09-ANB18 * PS2-ANA19 PW10-ANB19 * PS3-ANA20 PW11-ANB20 * ********************************************************************************

********************************************************************************  Detailed Description:  This example shows ADC triggering from the eTimer1 module.  The OFLAG signal from the eTimer1 channel 5 is fed into ADC1 converter,  so ADC is set up for injected conversion with end of scan interrupt.  Red LED is dimmed based on converted value  ------------------------------------------------------------------------------  Test HW: DEVKIT-MPC5744P rev.B  Maskset: 1N16P  Target : FLASH  Fsys: 160 MHz PLL  Debugger: S32DS ********************************************************************************

* Detailed Description: * This example demonstrates frequency modulation at 20kHz with 250 steps. * Test HW: xPC57xx EVB + MPC5746C minimodule * Maskset: 1N06M * Target : Internal Flash * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Apr-23-2015 b21190(Vlna Peter) Added INTC driver and PIT ISR 1.3 May-14-2015 b21190(Vlna Peter) Dissabling SWT in Startup code 1.4 Jun-06-2017 b21190(Vlna Peter) ported for MPC5746C 1.5 Sep-29-2020 b21190(Vlna Peter) Added 20kHz frequency modulation *******************************************************************************/

* Example of eMIOS configuration for shifted PWM mode ******************************************************************************** * Test HW: MPC5746C minimodule + MPC57xx Motherboard * Maskset: 1N06M * Target : Internal Flash * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Apr-23-2015 b21190(Vlna Peter) Added INTC driver and PIT ISR 1.3 May-14-2015 b21190(Vlna Peter) Dissabling SWT in Startup code 1.4 Jun-06-2017 b21190(Vlna Peter) ported for MPC5746C 1.5 Jun-06-2017 b21190(Vlna Peter) eMIOS example with shifter PWM *******************************************************************************/

This example content a basic FMPLL initialization and configuration of Mode Entry module and Clock Generation module. By default active is core 2 -> e200z4 Demonstration of PIT triggering an interrupt on timeout. ******************************************************************************** * Test HW: MPC57xx + S32R274RRUEVB * Maskset: 1N58R * Target : internal_FLASH * Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 ******************************************************************************** Revision History: 1.0 Apr-02-2019      b21190        (Vlna Peter) Initial Version 1.1 Sep-19-2019     nxa13250    (Vlna Peter) Added PIT + interrupts *******************************************************************************/

This is the first lab for the 2D-ACE (DCU) tutorial