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******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit * ECC error in internal FLASH (user must choose it in the option at the end of * main function). * Flash over-programming is used to generate a non-correctable (or single-bit) * ECC error in FLASH. The bad data is accessed then what's generate IVOR1 * exception or FCCU_Alarm_Interrupt. Both function calls MEMU handler. * Example also offers useful macros for MEMU module. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW: MPC57xx_Motherboard + MPC5744P-144DC * MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys: 200 MHz PLL with 40 MHz crystal reference * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ********************************************************************************

******************************************************************************** * Detailed Description: * * Example shows MCU's temperature measurement with the help of TSENS. * Calibartion constants for TSENS0/TSENS1 are read from Test flash and * eQADC is set to measure Vbg and TSENS outputs. eQADC calibration is also done. * Calculated internal temperature can be displayed on the Terminal. * * See results on PC terminal (19200, 8N1, None). You should see following text * (with different values for sure) * * TSENS0/TSENS1 temperature measurement * press any key to continue... * * Calibration constants read from TSENS registers * * TSENS0 TSENS1 * * TSCA_0 = 207 TSCA_1 = 148 * TSCB_0 = 7 TSCB_1 = 19 * * T = (232 + TSCA * 2^-6) * TSENS_CODE_T / VBG_CODE_T - (273 + TSCB * 2^-4) [degC] * * VBG_CODE_T = 997 * TSENS0_CODE_T = 1325 TSENS1_CODE_T = 1332 * * TSENS0 temp = 39.19 degC TSENS1 temp = 38.86 degC * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * * * This example shows usage of FlexPWM and Sine Wave generator (SGEN) modules. * The setting is selected in the way to have a PWM output signal synhronized with * SWG output signal. This is necessary for resolver usage in motor control appls. * The CTU_0 is triggered from FlexPWM_0's. The PMWB output rising edge is used here. * The CTU generates the eTIMER1_TRG signal, that is a trigger signal for the * SGEN module. The delay between PWMB and SGEN trigger is changed so you can see * the generated sinusoidal signal change phase against the PWMB output. * * See attached Excel sheet for calculation of parammeters used here (AUX0_clk_DIV0, * AUX0_clk_DIV1, SGEN_IOFREQ, PWM_PRESCALER, PWM_MODULO). * * This example is set for 9.765625KHz SGEN/PWM frequency. * * Note because the SGEN trigger input is an asynchronous signal, it must be held high * for at least 2 SGEN clock cycles in order to capture the input trigger. * As the CTU generates the trigger as a pulse of single CTU clock width, the CTU clock must be * half of the SGEN clock at least. * * Use the AUX0_clk_DIV0 to test this behaviour. * * * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N65H * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P11.8 - D[7] .. SGEN output * connected to FEC PHY's MIIMODE input on motherboard, * to see full amplitude remove J26 * * P8.12 - A[11] .. FlexPWM A[0] output * P8.11 - A[10] .. FlexPWM B[0] output * * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demostrates how to configure CGM )clock generation module) * and supply by clock all main peripherals. * * ------------------------------------------------------------------------------ * Test HW: Test HW: MPC57xx Motherboard + MPC5777M_512DS minimodule, MPC5777M, * Maskset: 0N75H * Target : internal_FLASH * Fsys: 200 MHz PLL * ******************************************************************************** Revision History: 1.0 Nov-04-2014 b21190(Vlna Peter) Initial Version 1.1 Feb-04-2016 b21190(Vlna Peter) Fixed Clock configuration *******************************************************************************

******************************************************************************** * Detailed Description: * * Example shows how to trigger ADC conversion on falling edge of PWM signal. * eMIOS ch1 is set to SAIC mode and a flag generated on selected edge detection * triggers BCTU channel which starts conversion of ADC1 ch9. On this channel * the board's trimmer is connected. * * EVB connection: * * J3.1 .. PA[1] - connect external PWM signal * J3.3 .. PA[2] - toggled in BCTU interrupt after ADC measurement * * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5748G * Maskset: 0N78S * Target : FLASH * Fsys: 160 MHz PLL * Debugger: Lauterbach * ******************************************************************************** Revision History: 1.0 Nov-5-2019 Petr Stancik Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * * Application initializes SPI0 module as a master and SPI2 module as a slave. * Data are sent from master to slave and from slave to master. Simple * polling method is used to determine, when data were sent/received. * Received data are saved to global variables. * * ------------------------------------------------------------------------------ * Test HW: MPC5777M-512DS, MPC57xx Motherboard * MCU: PPC5777MQMVA8 0N78H * Fsys: PLL0 300MHz * PLL1 300MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, debug_ram mode, release mode) * EVB connection: P18.12 to P14.13 (CS_0) * P11.4 to P8.13 (SCK) * P11.1 to P11.5 (SOUT - SIN) * P11.8 to P12.9 (SIN - SOUT) * * ********************************************************************************

* Detailed Description: * This example demonstrates how to correctly execute ADC self-test for algorithm S and C. * -------------------------------------------------------------------------------------------------------------------- * Test HW: MPC57xx EVB + MPC5744P minimodule * Maskset: 1N65H * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0 Apr-04-2016 b21190(Vlna Peter) Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * * ------------------------------------------------------------------------------ * Test HW: TRK-MPC5604P, SPC5604P * Maskset: 0M36W * Target : RAM * Terminal: no * Fsys: 64 MHz PLL with 8 MHz crystal reference in RUN0. IRC in DRUN * * 1. you have to use an external power supply to the board (SBC power) 2. The SBC chip must be initialized (via SPI interface) to turn on the CAN transceiver. 3. For ease of use, install the VSUP shunt on (jumper J5). This it to put 9 V on the SBC's DBG pin - refer to the SBC Data Sheet for more details about the DBG pin of the SBC chip. 4. This code initializes the MCU, then sends commands to the SBC chip over the SPI bus to turn on the CAN transceiver, then the FlexCAN_0 module transmits a message out of the board. I/O configuration for the TRK-MPC5604P CAN example: MCU_PB0 -> SBC_TXD (MPC5604P CAN0TX PCR[16] ALT1 function) MCU_PB1 <- SBC_RXD (MPC5604P CAN0RX PCR[17] input function) SPI bus between the MCU and SBC: MCU_PC4 -> SBC_!CS (MPC5604P DSPI_0 CS0 ALT1 function PCR[36]) MCU_PC5 -> SBC_CLK (MPC5604P DSPI_0 SCK ALT1 function PCR[37]) MCU_PC6 -> SBC_MOSI (MPC5604P DSPI_0 SOUT ALT1 function PCR[38]) MCU_PC7 <- SBC_MISO (MPC5604P DSPI_0 SIN input function PCR[39]) * ********************************************************************************

******************************************************************************** * Detailed Description: * * * This example demonstrate functionality of XBIC_0 error injection * capability on XBAR_0. The fault is generated on Core access to SRAM. * After fault generation it is propagated to FCCU unit as NCF[38]. * * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N65H * Target : internal_FLASH * Fsys: 16MHz IRC * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates how to configure (CGM) clock generation module * and supply by clock all main peripherals. * ------------------------------------------------------------------------------ * Test HW: MPC57xx Motherboard + MPC5746R_176DC minimodule, MPC5746R * Maskset: 1N83M (cut 2.0B) * Target : internal_FLASH * Fsys: 200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0 Oct-19-2015 b21190(Vlna Peter) Initial Version 1.1 Nov-11-2015 b21190(Vlna Peter) Added PPL0 200MHz as system clock 1.2 Dec-02-2015 b21190(Vlna Peter) Added Flash controller init 1.3 Dec-02-2015 b21190(Vlna Peter) Fixed system clock init 1.4 Feb-07-2017 b21190(Vlna Peter) SWT0 and SWT1 disabled in startup *******************************************************************************/

******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and cyclically converts PMC * internal channel as specified by macros CHOOSEN_PMC_ADC_CHNL, * CHOOSEN_PMC_ADC_SCALE and CHOOSEN_PMC_ADC_COMMAND to check particular voltage * level, displaying it into terminal window. * No external connection required excluding terminal via eSCI. * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC567xADAT516 Rev.D, MPC567XEVBFXMB Rev.C * MCU: PPC5676RDMVY1 3N23A * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 180MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: default ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates PMC Single VD self-test configuration and execution * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N15P and 0N15P * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0 Apr-04-2016 b21190(Vlna Peter) Initial Version 1.1 Apr-20-2017 b21190(Vlna Peter) added software PMC self-test 1.2 Aug-31-2017 b21190(Vlna Peter) added PMC self-test configuration fix *******************************************************************************/

******************************************************************************** * Detailed Description: * * ------------------------------------------------------------------------------ * Test HW: TRK-MPC5634M rev.B, SPC5634M * Maskset: 1M35Y * Target : RAM * Terminal: no * Fsys: 64 MHz PLL with 8 MHz crystal reference * * 1. you have to use an external power supply to the board (SBC power) 2. The SBC chip must be initialized (via SPI interface) to turn on the CAN transceiver. 3. For ease of use, install the VSUP shunt on (jumper J5). This it to put 9 V on the SBC's DBG pin - refer to the SBC Data Sheet for more details about the DBG pin of the SBC chip. 4. This code initializes the MCU, then sends commands to the SBC chip over the SPI bus to turn on the CAN transceiver, then the FlexCAN_A module transmits a message out of the board. I/O configuration for the TRK-MPC5634M CAN example: SBC_TXD (MPC5634M CANATX PCR[83] ALT1 function) SBC_RXD (MPC5634M CANARX PCR[84] input function) SPI bus between the MCU and SBC: SBC_!CS (MPC5634M DSPI_B CS0 ALT1 function PCR[105]) SBC_CLK (MPC5634M DSPI_B SCK ALT1 function PCR[102]) SBC_MOSI (MPC5634M DSPI_B SOUT ALT1 function PCR[104]) SBC_MISO (MPC5634M DSPI_B SIN input function PCR[103]) * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates how to use lauterbach multicore project. * All MPC5748G cores (z4a, z4b, z2) are active. Micro boots with core z4a. * On z4a is micro configuration executed and then in Core_Init(); function * are started other 2 cores (z4b and z2). * Example also include Lauterbach multicore (multi powerview) example script * + T32 configuration file * ------------------------------------------------------------------------------ * Test HW: MPC57xx MB + * Maskset: 1N81M * Target : SRAM * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Nov-20-2014 b21190(Vlna Peter) Added SWT_0 dissabling in startup 1.3 Feb-12-2016 b21190(Vlna Peter) Modified for multicore project *******************************************************************************/

******************************************************************************** * Detailed Description: * Used flash driver: MPC5700 C55FG Flash Standard Software Driver (REV 1.1.0) * http://www.nxp.com/files/product/software/C55_JDP_SSD.exe * * This example checks four large 256KB flash blocks at address 0x0100_0000 - * 0x010F_FFFF. * Some random data are placed to this section (constant "flash_data[]"), so the * s-record is not empty. * It is necessary to use off-line MISR_C55.exe tool which calculates MISR * values for selected flash blocks. See the "MISR gen" folder included in this * project. File "core0.run" is s-record file which is used for calculation. It * contains the data (constant "flash_data[]") placed to the selected blocks. * "misr.bat" file shows how to call the calculator. * "output.txt" contains the result of this operation - the MISR values. * Once this is done, initialize the SSD drivers, unlock blocks which are going * to be checked and run the FlashArrayIntegrityCheck function. * Notice that the code must be executed from RAM. We cannot access the flash * during this operation. If the operation is successful, FlashCheckStatus will * return opResult C55_OK if the MISR values are equal. It will return * C55_ERROR_MISMATCH if the MISR values are not equal, i.e. the flash is * corrupted and the content does not correspond to s-record file. * ------------------------------------------------------------------------------ * Test HW: X-MPC5744PE257DC, MPC57xx motherboard * MCU: PPC5744PFMMM8 1N65H * Fsys: 200 MHz PLL * Debugger: Lauterbach Trace32 * Target: internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to configure Wake up unit and CAN sampler. * Once the device is woken up from STOP mode by falling edge on CAN0RX pin, * the CAN sampler starts to sample this pin in given period. * FlexCAN module is not initialized and used in this example because the CAN * sampler is independent of FlexCAN. * ------------------------------------------------------------------------------ * Test HW: XPC56xxMB2 + XPC560B 176LQFP, PPC5607B * Target : internal_FLASH, RAM * Fsys: 64 MHz PLL * ********************************************************************************