******************************************************************************** * Detailed Description: * This example demonstrates how to use lauterbach multicore project. * All MPC5748G cores (z4a, z4b, z2) are active. Micro boots with core z4a. * On z4a is micro configuration executed and then in Core_Init(); function * are started other 2 cores (z4b and z2). * Example also include Lauterbach multicore (multi powerview) example script * + T32 configuration file * ------------------------------------------------------------------------------ * Test HW:  MPC57xx MB + * Maskset:  1N81M * Target :  SRAM * Fsys:     160 MHz PLL * ******************************************************************************** Revision History: 1.0     Oct-29-2014     b21190(Vlna Peter)  Initial Version 1.1    Nov-20-2014    b21190(Vlna Peter)  Modified for Cut2.0 1.2    Nov-20-2014    b21190(Vlna Peter)  Added SWT_0 dissabling in startup 1.3    Feb-12-2016    b21190(Vlna Peter)  Modified for multicore project *******************************************************************************/

******************************************************************************** * Detailed Description: * This example content a basic PMPLL initialization and * configuration of Mode Entry module and Clock Generation * module. By default active is core 2 -> e200z4a * Configure PIT timer to trigger interrupt and service it. * Example configures start of z7 cores via SW routine. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx MB + MPC5775K-326DS minimodule * Maskset:  0N76P * Target :  internal_FLASH * Fsys:     265 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0     Sep-07-2017     b21190(Vlna Peter)  Initial Version *******************************************************************************/ Example also contains Lauterbach multicore script as you can see below: It will display 3 Power view instances.

******************************************************************************** * Detailed Description: * This example content a basic PMPLL initialization and * configuration of Mode Entry module and Clock Generation * module. By default active is core 2 -> e200z4 * Configure PIT timer to trigger interrupt and service it  * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  0N76P * Target :  internal_FLASH * Fsys:     265 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Sep-07-2017     b21190(Vlna Peter)  Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * DRUN mode with max core frequency(200MHz) generated from PPL0 * This example demonstrates ECC error injection to peripheral RAM *  and ECC error reporting to MEMU * --------------------------------------------------------------------------------------------- * Test HW:  MPC57xx * Maskset:  1N15P * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference *           ******************************************************************************** Revision History: 1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version 1.1    Aug-15-2017     b21190(Vlna Peter)  EIM ECC RAM error injection to DMA added *******************************************************************************/

******************************************************************************** * Detailed Description: * This example demonstrates frequency modulation at 20kHz with 250 steps. * System frequency which is modulated is 40MHz. * ------------------------------------------------------------------------------ * Test HW:   MPC57xx EVB + MPC5748G minimodule * Maskset:   1N81M * Target :     SRAM * Fsys:        40 MHz PLL * ******************************************************************************** Revision History: 1.0     Oct-29-2014     b21190(Vlna Peter)  Initial Version 1.1    Nov-20-2014    b21190(Vlna Peter)  Modified for Cut2.0 1.2    Nov-20-2014    b21190(Vlna Peter)  Added SWT_0 dissabling in startup 1.3    Mar-10-2016    b21190(Vlna Peter)  Fixed clock configuraion for PLL 1.4    Jun-30-2017    b21190(Vlna Peter)  Added 20kHz frequency modulation *******************************************************************************/ Measure modulated system Frequency at PG[7] - SYSCLK0 pin.

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts and external * interrupt for IRQ0 pin (alternative function of ETPUC9 pin). * User needs to connect ETPUC9 pin to user switch and general purpose output * ETPUA30 to user LED 1: * ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUC9  (PortV P30-8) --> USER_SWITCHES (P6-4) * * If rising edge is detected (i.e. button is pressed), interrupt is triggered * and LED1 on is toggled. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUC9  (PortV P30-8) --> USER_SWITCHES (P6-4) ********************************************************************************

******************************************************************************** * Detailed Description: * DRUN with PLL 160MHz active. * Example of INTC configuration. PIT timer is triggering an * interrupt which is served in PIT ISR. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N06M * Target :  Internal Flash * Fsys:     160 MHz PLL * ******************************************************************************** Revision History: 1.0     Oct-29-2014     b21190(Vlna Peter)  Initial Version 1.1    Nov-20-2014    b21190(Vlna Peter)  Modified for Cut2.0 1.2    Apr-23-2015    b21190(Vlna Peter)  Added INTC driver and PIT ISR 1.3    May-14-2015    b21190(Vlna Peter)  Dissabling SWT in Startup code 1.4     Jun-06-2017    b21190(Vlna Peter)  ported for MPC5746C *******************************************************************************/

******************************************************************************** * Detailed Description: * This example demostrates how to configure CGM )clock generation module) * and supply by clock all main peripherals. * Example demonstrate FCCU fake fault injection for fault 7 amd Alarm state * interrupt calling after injecting fake fault 7. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx EVB * Maskset:  0N50N * Target :  internal_FLASH * Fsys:     200 MHz PLL * ******************************************************************************** Revision History: 1.0     Nov-04-2014     b21190(Vlna Peter)  Initial Version 1.1     Feb-04-2016     b21190(Vlna Peter)  Fixed Clock configuration 1.2    Jun-16-2017    b21190(Vlna Peter)  FCCU fake fault injection 1.3    Jun-16-2017    b21190(Vlna Peter)  FCCU alarm interrupt example *******************************************************************************/

******************************************************************************** Detailed Description:  Example shows MCU's temperature measurement with the help of TSENS.  Calibration constants for TSENS0 are read from Test Flash and  SARADC_B is set to measure Vbg and TSENS outputs.  Calculated internal temperature can be displayed on the Terminal.  EVB connection:    Motherboard    J14 - SCI_RX ON    J13 - SCI_TX ON    J25 - SCI_PWR ON    See results on PC terminal (19200, 8N1, None). You should see following text  (with different values for sure)  TSENS - temperature measurement  press any key to continue...  TSENS's calibration constants read from Test Flash  TSCA = 184  TSCB = 21    T = (232 + TSCA * 2^-6) * TSENS_code / VBG_code - (273 + TSCB * 2^-4) [degC]  ----------------------------------------------------------------------------  VBG_code   =  251  TSENS_code =  339  TSENS temp = 42.91 degC  ------------------------------------------------------------------------------  Test HW:  MPC5777M  Maskset:  0N50N  Target :  RAM, internal_FLASH  Fsys:     600 MHz PLL1 with 40 MHz crystal reference  Terminal: 19200baud, 8N1 ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * Initializes the MCU including the FlexCAN peripherals. * Configures the FlexCAN to transmit and receive a CAN message. * * In this config, CAN_0 transmits a message. CAN_2 receives the message. * CAN_0 MB0 is configured to send data. * * CAN_2 MB0 is configured to receive a message, interrupt is used. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5746R-176LQFP, MPC57xx Motherboard * MCU:             PPC5743R 1N83M * Fsys:            PLL0 200MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, debug_ram mode) * EVB connection: * * Jumpers j37 and j38 on motherboard must be in position 2-3 * * Connect CAN P5.2 to CAN2 P4.2 on motherboard * Connect CAN P5.1 to CAN2 P4.1 on motherboard * * ******************************************************************************** Revision History: Version  Date         Author              Description of Changes 1.0      Jun-07-2017  Martin Kovar      Initial version

******************************************************************************** * Detailed Description: * * Configures the FlexCAN to transmit and receive a CAN message. * ECC reporting in the FlexCAN module is enabled. * * In this config, CAN_A transmits a message. CAN_B receives the message. * CAN_A MB8 is configured to send data. CAN_A sends message each 1sec. * This interval is generated by PIT. * CAN_B MB9 is configured to receive a message, SW polling is used. * * Install jumpers J37 1-2 and J38 1-2 * * Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * * ********************************************************************************

******************************************************************************** * Detailed Description: * Preparation, configuration and execution of ONLINE(SHUTDOWN) build-in self-test. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version 1.1    Apr-28-2017     b21190(Vlna Peter)  Added cut 1N65H (2.1) *******************************************************************************/

A requirement of the standard is to detect the accumulation of latent defects. To meet this requirement the MPC5744P has the ability to execute Built-In Self-Test (BIST) procedures.

******************************************************************************** * Detailed Description: * Application initializes FCCU and Software watchdog. After SWT timeout expires, * microcontroller is reset. * * Macro LONG_RESET defines, which reset is performed. If LONG_RESET is 1, long * reset is performed, else short reset is performed. * * ------------------------------------------------------------------------------ * Test HW:         S32R274RRUEVB, MPC57xx Motherboard * MCU:             S32R274KAMMM 1N58R * Fsys:            PLL0 240MHz *                    Z4 Core 120MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, debug_ram and release mode) * EVB connection: default * * ********************************************************************************

The device can be secured by adding a Non-Volatile System Censorship Information (NVSCI) record to the DCF record list in the UTEST Flash block. A value of 55AAh in the censorship control word of the NVSCI record determines that the device is unsecured, any other value determines that the device is secured.   Censoring the device (example for lauterbach script) 1. Program NVSCI DCF record to first available space in UTEST memory.    data.set 0x00400308 %QUAD 0x55AA12340100000C ;NVSCI - Censorship Control enabled 2. Program Censorship password (0x1234567812345678)    data.set 0x00400310 %QUAD 0x1234567801000004 ;NVPWDL                                                            data.set 0x00400318 %QUAD 0x1234567801000008 ;NVPWDH    3. Perform reset   Now the device is censored and JTAG PASSWORD must be inserted in order to work with JTAG. Lauterbach ->   sys.option.keycode 0x1234567812345678 sys.attach sys.break The device is now accessible trough JTAG.   " After every reset the JTAG PASSWORD key must be reentered on censored device "   Uncensoring device: data.set 0x004003018 %QUAD 0x55AA55AA0100000C ;NVSCI - Censorship Control disabled   NOTE:   Peter Original Attachment has been moved to: MPC5744P_DCF_Censorship.cmm.zip

******************************************************************************** * Detailed Description: * This example demonstrates PMC Single VD self-test configuration and execution * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N15P and 0N15P * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference *            ******************************************************************************** Revision History: 1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version 1.1     Apr-20-2017     b21190(Vlna Peter)  added software PMC self-test 1.2     Aug-31-2017    b21190(Vlna Peter)  added PMC self-test configuration fix *******************************************************************************/

******************************************************************************** * Detailed Description: * This example demonstrates PMC SW triggered self-test configuration and execution * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N15P and 0N15P * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference *            ******************************************************************************** Revision History: 1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version 1.1     Apr-20-2017     b21190(Vlna Peter)  added software PMC self-test *******************************************************************************/

With author's permission I am publishing document dealing with migration between MPC5646C to MPC574xG devices.   Document was created in year 2013, it was never been officially released, it is not maintained and it is shared AS IS. There is NO WARRANTY and NO SUPPORT can be expected.   However, it could be helpful for initial orientation on which points to look during migration work. If it is used, user should always refer to latest device's reference manual for possible specification changes.   Thanks to Christian Michel-Sendis, Viktor Fellinger and Jose Cisneros for their great job.

******************************************************************************** * Detailed Description: * * This example shows possible implementation of frequency and duty cycle * measurement with the help of eMIOS module. * Two eMIOS channels are used and set to IPWM and IPM modes. The first channel * measures the positive pulse width and the second channel measures the period. * * EVB connection: * PJ7.5 to PJ7.6 ... connect external pulse signal to this * * See result on PC terminal (9600, 8N1) * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC564xB/C, SPC5646C 0N32E silicon * Target :  internal_FLASH, RAM * Fsys:     120 MHz PLL0 * Debugger: Lauterbach Trace32. script for internal_FALSH run_from_flash.cmm *                               script for RAM: run_from_ram_vle.cmm * ********************************************************************************     BR, Petr

Detailed Description: * This example shows, how to configure Mode entry module and enable required * peripherals only. RTC module is configured to create interrupt every 50ms. * Microcontroller is in in STOP mode most of the time and it is waken-up using RTC * interrupt. * * ------------------------------------------------------------------------------ * Test HW:         XPC560S 144LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             PPC5606S 0M25V * Terminal:         * Fsys:            16MHz IRC * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  Default * ********************************************************************************