******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit ECC error in * local DMEM memory. * ECC fault is generated with using of core register DMEMCTL0. If error * injection is enabled (DMEMCTL0[DPEIE]=1), subsequent write to DMEM creates * 2b ECC error in DMEM array and following read of this area causes bus error * (IVOR1 exception) or FCCU_Alarm_Interrupt. * Both function calls MEMU handler. * Example does not show any handling as it is application specific. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************

This document describes, how to create another configuration to existing ones (RAM, FLASH) and how to use your own linker file for the new configuration. As soon as you have created project, right click the project and select Properties. Click Tool Chain Editor. In upper right corner, select Manage Configurations. New window will appear, then click new. As soon as you choose new, another window will appear and here you can insert name of the configuration, description and last, you must choose, which configuration will be settings copied from. So, for example, you can choose existing FLASH configuration. Click OK and new configuration will be created. Now, you can choose the new configuration as the active configuration, also this new configuration is added to configurations, and it is accessible via "hammer" icon in upper left corner. Now, it is necessary to set linker file you want to use with this configuration. Because this new configuration is inherited from FLASH configuration, it also uses default flash linker file. Set your configuration as active at first. After this step, in project properties select Settings->PowerPC Linker input tab. Into line Link Command File, choose path to required linker file you want to use with the new configuration. Click OK. You can verify the new configuration is chosen using arrow new to the hammer icon. How to use new configuration in debug configuration As soon as you have new configuration created, it is highly probable, you would like to download created elf into microcontroller and eventually debug it. Open debug configuration window. Now you can create new debug configuration or you can duplicate existing one. I will describe easier option and I will duplicate Flash configuration. Choose the flash configuration and click the duplicate icon. New configuration will appear. Now choose the new configuration, change the name and select elf file, which is created by new configuration. Click Apply and Debug button.

* Owner:            b21190(Vlna Peter) * Version:          1.6 * Date:               Nov-11-2015 * Classification: General Business Information * Brief:               Example contains startup with PLL0 200MHz as system clock *                        ADC self-test demonstration                       ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N83M (cut 2.0B) * Target :  internal_FLASH * Fsys:     200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0     Oct-19-2015          b21190(Vlna Peter)  Initial Version 1.1        Nov-11-2015        b21190(Vlna Peter)  Added PPL0 200MHz as system clock 1.2        Dec-02-2015        b21190(Vlna Peter)  Added Flash controller init 1.3        Dec-02-2015        b21190(Vlna Peter)  Fixed system clock init 1.4        Feb-07-2017        b21190(Vlna Peter)  SWT0 and SWT1 disabled in startup 1.5       May-31-2017        b21190(Vlna Peter)  Fixed comments in AC6 (CLKOUT) 1.6        Jul-10-2018        nxa13250(Vlna Peter) Added ADC self-tests *******************************************************************************/

This document describes how to use Lauterbach FCCU (fault collection and control unit) periphery extension for MPC57xx devices. It is expected that user has deep knowledge on FCCU mechanisms in order to effectively use this extension. This scripting tool consist of 136 scripts for Lauterbach debugger. It helps user to quickly debug micro without need of reference manual. Here is and example of windows that user can use (detailed description can be found in user guide):

******************************************************************************** * Owner:            b21190(Vlna Peter) * Version:          1.0 * Date:             May-09-2018 * Classification:   General Business Information * Brief:            BIST demonstration ******************************************************************************** * Test HW:  MPC57xx * Maskset:  3N23A * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Oct-22-2014     b21190(Vlna Peter)  Initial Version 1.1    Sep-25-2018    b21190(Vlna Peter)  STCU2 BIST Multicore *******************************************************************************/

* Owner:            b21190(Vlna Peter) * Version:          1.0 * Date:               May-09-2018 * Classification:   General Business Information * Brief:                 BIST demonstration *                    ******************************************************************************** * Test HW:  MPC57xx * Maskset:  3N23A * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0       Oct-22-2014     b21190(Vlna Peter)  Initial Version 1.1        Mar-19-2015        b21190(Vlna Peter)  Added ADC_0 driver 1.2        Mar-19-2015        b21190(Vlna Peter)  Added STCU self-test for core1 *******************************************************************************/

******************************************************************************** * File:                 main.c * Owner:            Peter Vlna * Version:           1.7 * Date:               Oct-10-2017 * Classification: General Business Information * Brief:                Example contains startup with PLL0 200MHz as system clock *                          and demonstrates reset triggered on FCCU Alarm state *                          counter exppire. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N83M (cut 2.0B) * Target :  internal_FLASH * Fsys:     200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0     Oct-19-2015     Peter Vlna   Initial Version 1.1    Nov-11-2015    Peter Vlna   Added PPL0 200MHz as system clock 1.2    Dec-02-2015    Peter Vlna  Added Flash controller init 1.3    Dec-02-2015    Peter Vlna  Fixed system clock init 1.4    Feb-07-2017    Peter Vlna  SWT0 and SWT1 disabled in startup 1.5     May-31-2017    Peter Vlna  Fixed comments in AC6 (CLKOUT) 1.6     Oct-04-2017    Peter Vlna  Added PIT + Interrupts 1.7    Oct-05-2017    Peter Vlna  FCCU EOUT test in Alarm state with SMC *******************************************************************************/

******************************************************************************** * File:             main.c * Owner:            b21190(Vlna Peter) * Version:          1.6 * Date:             Oct-10-2017 * Classification:   General Business Information * Brief:            Example contains startup with PLL0 200MHz as system clock *                   and demonstrates PIT interrupt triggering. ******************************************************************************** * Test HW:  MPC57xx EVB + MPC5746R minimodule * Maskset:  1N83M (cut 2.0B) * Target :  internal_FLASH * Fsys:     200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0     Oct-19-2015   b21190(Vlna Peter)  Initial Version 1.1    Nov-11-2015     b21190(Vlna Peter)  Added PPL0 200MHz as system clock 1.2    Dec-02-2015    b21190(Vlna Peter)  Added Flash controller init 1.3    Dec-02-2015    b21190(Vlna Peter)  Fixed system clock init 1.4    Feb-07-2017    b21190(Vlna Peter)  SWT0 and SWT1 disabled in startup 1.5     May-31-2017    b21190(Vlna Peter)  Fixed comments in AC6 (CLKOUT) 1.6     Oct-10-2017    b21190(Vlna Peter)  Added PIT + Interrupts *******************************************************************************/

******************************************************************************** * Detailed Description: * This exapmple demonstrates progressive clock switching from full PLL clock * 256MNHz down to 200MHz. * * --------------------------------------------------------------------------------------------- * Test HW:  MPC57xx * Maskset:  3N45H * Target :  FLASH * Fsys:     256 MHz PLL * ******************************************************************************** Revision History: 1.0     Aug-04-2016     b21190(Vlna Peter)  Initial Version 1.1    Sep-05-2017     b21190(Vlna Peter)  Added FCCU faults clearing 1.2    May-07-2018    nxa13250(Vlna Peter)  PLL switch from 256->200MHz *******************************************************************************/

* Detailed Description: * This example shows, how to use interrupt hardware vector mode. In the example * PIT3 and PIT2 interrupts are implemented. PIT interrupt toggle LED every second. * * * This example also shows, how to implement IVOR exceptions for core 0. * IVOR1 handler with while(1) loop is ready to use. * * * For correct HW vector mode setup, following files was added to the project: * *  - exceptions.s *  - handlers_vle.s *  - HW_vector.c * * * Following files has been modified (all changes are marked by comment): * *  - 56xx_flash.ld *  - Vector.c *  - MPC57xx__Interrupt_Init.c * *  Following file was removed from project (files are still place in project, but *  not compiled and linked) * *  - intc_sw_handlers.S *  - intc_SW_mode_isr_vectors_MPC5744P.c * * * * Test HW:         MPC567XADAT516, MPC567XEVBFXMB * MCU:             PPC5676RDMVY1 3N23A * Fsys:            180 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to J241, *                    User LED 1 connected to J242. *

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate EDC after ECC error in * internal FLASH. Error response in achieved by reading of pre-defined patterns * in UTEST area at address 0x00400080 which generates IVOR1 exception and FCCU * interrupt (FCCU_Alarm_Interrupt). * Example does not show any handling as it is application specific. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************

******************************************************************************** * Detailed Description: * A simple example configures eTPU engine B channels 0/1 for GPO/GPI. It is * needed to connect these pins by wire. Output wave is generated by eTPU GPIO * output function and inputs are read by fs_etpu_gpio_input_immed function * latching just current pin state. Pin history is displayed in ISR. * * Note: It is needed to configure IGF module, otherwise inputs does not pass * to eTPU module. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUB0 (PortR P25-1) --> ETPUB1 (PortR P25-0) by wire * ********************************************************************************

******************************************************************************** * Detailed Description: * The example uses serial flash memory S25FL129P (connected to DSPI_PCS1) * that is connected to DSPI_B module (PCS1). No Dual or Quad I/O has been used. * SW uses polling mechanism. * The example at first read device ID, performs bulk erase of S25FL129P and then * programs some sample data specified in main function. Check reading is then * performed. During that some notices are displayed on the terminal window. * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC567xADAT516 Rev.D, MPC567XEVBFXMB Rev.C * MCU:             PPC5676RDMVY1 3N23A * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            180MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  default ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module for differnential single scan mode (with choosen GAIN * factor), converts specified command queue and displays results into terminal * window when EOQ is reached. * Differential analog input DAN0+:DAN0- needs to be connect externally between * pins ANA_0 and ANA_1 to see some valid numbers. * EVB potentiomenters can be used for the purpose. * As differential mode has been used, eQADC does not required to be calibrated.             * * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            264/200/150/60 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  Potentiometers     --> ADC inputs *                  USER_DEV_RV2(J4-7) --> ANA_0 (J18-3) DAN0+ *                  USER_DEV_RV3(J4-8) --> ANA_1 (J18-4) DAN0- * *                    Buttons            --> ADC triggers *                    USER_DEV_1D(J4-2)  --> TPU_A0 (J22-1)                  ********************************************************************************

******************************************************************************** * Detailed Description: * Basic initialization of CMPU: * Region 0 (Instruction): Internal Flash @ 0x0040_0000-0x01FF_FFFF * Region 1 (Instruction): SRAM   @ 0x4000_0000-0x4005_FFFF * Region 6 (Data): SRAM @ 0x4000_0000-0x4005_FFFF * Region 7 (Data): Internal Flash @ 0x0040_0000-0x011F_FFFF * Region 8 (Data): PBRIDGE1/0 @ 0xF800_0000-0xFFFF_FFFF * * This excel configurator has been used: * https://community.nxp.com/docs/DOC-335467 * * ------------------------------------------------------------------------------ * Test HW:         X-MPC5744PE257DC, MPC57xx motherboard * MCU:             PPC5744PFMMM8 1N65H * Fsys:            200 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************

This excel tool helps to configure Core MPU on MPC57xx devices. It generates asm code and also command for Lauterbach debugger for selected configuration of MPU entry.

This document describes how to use On-line BISTs on MPC5777C. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- STCU2 On-line BIST (MBIST+ LBIST) execution time on NXP Evaluation board ( X-MPC5777C-561DS) is 25.8ms. This measured time is valid for: System clock PLL = 200MHz STCU module clock = System clock / 4 MBIST = 50MHz LBIST = 25MHz Result after testing MBIST+LBIST = 0 faults latched in ERR_STAT register and all LBISTs was successfully executed. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- STCU2 On-line LBIST only execution time on NXP Evaluation board ( X-MPC5777C-561DS) is 37.4ms. This measured time is valid for: System clock PLL = 200MHz STCU module clock = System clock / 4 LBIST = 25MHz --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- LBIST on 50MHz I do not recommend to run LBIST at 50MHz as it was failing in my setup.

******************************************************************************** * Detailed Description: * Initializes eQADC module and cyclically converts chosen channel, displaying * it into terminal window. * User could connect EVB pot's wiper to pin header W (see below) to see valid * conversion result. * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  For ADC: J53-1 (EVB pot's wiper) --> PW7  - ANB16 *                                                       PW8  - ANB17 *                                                       PW9  - ANB18 *                                                       PW10 - ANB19 ********************************************************************************

******************************************************************************** * Detailed Description: * Example configures Sigma_Delta ADC and periodically converts ANA0_SDA0 input * (EVB's potentiometer can be connected i.e. J53-1 --> PO15) and displays * results in the terminal window (USBtoUART bridge J21). Terminal settings is * 19200-8-no parity-1 stop bit-no flow control on eSCI_A. * Example uses external ADC triggering from eTPU channels, that are for purpose * of this example configured for eTPU GPIO function for all eTPU channels that * can trigger start of SDADC conversion. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *                  eSCI_A is USBtoUART bridge (connector J21) * EVB connection:  For ADC: J53-1 (EVB pot's wiper) --> PO15 (header P22) * ********************************************************************************

Detailed Description:  Initializes the MCU including the FlexCAN peripherals.  Configures the FlexCAN to transmit and receive a CAN message.  In this config, CAN_0 transmits a message. CAN_1 receives the message.  CAN_0 MB8 is configured to send data each 1sec.This interval is generated by PIT.  CAN_1 RXFIFO is configured to receive a message and interrupt for MB5 is enabled.  To connect FlexCAN0 module (MCU's PB0/PB1 pins) to the motherboard's transceiver  with J5 CAN DB9 connector you have to:  - connect J17 2-6 on daughter board  - connect J17 5-3 on daughter board  This should be done as default    To connect FlexCAN1 module (MCU's PA14/PA15 pins) to the motherboard's transceiver  with J6 CAN DB9 connector you have to:  - connect J37 2-3 on motherboard  - connect J38 2-3 on motherboard  Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1  Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2  Terminate the CAN bus by connecting a 60 ohm resistor between CANH and CANL  To see LED toggling connect P8.1 to USER LED (P7.x)  ------------------------------------------------------------------------------  Test HW:  MPC5744P EVB  Maskset:  1N65H  Target :  RAM, internal_FLASH  Fsys:     200 MHz PLL with 40 MHz crystal reference