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When deploying a custom built model to replace the default models in MCUXpresso SDK examples, there are several modifications that need to be made as described in the eIQ Neutron NPU hands-on labs. Here are some common issues and error messages that you might encounter when using a new custom model with the SDK examples and how to solve them. If there is an issue not covered here, then please make a new thread to discuss that issue.    “Didn't find op for builtin opcode ‘<operator_name>’” Need to add that operator to MODEL_GetOpsResolver function found in source\model\model_name_ops_npu.cpp A full list of operators used by a model that can be copy-and-pasted into that file is automatically generated by Neutron Converter Tool with the dump-header-file option. Make sure to also increase the size of the static array s_microOpResolver to match the number of operators   “resolver size is too small” Need to increase the size of the static array s_microOpResolver in MODEL_GetOpsResolver function found in source\model\model_name_ops_npu.cpp to match the number of operators     “Failed to resize buffer” The scratch memory buffer is too small for the model and needs to be increased. The size of the memory buffer is set with the kTensorArenaSize variable found in the model data header file   “Internal Neutron NPU driver error 281b in model prepare!” or “Incompatible Neutron NPU microcode and driver versions!” Ensure the version of the eIQ Neutron Converter Tool used to convert the model is the correct one that is compatible with the NPU libraries used by the SDK project.  eIQ Toolkit v1.10.0 should be used with MCXUpresso SDK for MCX N 2.14.0. The Neutron Converter Tool version is 1.2.0+0X84d37e1f     Camera colors are incorrect on FRDM-MCXN947 board Modify solder jumpers SJ16, SJ26, and SJ27 on the back of board to move them to the left (dashed line side) to connect camera signals properly.             This modification will disable Ethernet functionality on the board due to a signal conflict with EZH D0 and ENET_TXCLK. If your project needs both camera and Ethernet functionality, then only move SJ16 and SJ26 to the left (dashed line side) and then connect a wire from P1_4 (J9 pin 😎 to the left side of R58. Then in the pin_mux.c file in the project, instead of using PORT1_PCR4 for EZH_Camera_D0, use PORT3_PCR0.                           
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Introduction This article describes the method to update the Boot ROM patch on MCX N94x / N54x devices to patch version T1.1.5.   Before beginning, note that this process can only be performed via ISP mode of the device and can only be performed using a command line method.  The NXP Secure Provisioning tool uses command line operations in its backend and does make these available to the user.  For directions on how to access the command line interface through the Secure Provisioning tool, consult your Secure Provisioning Tool documentation.  Command line blhost method ISP Pin Method 1) With the device powered off, assert the ISP pin (GPIO P0_6) by pulling this pin low. 2) With ISP pin still asserted, power on the device.   3) After the device has fully powered on (at least as long as the t_POR time quoted in the Power mode transition operating behaviors table of the MCX N94x / N54x datasheet), release the ISP pin.  4) Open a command prompt and set the working directory to your blhost installation. 5) Verify that the current version of ROM patch is not T1.1.5 using this command: blhost <interface> <parameters> -- get-property 24.  a) Where <interface> should be replaced with the code for the interface type and <parameters> should be replaced with the parameters of that interface.  For more information on this syntax, refer to the blhost User's Guide.   6) Execute this command:  blhost <interface> <parameters> receive-sb-file <path_to_file_location>/mcx_n10_a1_prov_fw_rp_v5.0.sb3.  7) Repeat steps 1 - 5 to verify that the ROM version is T1.1.5.  ISP Pin Unavailable - SWD Method 1) Connect to target via SWD 2) Open the secure provisioning tool 3) Select the serial interface window and select the command line button 4) Send the following command: nxpdebugmbox -i pyocd ispmode -m 0 5) Verify that the current version of ROM patch is not T1.1.5 using this command: blhost <interface> <parameters> -- get-property 24.  a) Where <interface> should be replaced with the code for the interface type and <parameters> should be replaced with the parameters of that interface.  For more information on this syntax, refer to the blhost User's Guide.   6) Execute this command:  blhost <interface> <parameters> receive-sb-file <path_to_file_location>/mcx_n10_a1_prov_fw_rp_v5.0.sb3 7) Repeat steps 1 - 5 to verify that the ROM version is T1.1.5.         
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FRDM Boards Enclosures (3D Print)   Hi NXP FRDM enthusiasts! we want to share some 3D files that you can use to 3D print your own enclosures for the FRDM-MCX family!    FRDM-MCXN947 case step files are here   FRDM-MCXA153 case step files are here   FRDM-MCXW71 case step files are here
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The table below contains notable updates to the current release of the Reference Manual. The information provided here is preliminary and subject to change without notice. Affected Modules Issue Summary Description  Date MCXNx4x Pinout xlsx Attachment Defeature PF* pins Erroneous pinouts to PF* signals on ALT11 are removed.  Before:    After:    01 March 2024 System Boot ROM API Missing Boot Modes sections in ROM API chapter of System Boot New sections added: 15.3 Boot modes 15.3.1 Master boot mode Master boot mode supports the following boot devices: Internal flash memory boot FlexSPI NOR flash memory boot SPI 1-bit NOR recovery boot Secondary bootloader boot Table 229. Image offsets for different boot media   Boot media Image offset Internal flash memory boot 0h FlexSPI NOR flash memory boot 1000h SPI 1-bit NOR recovery boot 0h Secondary bootloader boot 0h   15.3.2 Secondary bootloader mode   The Secondary bootloader mode can be enabled by setting the CMPA[BOOT_SRC] as 2, the image loaded in the Bank1_IFR0 region (0x0100_8000 to 0x0100_FFFF) will be set as primary boot mode, and the secondary boot image will boot first after the device reset. The secondary boot image type can be plain, crc or signed image, but cannot set as the SB file.   Based on the CMPA[OEM_BANK1_IFR0_PROT](0x01004004[5:7]) setting, after the secondary boot image boot, the Bank1_IFR0 region will be configured with different MBC setting:   Lifecycle CMPA[OEM_BANK1_IFR0_PROT] Secondary bootloader mode MBC IFR0 recovery boot MBC Develop (0x3) NA GLABC0 GLBAC0 Develop2 (0x7), In-field (0xF), In-field Locked (0xCF), Field Return OEM (1F) 0 GLBAC4 GLBAC4   1 GLBAC4 2 GLBAC2 3 GLBAC6 4 GLBAC4 5 6 7     01 March 2024 Input Multiplexing (INPUTMUX) Clarification to CMP trigger input registers Update to the CMPx_TRIG Register function description for the following registers: CMP0_TRIG (260h), CMP1_TRIG (4EOh), and CMP2_TRIG (500h)  Before:  Function This register selects the CMPx trigger inputs   After: Function This register selects the CMPx SAMPLE/WINDOW input 01 March 2024  
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Sometimes connecting things requires a lot of cables because the component you need alone doesn't have the correct connector to mount on an evaluation board.   A few weeks ago, we needed to connect this display Adafruit 1.54" 240x240 Wide Angle TFT LCD Display to some FRDM boards. We started using cables but ended up making a small card to mount the board and plug it directly into the PMOD port of the FRDM board.   We decided to make it available in case you have the same problem 😊   Adafruit 1.54" 240x240 Wide Angle TFT LCD Display PMOD Adapter Gerber files for fabrication are here Final Assembly   3D render     This is how it looks connected to a FRDM-RW612 board  enjoy!    
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In most cases, C project is generated and used. But assembly project has it’s own advantage, with assembly project, you can program with assembly language directly, can test assembly instruction with assembly mnemonic. Generally, C language is inefficient, so in order to test the performance of the core, or get peripheral highest performance, the assembly project is required. The doc discusses the procedure to create an assembly language project, in the end, gives an example to toggle a LED, which demos how to initialize the NVIC, CTimer, GPIO with assembly language. It also gives the example of subroutine.   1. The procedure to create an assembly language project based on MCUXPresso tools 1.1 Load MCUXPresso tools and drag SDK to the Installed SDK menu Then click “Create a new C/C++ project”   1.2 Select the board or processor, then clock “Next” software button   1.3 Name the project and Select the driver. In the menu, it is okay to use default configuration, then clock “Finish”   1.4 A New project called MCXN947_project is created with C language   1.5 Delete the MCXN947_project.c and add the main.s Click the “source” group with right mouse button, the click “New”->”source File”   1.6 Add the main.s as the following Fig and click “Finish”   1.7 The final project is like:   2.0 writing the assembly code in the main.s This is the code in main.s /* This assembly file uses GNU syntax */ .equ SYSCON_ANGCLKCTRLSET0,0x40000220 .equ SYSCON_AHBCLKCTRLSET1,0x40000224 .equ SYSCON_AHBCLKCTRLSET2,0x40000228 .equ SYSCON_CTIMER4CLKSEL, 0x4000027C .equ SYSCON_CTIMER4CLKDIV, 0x400003E0   /*PIO3_4 LED blue*/ .equ PORT3_PCR_BASE,0x40119000 .equ PORT3_PCR4,PORT3_PCR_BASE+0x90   .equ GPIO3_BASE,0x4009C000 .equ GPIO3_PDDR,GPIO3_BASE+0x54 .equ GPIO3_PDOR,GPIO3_BASE+0x40     /*PIT configuration*/ .equ CTIMER4_BASE,0x40010000 .equ CTIMER4_IR,CTIMER4_BASE+0x00 .equ CTIMER4_TCR,CTIMER4_BASE+0x04 .equ CTIMER4_MCR,CTIMER4_BASE+0x14 .equ CTIMER4_MR0,CTIMER4_BASE+0x18 .equ CTIMER4_MSR0,CTIMER4_BASE+0x78 .equ CTIMER4_PWMC,CTIMER4_BASE+0x74     /*NVIC configuration*/ /*refer to 4.2 Nested Vectored Interrupt Controller in Cortex-M4 Generic User's Guide.pdf*/ .equ NVIC_ISER0,0xE000E100 .equ NVIC_ISER1,0xE000E104   .equ NVIC_ICPR0,0xE000E284 .equ NVIC_ICPR1,0xE000E288   .equ NVIC_IPR12,0xE000E430 .equ NVIC_IPR14,0xE000E438           .global __user_mem_buffer1,__user_mem_buffer2     .text     .section   .rodata     .align  2     .LC0:       .text     .thumb     .align  2     .global main     .global CTIMER0_IRQHandler     .type main function   main:     push {r3, lr}     add r3, sp, #4     nop     BL peripheralInit     nop     nop     nop     nop     NOP     /*cpsie i*/ loop:     b loop     mov r3, #0     mov r0, r3     pop {r3, pc}     /*subroutine 1*/ /* copy 10 words from one place to another*/     .type MyFunc function     .func MyFunc:     push {r0,r1,r2,lr}     MOV R2,#0x00     LDR R0,=USER_MEM_BUFFER1     MOV R1,#0x00 loop1:     NOP     STR R1,[R0]     ADD R1,#0x10     ADD R0,#4     ADD R2,#1     CMP R2,#0x10     BNE loop1     AND R5,R1,R5 ;     ASR R3,R2,#1     ORR R5,R1,R5     ADD R3,R2,R3     ADC R3,R2,R3     AND R2,R1,R2 ; /*#0x0F*/     LDR R0,=0x1234     /*LDR R0, [R1], #4*/     nop     pop {r0,r1,r2,pc}     .endfunc /***************************************/   /*subroutine 2*/     .type peripheralInit function     .func peripheralInit:    //enable CTimer4 gated clock     LDR R0,=0x400000     LDR R1,=SYSCON_AHBCLKCTRLSET2     nop     STR R0, [R1]       MOV R0,#0x03 //select     LDR R1,=SYSCON_CTIMER4CLKSEL     nop     STR R0, [R1]         MOV R0,#0x09 //select     LDR R1,=SYSCON_CTIMER4CLKDIV     nop     STR R0, [R1]     /*setting CTimer0*/       //set Ctimer0_IR     MOV R3,#0x01     LDR R1,=CTIMER4_IR     Nop     LDR R2,[R1]     ORR R2,R2,R3     STR R2,[R1]     //set CTIMER4_MCR     MOV R3,#0x03     LDR R1,=CTIMER4_MCR     LDR R2,[R1]     ORR R2,R2,R3     STR R2,[R1]         LDR R0,=6000000     LDR R1,=CTIMER4_MR0     STR R0,[R1]       LDR R0,=6000000     LDR R1,=CTIMER4_MSR0     STR R0,[R1]         MOV R0,#00     LDR R1,=CTIMER4_PWMC     STR R0,[R1]       nop     nop //lop1: //  b lop1         /*setting interrupt, Ctimer4 IRQ 56*/     LDR R1,=NVIC_ISER1     LDR R0,[R1]     LDR R3,=0x01000000     ORR R0,R0,R3     STR R0,[R1]       LDR R1,=NVIC_ICPR1     LDR R0,[R1]     LDR R3,=0x01000000     ORR R0,R0,R3     STR R0,[R1]       MOV R0,#0x00     LDR R1,=NVIC_IPR14     STR R0,[R1]       /*pin mux setting*/     /*enable PORT3 and GPIO3 gated clock*/     LDR R0,=0x410000     LDR R1,=SYSCON_ANGCLKCTRLSET0     nop     STR R0, [R1]     /*set the GPIO3_4 as GPIO output mode*/     LDR R0,=#0x1000     LDR R1,=PORT3_PCR4     STR R0,[R1]         LDR R1,=GPIO3_PDDR     LDR R0,[R1]     LDR R3,=0x10     ORR R0,R0,R3     STR R0,[R1]       /*CTimer4 start*/     MOV R3,#0x01     LDR R1,=CTIMER4_TCR     LDR R0,[R1]     ORR R0, R0,R3     STR R0,[R1]     nop     nop     nop     /*cpsid i*/     BX LR     .endfunc /*********************************************/   /*subroutine 3*/     .text     .type testcal function     .func testCal:     LDR R0,=0x12345678     MOV R1,#0x0F     AND R0,R1     /*test saturation function*/     LDR R0,=0x8234     LDR R1,=0x8234     /*ADDS R5,R0,R1*/     QADD16 R6,R0,R1  /*saturation heppen, the R6 will become negative minumum 0x8000*/     nop     /***8888888*/       LDR R0,=0x6234     LDR R1,=0x6234     /*ADDS R5,R0,R1*/     SADD16 R6,R0,R1     nop     QADD16 R6,R0,R1 /*saturation heppen, the R6 will become negative minumum 0x7FFF*/     nop     SMUAD R6,R0,R1     BX LR     .endfunc /*********************************************/   /*interrupt service routine*/     .global CTIMER4_IRQHandler     .text     .align 2     .type CTIMER4_IRQHandler function     .func CTIMER4_IRQHandler:         /*clear interrupt*/     push {R0,R1,LR}     nop     nop     nop     LDR R1,=CTIMER4_IR     LDR R0,[R1] /*dummy reading*/     MOV R4,#0x10;     ORR R0,R0,R4     STR R0, [R1]     /*toggle a LED*/     LDR R1,=GPIO3_PDOR     LDR R0,[R1]     LDR R3,=0x10     EOR R0,R0,R3     STR R0,[R1]     NOP     POP {R0,R1,PC}     .endfunc     /******************************************************/ /*interrupt service routine*/     .global SVC_Handler     .text     .align 2     .type SVC_Handler function     .func SVC_Handler:     push {R0,R1,LR}            NOP     POP {R0,R1,PC} /******************************************************/       .align  2 .L3:     .word       .align 4     .section .contantData HELLO_TXT:     .space 0x100 Hello_END:     .ALIGN 4   /*.lcomm */   .lcomm USER_MEM_BUFFER1  0x100   .lcomm USER_MEM_BUFFER2  0x100     .end   3.0 code explanation   In the code, you have to define the main function, after the core has executed the code ResetISR(void), which is defined in startup_mcxn847_cm33_core0.c, it jump to main() function   The example code implement the function to initialize CTimer, GPIO and NVIC, SYSCON module so that the CTImer can generate interrupt, in the ISR of CTimer, a LED is toggled. After you run the code, you can see that the led is toggled. The peripheralInit Subroutine is used to initialize the CTimer, NVIC, GPIO, SYSCON module so that the CTimer can fire an interrupt and toggle a LED.The CTIMER4_IRQHandler is an ISR of CTimer4, which is defined in startup_mcxn847_cm33_core0.   The MyFunc function and testCal  Subroutines are just for testing a specific assembly instruction, and test how to establish and call a subroutines, they do not have a specific target.
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1. RS485 hardware connection RS-485 is a multiple drop communication protocol in which the LPUART transceiver's driver is three-stated unless LPUART is driving. The transmitter can uses the RTS_B signal to enable the driver of a transceiver. The polarity of RTS_B can be configured by firmware to match with the polarity of the transceiver's driver enabling signal. The following figure shows the receiver enabling signal asserted. This connection can also connect RTS_B to both DE and RE_B. The transceiver's receiver is disabled when the uart transmitter is sending char. A pullup can pull RXD to a non-floating value during this time. You can refine this option further by operating LPUART in Single-Wire mode, freeing the RXD pin for other uses.     When the uart transmits character via TXD pin, the RTS_b signal is asserted automatically, after the RS-485 transceiver, the urat transmitter can drive the differential signals Y/Z. When the uart dose not transmit character, the RTS_b signal is unasserted, so the RS-485 transceiver is in tr-state, the differential signal Y/Z is NOT driven by this RS-485 transceiver. For receiver part of the RS-485 transceiver, if the RTS_b sigbal is connected to the RE_b pin of receiver of RS-485 transceiver directly or via an inverter depending on the required logic of the RS-485 transceiver , when the uart transmits character, the receiver of  RS-485 transceiver is disabled, the RO pin of the RS485 is in tri-state, so a pull-up resistor is required on the RO pin and the RXD pin of LPUart can not receive any character from it’s own transmitter.  The RTS_B signal can function as hardware flow control, but note the application uses RTS_b signal to control RS485 enabling instead of hardware flow control. )   2. RTS_b pin assigmnet.   For the uart module of MCXN family, the FCx_P0 is RXD pin of UARTx module, the FCx_P1 is TXD pin of UARTx module, the FCx_P2 is RTS_b of UARTx module. For MCXN94x family, the P1_8 pin can function as FC4_P0 or RXD pin of UART4; the P1_9 pin can function as FC4_P1 or TXD pin of UART4; the P1_22 pin can function as FC4_P2 or RTS_b pin of UART4 with setting up PORT1_PCR22[MUX] bits as decimal 3;   3)software 3.1 pin assignment void BOARD_InitPins(void) {     /* Enables the clock for PORT1: Enables clock */     CLOCK_EnableClock(kCLOCK_Port1);       const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */                                                     kPORT_PullDisable,                                                     /* Low internal pull resistor value is selected. */                                                     kPORT_LowPullResistor,                                                     /* Fast slew rate is configured */                                                     kPORT_FastSlewRate,                                                     /* Passive input filter is disabled */                                                     kPORT_PassiveFilterDisable,                                                     /* Open drain output is disabled */                                                     kPORT_OpenDrainDisable,                                                     /* Low drive strength is configured */                                                     kPORT_LowDriveStrength,                                                     /* Pin is configured as FC4_P0 */                                                     kPORT_MuxAlt2,                                                     /* Digital input enabled */                                                     kPORT_InputBufferEnable,                                                     /* Digital input is not inverted */                                                     kPORT_InputNormal,                                                     /* Pin Control Register fields [15:0] are not locked */                                                     kPORT_UnlockRegister};     /* PORT1_8 (pin A1) is configured as FC4_P0 */     PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);       const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */                                                     kPORT_PullDisable,                                                     /* Low internal pull resistor value is selected. */                                                     kPORT_LowPullResistor,                                                     /* Fast slew rate is configured */                                                     kPORT_FastSlewRate,                                                     /* Passive input filter is disabled */                                                     kPORT_PassiveFilterDisable,                                                     /* Open drain output is disabled */                                                     kPORT_OpenDrainDisable,                                                     /* Low drive strength is configured */                                                     kPORT_LowDriveStrength,                                                     /* Pin is configured as FC4_P1 */                                                     kPORT_MuxAlt2,                                                     /* Digital input enabled */                                                     kPORT_InputBufferEnable,                                                     /* Digital input is not inverted */                                                     kPORT_InputNormal,                                                     /* Pin Control Register fields [15:0] are not locked */                                                     kPORT_UnlockRegister};     /* PORT1_9 (pin B1) is configured as FC4_P1 */     PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);       //* PORT1_22 (pin L4) is configured as FC4_P2 with ALT3*/       const port_pin_config_t port1_22_pinC3_config = {/* Internal pull-up/down resistor is disabled */                                                        kPORT_PullDisable,                                                        /* Low internal pull resistor value is selected. */                                                        kPORT_LowPullResistor,                                                        /* Fast slew rate is configured */                                                        kPORT_FastSlewRate,                                                        /* Passive input filter is disabled */                                                        kPORT_PassiveFilterDisable,                                                        /* Open drain output is disabled */                                                        kPORT_OpenDrainDisable,                                                        /* Low drive strength is configured */                                                        kPORT_LowDriveStrength,                                                        /* Pin is configured as FC4_P1 */                                                        kPORT_MuxAlt3,                                                        /* Digital input enabled */                                                        kPORT_InputBufferEnable,                                                        /* Digital input is not inverted */                                                        kPORT_InputNormal,                                                        /* Pin Control Register fields [15:0] are not locked */                                                        kPORT_UnlockRegister};        /* PORT1_9 (pin B1) is configured as FC4_P1 */        PORT_SetPinConfig(PORT1, 22U, &port1_22_pinC3_config); }   The   //P1_22 function as RTS_b signal void RTS_b_init(LPUART_Type *base) {  base->MODIR |=LPUART_MODIR_TXRTSE(1); //                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)   }   4)uart timing tested by scope   Conclusion: From the above scope screen shot, you can see that when the uart transmitter sends char, the RTS_b signal becomes low, so it can function as RS485 transceiver enabling signal.  
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The Serial Peripheral Interface (SPI) is ubiquitous in embedded systems for interfacing to external peripherals such flash memories, EEPROMs, analog to digital converters and sensors. SPI controllers are essentially shift registers. When combined with DMA, SPI can be used for interesting use cases. In this paper we will look at an LED lighting application and hint at some other interesting use cases such as PDM audio streams.
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Introduction This article describes the method to update the Boot ROM patch on MCX N23x devices to patch version T1.0.7 Before beginning, note that this process can only be performed via ISP mode of the device and can only be performed using a command line method.  The NXP Secure Provisioning tool uses command line operations in its backend and does make these available to the user.  For directions on how to access the command line interface through the Secure Provisioning tool, consult your Secure Provisioning Tool documentation.  Command line blhost method ISP Pin Method 1) With the device powered off, assert the ISP pin (GPIO P0_6) by pulling this pin low. 2) With ISP pin still asserted, power on the device.   3) After the device has fully powered on (at least as long as the t_POR time quoted in the Power mode transition operating behaviors table of the MCX N23x datasheet), release the ISP pin.  4) Open a command prompt and set the working directory to your blhost installation. 5) Verify that the current version of ROM patch is not T1.0.7 using this command: blhost <interface> <parameters> -- get-property 24.  a) Where <interface> should be replaced with the code for the interface type and <parameters> should be replaced with the parameters of that interface.  For more information on this syntax, refer to the blhost User's Guide.   6) Execute this command:  blhost <interface> <parameters> receive-sb-file <path_to_file_location>/mcx_n11_a0_prov_fw_rp_v7.0.sb3.  7) Repeat steps 1 - 5 to verify that the ROM version is T1.0.7.  ISP Pin Unavailable - SWD Method 1) Connect to target via SWD 2) Open the secure provisioning tool 3) Select the serial interface window and select the command line button 4) Send the following command: nxpdebugmbox -i pyocd ispmode -m 0 5) Verify that the current version of ROM patch is not T1.0.7 using this command: blhost <interface> <parameters> -- get-property 24.  a) Where <interface> should be replaced with the code for the interface type and <parameters> should be replaced with the parameters of that interface.  For more information on this syntax, refer to the blhost User's Guide.   6) Execute this command:  blhost <interface> <parameters> receive-sb-file <path_to_file_location>/mcx_n11_a0_prov_fw_rp_v7.0.sb3 7) Repeat steps 1 - 5 to verify that the ROM version is T1.0.7. 
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NXP officially launched the MCX C series chips in July 2024. As a Cortex-M0+ MCU with high cost-effectiveness, energy efficiency, and security, it strongly supports the upgrade of traditional 8-bit and 16-bit designs. Since its release, the chip has gained rapid favor among customers, with many projects now entering mass production. In practical applications, more and more customers have inquired about how to enter the ISP mode of MCX C series chips and complete firmware updates. We have previously introduced the method using the blhost tool (see MCX C: How to Enter the ROM Bootloader to Update the Firmware - NXP Community). It is worth noting that the MCUXpresso Secure Provisioning (SEC) tool now supports MCX C series chips starting from version 25.03. The operation process is described in detail below. Refer to the attached PDF file for details.
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1.Overview The NXP MCXN947 is a high-performance microcontroller that supports booting from either internal or external Flash memory. For most embedded applications, the on-chip Flash provides sufficient capacity to host both code and resources. However, in domains such as AI, image processing, or speech recognition—especially when deploying large neural network models with the eIQ toolchain—the size of the models can easily exceed the available internal Flash space. Although the MCXN947 supports executing directly from external Flash (XIP), the system typically boots from a fixed entry point in either internal or external Flash. This raises the question: can we combine the best of both worlds by booting from internal Flash while placing large resources or code segments in external Flash for direct execution? This article presents a demo implementation of exactly such a hybrid “internal boot + external XIP execution” scheme. The approach preserves fast and flexible system startup, while significantly expanding available storage capacity—ideal for hosting large AI models. Hardware Environment: Development Board: FRDM-MCXN947 Software Environment: IDE: MCUXpresso IDE v11.9.0 SDK: SDK Builder | MCUXpresso SDK Builder (nxp.com) Base Project: frdmmcxn947_tflm_cifar10 2. External Flash Hardware Configuration and Pin Assignment The FRDM-MCXN947 board integrates an external 8-line Octal Flash, connected to the MCU’s FlexSPI interface. The key pin assignments are as follows: Octal Flash Pin Function MCXN947 Connection HyperRAM Chip Pin Function Connected to MCXN947 CS SPI communication chip select signal P3_0 / FLEXSPI0_A_SS0_b SCK SPI communication clock signal P3_7 / FLEXSPI0_A_SCLK DQS SPI communication data strobe signal P3_6 / FLEXSPI0_A_DQS DQ0 OSPI data signal D0 P3_8 / FLEXSPI0_A_DATA0 DQ1 OSPI data signal D1 P3_9 / FLEXSPI0_A_DATA1 DQ2 OSPI data signal D2 P3_10 / FLEXSPI0_A_DATA2 DQ3 OSPI data signal D3 P3_11 / FLEXSPI0_A_DATA3 DQ4 OSPI data signal D4 P3_12 / FLEXSPI0_A_DATA4 DQ5 OSPI data signal D5 P3_13 / FLEXSPI0_A_DATA5 DQ6 OSPI data signal D6 P3_14 / FLEXSPI0_A_DATA6 DQ7 OSPI data signal D7 P3_15 / FLEXSPI0_A_DATA7 The configuration code begins with  /* Enables the clock for PORT3: Enables clock */ CLOCK_EnableClock(kCLOCK_Port3); const port_pin_config_t port3_0_pinB17_config = {/* Internal pull-up/down resistor is disabled */ kPORT_PullDisable, /* Low internal pull resistor value is selected. */ kPORT_LowPullResistor, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive input filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain output is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Pin is configured as FLEXSPI0_A_SS0_b */ kPORT_MuxAlt8, /* Digital input enabled */ kPORT_InputBufferEnable, /* Digital input is not inverted */ kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORT3_0 (pin B17) is configured as FLEXSPI0_A_SS0_b */ PORT_SetPinConfig(PORT3, 0U, &port3_0_pinB17_config);   The same procedure is repeated for all FlexSPI pins. 3. FlexSPI Module Initialization To enable XIP from external Flash, the FlexSPI peripheral must be properly initialized.   3.1. Configure the FlexSPI clock /* Flexspi frequency 150MHz / 2 = 75MHz */ CLOCK_SetClkDiv(kCLOCK_DivFlexspiClk, 2U); CLOCK_AttachClk(kPLL0_to_FLEXSPI); /*!< Switch FLEXSPI to PLL0 */ 3.2 Initialize the FlexSPI driver Integrate the FlexSPI driver, which is provided in the SDK, into the project, /*Get FLEXSPI default settings and configure the flexspi. */ FLEXSPI_GetDefaultConfig(&config); /*Set AHB buffer size for reading data through AHB bus. */ config.ahbConfig.enableAHBPrefetch = true; config.rxSampleClock = EXAMPLE_FLEXSPI_RX_SAMPLE_CLOCK; config.ahbConfig.enableAHBBufferable = true; config.ahbConfig.enableAHBCachable = true; FLEXSPI_Init(base, &config); /* Configure flash settings according to serial flash feature. */ FLEXSPI_SetFlashConfig(base, &deviceconfig, FLASH_PORT); #if defined(EXAMPLE_FLASH_RESET_CONFIG) uint32_t TempFastReadSDRLUTCommandSeq[4]; memcpy(TempFastReadSDRLUTCommandSeq, FastReadSDRLUTCommandSeq, sizeof(FastReadSDRLUTCommandSeq)); #endif   4. Configure MCUXpresso Project to Support Octal Flash In MCUXpresso IDE, go to MCU Settings > Memory, and add a new memory region: Name: OSPI_FLASH (or OCTAL_FLASH) Start Address: Set according to the external flash address connected to your chip. According to the user manual, the FLEXSPI start address is 0x80000000. Size: For example, 128MB Next, select the corresponding external flash driver provided by NXP. The FRDM_MCXN947 board is connected to the mt35xu512aba flash, which supports SFDP, so we can choose MCXN9xx_SFDP_FlexSPI.cfx. After adding it, you will see the memory details displayed. 5. Add Linker Script and Migrate Model Data 5.1 Create Linker Script Fragments Add two files to the linkscripts/ folder in your project: text.ldt (for code sections) rodata.ldt (for model read-only data) Contents: <#if memory.name=="OSPI_FLASH"> KEEP (*(.model_data*)) KEEP (*(model.o*)) KEEP(*(.text.OSPI_FLASH*)) *(.text.QSPI_FLASH*) *(.text.${memory.alias}*) *(.text.${memory.name}*) </#if> This ensures that model data (e.g., the .model_data section) is properly retained and placed in the XIP (Execute In Place) region. 5.2 Place Model Data in XIP Region Use the following method to place the model into the .model_data section (in C code): __attribute__((section(".model_data"))) const unsigned char model_data[] = { #include "model_data.inc" }; 6. Build and Verify After building the project, the Image Memory Map Report in MCUXpresso IDE will show that parts of the .text and .rodata sections have been successfully placed into the Octal Flash (OSPI_FLASH) region. For example: OSPI_FLASH:      100144 B    262140 KB      0.04% After downloading and running the program, the system boots from internal Flash and successfully reads model data directly from external Flash, completing the AI inference task.   Conclusion Through the configuration steps introduced in this article, the MCXN947 successfully implements a hybrid storage solution combining internal boot with external XIP execution. This approach retains the advantage of fast boot speed while significantly expanding the available storage capacity for programs and models, providing strong support for deploying complex AI models. For resource-constrained MCU platforms, this architecture is not only a practical and feasible choice, but also represents an optimized strategy that is likely to be widely adopted in future embedded AI applications.
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Overview NXP FRDM-MCXN947 board is a low-cost design and evaluation board based on the MCXN947 device. NXP provides tools and software support for the MCXN947 device, including hardware evaluation boards, software development integrated development environment (IDE), sample applications, and drivers. The board is equipped with Ethernet PHY, and also supports camera modules and NXP's low-cost LCD module PAR-LCD-S035.   In this article, we will explore how to simultaneously implement Ethernet connection transmission and image acquisition using a camera on the MCXN947 board. Hardware Environment Development Board: FRDM-MCXN947 Display: 3.5" TFT LCD (P/N PAR-LCD-S035) Camera: OV7670 Network Cable: RJ45 Software Environment IDE: MCUXpresso IDE v11.9.0 SDK: MCUXpresso SDK Builder (nxp.com) Pin Configuration and Multiplexing When designing circuits, attention must be paid to avoiding pin conflicts, that is, ensuring that the same pin is not configured to perform conflicting functions at different times. When configuring pin functions, it is necessary to consider whether their electrical characteristics (such as voltage range, current drive capability, etc.) meet the requirements of the peripherals. When writing software, it is necessary to consider the support for pin multiplexing in different versions of MCU firmware or library files to ensure software compatibility and stability. Import the " lwip_examples " -> " lwip_ping_bm " project from the FDRM-MCXN947 SDK, open the board -> pin_mux.c file, and you can see the pin configuration for Ethernet connection as shown in the table below: Pin Name Pinmux Assignment P1_4 ALT9 - ENET0_TX_CLK P1_5 ALT9 - ENET0_TXEN P1_6 ALT9 - ENET0_TXD0 P1_7 ALT9 - ENET0_TXD1 P1_8 ALT9 - ENET0_TXD2 P1_9 ALT9 - ENET0_TXD3 P1_13 ALT9 - ENET0_RXDV P1_14 ALT9 - ENET0_RXD0 P1_15 ALT9 - ENET0_RXD1 P1_20 ALT9 - ENET0_MDC P1_21 ALT9 - ENET0_MDIO   Download the schematic of the MCXN947 board from NXP's official website, and find the modules corresponding to Camera and FlexIO LCD, as shown below:   FlexIO is a flexible input/output (I/O) technology developed by NXP, used to provide high-speed, programmable communication capabilities between microcontrollers (MCU) and external devices. It allows developers to configure the FlexIO module inside the microcontroller to simulate various communication protocols and develop custom protocols. Note: This LCD only supports 3V I/O voltage, so when configuring all pins on this connector, you must ensure they are all set to 3V3 operation mode. The following diagram shows the working principle of the SDK example, where the camera collects images and transmits them to the LCD display: It can be seen that the LCD module does not have any pin conflicts with the pins required for Ethernet and Camera functions, while the pins required for configuring the Camera module are duplicated with Ethernet. The pin reuse can be found in the datasheet provided on the NXP official website as shown in the following table: Pin Name Pinmux Assignment P0_4 ALT0 - P0_4 P0_5 ALT0 - P0_5 P1_4 ALT7 - SmartDMA_PIO0 P1_5 ALT7 - SmartDMA_PIO1 P1_6 ALT7 - SmartDMA_PIO2 P1_7 ALT7 - SmartDMA_PIO3 P1_10 ALT7 - SmartDMA_PIO6 P1_11 ALT7 - SmartDMA_PIO7 P1_18 Default-PIO-Low P1_19 Default-PIO-High P2_2 ALT1 - CLKOUT P3_2 ALT2 - FC7_P0 P3_3 ALT2 - FC7_P1 P3_4 ALT7 - SmartDMA_PIO4 P3_5 ALT7 - SmartDMA_PIO5 As seen above, pins P1_4, P1_5, P1_6, and P1_7 conflict directly with Ethernet pins. Since Ethernet pins are fixed to the RJ45 PHY, the Camera interface must be reassigned to alternate pins. From the datasheet, P3_0, P3_1, P3_2, and P3_3 can serve as alternatives. However, P3_2 and P3_3 are already used for I²C. To resolve this, they are reassigned to P3_8 and P3_7 respectively (using kPORT_MuxAlt3). The updated pin mapping is shown below: Previous Pin Current Pin Pinmux Assignment P1_4 P3_0 ALT7 - SmartDMA_PIO0 P1_5 P3_1 ALT7 - SmartDMA_PIO1 P1_6 P3_2 ALT7 - SmartDMA_PIO2 P1_7 P3_3 ALT7 - SmartDMA_PIO3 P3_2 P3_8 ALT3 - FC7_P0 P3_3 P3_7 ALT3 - FC7_P1   Implementation The reassigned pins (P3_0, P3_1, P3_7, P3_8) are not exposed on the board’s headers, but the schematic shows that they are connected to test pads TP12, TP31, TP18, and TP16. The camera can be wired to these pads directly.   Pin Name Solder Pad P3_0 TP12 P3_1 TP31 P3_7 TP18 P3_8 TP16     Integrate the smartdma_camera_flexio_mculcd example from display_examples into the lwip_ping_bm project. Merge .c and .h files from board , drivers , component , and source folders. Add these folders to the include path under Project -> Properties -> C/C++ Build -> Settings -> Includes .   After integration, compile and flash the project to the board. The output is shown in the images.   Conclusion The Ethernet and Camera functions can be simultaneously implemented on the MCX N947 board. The lwip_ping_bm demo showcases ICMP-based Ping functionality using the lwIP TCP/IP stack. It periodically sends ICMP echo requests to a PC and processes the replies. The smartdma_camera_flexio_mculcd demo demonstrates how to use SmartDMA to capture image data frame-by-frame from the OV7670 camera and display it on the ST7796S LCD panel via FlexIO. By reconfiguring and multiplexing pins, simultaneous use of Ethernet and Camera on the MCX N947 is achievable.  
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1. Introduction During recent customer technical support, we have find that power supply design issues frequently occur when using MCXN94X/MCXN54X products with HLQFP 100-pin packaging. To address this, we have developed this design guide specifically for 100-pin packaged chips, based on the power supply design diagrams provided in the MCX Nx4x Power Management User Guide (UG10101). Description of Package Types The MCXNx4x series currently includes three package types: VFBGA 184-pin HDQFP 172-pin HLQFP 100-pin The power supply design solutions in the User Guide(UG10101) primarily target the 172-pin and 184-pin packages. 2. Special Design Requirements for HLQFP 100-Pin Packages 2.1 Power Supply Design Solution for HLQFP 100-Pin Packages (LDO_CORE Mode) When using a 100-pin MCXNx4x chip and selecting the LDO_CORE mode (with DCDC_CORE disabled), the power supply design shall comply with the following specifications: Key Design Differences 1)Shared Power Pin Characteristics In the 100-pin package, VDD_DCDC and VDD_LDO_SYS share the same pin. When DCDC_CORE is turned off, DCDC_LX must be left floating, and the DCDC function must be disabled through software configuration. 2) Port Power Supply Design The power supply pin Vdd_p2 for PORT2 shares a single pin with VDD. The 100-pin packaged chip cannot provide independent power supply to PORT2; instead, it must be uniformly powered by VDD, consistent with the power supply configuration for PORT0/PORT1. 2.2 Power Supply Design Solution for 100-Pin Packages (DCDC_CORE Mode) If the DCDC_CORE mode is used (with LDO_CORE turned off), the 100-pin chip can directly refer to the MCX Nx4x Power Management User Guide (UG10101). However, special attention must be paid to the following: PORT2 still cannot be supplied with independent power and must adhere to the port power supply design requirements specified above. 3.Technical Support If you have any issues during the power supply design of MCXNx4x series chips, please feel free to leave a message for communication at any time.   Thanks for Yang Zhang's help with the review.  
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In order to recover your board, you need to accomplish the following: Ensure that your PC successfully enumerates the LinkServer debugger under the COM ports. Confirm that you can attach to the running code on the board. When attempting to program the board, the following error appears:   The device stops during initialization because the value of SIM_CHIPCTL is not set to its default after reset. This happens because SRAMU and SRAML are retained across resets, which causes a flash initialization error. To resolve this issue, modify the debug script to override the SIM_CHIPCTL register with its default value: 0x0030_0000. Locate the file MCXE24x_connect.scp. If you are using the default installation path, it should be located at: C:\NXP\LinkServer_YourVersion\binaries\Scripts   Open the file and add the line "Poke32 this 0x40048004 0x00300000" I recommend do it after the "Release NRESET" message.     Note: You need to add a number to each line of code    After making this change, you should be able to program your MCX E24x board as usual.
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