iMX8QXP/iMX8QM have hardware JPEG decoder: The JPEG-D-X core. This is the example code to use this hw decoder in M4 SDK to decode JPEG files. M4_JPEG_DECODER_SDK_2.5.1.7z The attached "rear_view_camera_jpegdec.tar.bz2" is the updated source code for "SDK\boards\mekmimx8qx\demo_apps\rear_view_camera". It is based on SDK 2.5.1 for iMX8QXP MEK. The "rear_view_camera_jpegdec.patch" is the modified code, it hasn't included the added "fsl_jpeg_dec.c" and "fsl_jpeg_dec.h".   The testing used two 256*256 JPEG files, they are RGB color space. We used followed commands to build them into flash.bin: ./mkimage_imx8 -soc QX -rev B0 -append ahab-container.img -c -scfw scfw_tcm.bin -m4 m4_rear_view_camera.bin 0 0x34FE0000 --data demo_rgb.jpg 0x84000000 --data demo_rgb2.jpg 0x84008000 -out flash.bin   If customer need change the JPEG resoluion, they can change them in file "fsl_jpeg_dec.h", APP_JPEG_SIZE_OF_KB is the JPEG file length in memory, aligned in KB.   #define APP_JPEG_WIDTH (256) #define APP_JPEG_HEIGHT (256) #define APP_JPEG_SIZE_OF_KB (32) #define APP_JPEG_FORMAT JPEG_RGB #define APP_JPEG_BUFFER (0x84000000)   To created RGB format JPEG file from RGB data, the customer can use linux unit test application "/unit_tests/JPEG/encoder_test.out". M4_JPEG_DECODER_WINDOW_MODE_SDK_2.5.1.7z Based on JEPG decoder, added DPU CSC support and render JEPG decoded video in overlay window. The architecture is followed: NXP logo is put in FetchLayer0 with RGB565 format, after LayerBlend0, it will be the prim layer for LayberBlend1 (FetchLayer0 can't be used as prim layer for LayerBlend), the JPEG decoder output is put to FetchDecoder0. RGB888 format, and it will be resize to 640*480, and put to x=100, y=100 of the display. (Only the sec layer of LayerBlend can be window mode). Some limitation for layer selection in LayerBlend:

Recently I published this i.MX Dev Blog post about the Gateworks plugin gst-variable-rtsp-server support for i.MX 6. Now, you can check how to use it on i.MX 8 SoCs as well. 1. Preparing the image In order to use gst-variable-rtsp-server plugin, prepare your machine and distro: Add the following line to conf/local.conf: IMAGE_INSTALL_append += "gstreamer1.0-rtsp-server gst-variable-rtsp-server" Download the attached patch and apply it by doing: $ cd <yocto_path>/sources/meta-fsl-bsp-release/ $ git am ~/Download/0001-Add-RTSP-support-for-i.MX-8-L4.14.78_ga1.0.0-or-olde.patch Note: This patch is not necessary for L4.14.98_ga2.0.0 BSP! Then, build the image with bitbake and deploy it to the SD card. 2. Video Test Source Example Server $ gst-variable-rtsp-server -p 9001 -u "videotestsrc ! v4l2h264enc ! rtph264pay name=pay0 pt=96" Client 2. Camera Example Server $ gst-variable-rtsp-server -p 9001 -u "v4l2src device=/dev/video0 ! video/x-raw,width=640,height=480 ! v4l2h264enc ! rtph264pay name=pay0 pt=96" Client In order to use VLC or other application as the client, just enter the URL as shown in the image below:

The iMX8QM LVDS has followed work mode, (There are two LVDS modules in IMX8QM): Single mode (LVDS panel connects to one channel) panel 1 and panel 2 can be different panels: Dual channel split mode (The panel needs two LVDS channels, CH0 for 1,3,5,7,... pixels and CH1 for 2,4,6,8,... pixels): Mirror dual mode (The two panels on same LDB PHY should be same panels on pixel clock and resolution, panel 1 and panel 2 are same; panel 3 and panel 4 are same): The reference patch is based on L5.4.3_GA1.0.0 BSP. LVDS single mode and dual channel split mode are supported in default Linux BSP. Patch 0002 can be used to test this dual mode on MEK board, some rework is needed on MEK board:     R194, R195, R208, R209, R213, R214 should be mounted. And the I6263 board can't be connected to LVDS0_CH0 and LVDS0_CH1 at the same time. The I6263 board can't be connected to LVDS1_CH0 and LVDS1_CH1 at the same time too. Note: for iMX8QXP, there is no mirror dual mode support, because its two LVDS ports are from two different LDB modules, there are no CH1 for them: Note: for iMX8QXP dual channel split mode (The pixel order can be switched: LDB1_CH0 for 1,3,5,7,... pixels and LDB2_CH0 for 2,4,6,8,... pixels; or LDB2_CH0 for 1,3,5,7,... pixels and LDB1_CH0 for 2,4,6,8,... pixels), iMX8QM LVDS has no such feature.

  1.overwrite the sources/meta-freescale/recipes-security/optee-imx with optee-imx.zip 2.add below code to conf/local.conf DISTRO_FEATURES_append += " systemd" DISTRO_FEATURES_BACKFILL_CONSIDERED += "sysvinit" VIRTUAL-RUNTIME_init_manager = "systemd" VIRTUAL-RUNTIME_initscripts = "systemd-compat-units" MACHINE_FEATURES_append += "optee" DISTRO_FEATURES_append += "optee" IMAGE_INSTALL_append += "optee-test optee-os optee-client optee-examples" 3.bitbake optee-examples or bitbake imx-image-xxx You can directly install optee-examples_3.11.0-r0_arm64.deb in your device.  

Introduction This document describes the Spread Spectrum support for displays on i.MX 8QuadMax and i.MX 8QuadXPlus, specific for LVDS display. It describes the underlying HW function, how to enable it and the intended capability. The display controller (DC) subsystem on i.MX 8QuadMax and i.MX 8QuadXPlus uses an AVPLL to generate the reference clock for operation of the LVDS PHYs.  Enabling Spread Spectrum on the reference clock will result in the PHY interfaces being spread as well. This Spread Spectrum feature is controlled by the SCU firmware and can be enabled or disabled by configuring the board file of the SCU firmware porting kit. (The Spread Spectrum feature is added starting from SCFW porting kit V1.2.2 release which can be download from NXP web site “i.MX Software and Development Tool”.) The User Guide will include following content: 1. Introduction ............................................................................ 1 2. Configuration of the frequency modulation ......................... 2 3. Support in SCFW Porting Kit ............................................... 4 4. Modulation Characteristics ................................................... 4 5. Enablement Example ............................................................. 5 6. Revision History .................................................................... 7 For more information, please check the attachment "User Guide of Spread Spectrum for i.MX8QM_QXP Display.pdf".   Rev2.0 Update For SCFW Porting Kit V1.2.5 and later version, please check document "User Guide of Spread Spectrum for i.MX8QM_QXP Display 2.0.pdf" with updated algorithm. Rev2.1 Update For SCFW Porting Kit V1.2.10 and later version, please check document "User Guide of Spread Spectrum for i.MX8QM_QXP Display 2.1.pdf" with fspread value selection feature. Users can choose the percentage of frequency spread from following values: 0%, 0.4%, 1.0%, 1.4%, 2.0%.

 

Attachched is the reference patch to enable the PMIC external watchdog in SCFW, it is based on SCFW porting kit v1.1.2 from NXP website: https://www.nxp.com/webapp/Download?colCode=L4.14.78_1.0.0_SCFWKIT&appType=license&location=null Please apply the patches to "imx-scfw-porting-kit-1.1.2/src/scfw_export_mx8qx_b0" On iMX8QXP MEK board, the patches will enable the PF8100 watchdog by macro "#define ENABLE_PMIC_EXTERNAL_WDOG", and it will refresh the watchdog timer by I2C interface. The default timeout value is 0xD for 8192ms (#define PMIC_EXTERNAL_WDOG_TIMEOUT  0xD), and SCFW will refresh it with 1000ms period (board_pmic_wdog_refresh_period_ms = 1000U). When the iMX8 system goto low power mode, it will pull SCU_PMIC_STANDBY to notify the PMIC, then PMIC will switch to suspend mode too, during PMIC suspend mode, this watchdog timer is off too. It will restart after PMIC resume to normal mode. Without PMIC OTP burning for WDOG, the current setting of patch will trigger hard reset after PMIC WDOG is timeout. 0001-scfw-add-board-board-tick.patch This patch is used to added polling ticket in board.c, after SCFW running, it will call board_tick() with 10ms period. In future SCFW release, this patch is not needed to apply, it is in default code, only when SCFW porting kit version is 1.1.2 and early version, you need apply this patch. 0002-scfw-enable-pmic-external-wdog.patch This is the reference patch to enable the PF8100 watchdog timer and refresh code. iMX8QXP MEK is used as the example. Note: In default SCFW, it had already used internel watchdog to make sure SCFW is always running, if SCFW is built as no debug version (M=0 D=0), all SCFW halt will cause SOC reset. And if hardware had connected the SCU_WDOG_OUT pin from iMX8QXP to PMIC's WDI pin, then during SOC reset, the PMIC will also do hard reset to make a POR reboot for the whole system.

The document to descript change the u-boot environment variables under the Linux rootfs.  Also provide a demo on i.MX6ull evk of sdcard mirror.  Linux fw_printenv fw_setenv to access U-Boot's environment variables.pdf  --- the document fw_printenv_fw_setenv_demo_iMX6ullevk_L4.14.98_2.0.0_ga.sdcard  --- demo sdcard mirror

The System Controller Unit (SCU) is in charge of controlling several features related to power management of the whole system. The user gets access to the following features through the System Controller Firmware: Powering up/down the system,resources and partitions Configuring resource clocks Reset controls Configuring wake-up sources This document will cover the more commonly used features, for details on the full capabilities of the API please refer to the API document for your device. Resource Power Control The SCU is in charge of managing power control to the resources (peripherals) in the SoC. Attempting to access a resource on the OFF state will result in a bus error or a hang All resources are organized within several subsystems, subsystems group together resources with common functionality. Subsystems are independent of each other and have their own PLLs and power domains, this allows modular control of clocks and power to the resources. The System Controller Unit has a dedicated I2C channel to interact with the PMIC, this allows dynamic control of some power sources for resources like the GPUs and Cortex-A cores. The SCU can enable/disable the LDO that supplies power to the GPU for instance and also turn on/off the internal power domains. The mapping of PMIC supplies and resources happens on the board.c (included in the SCFW Porting kit) and it is part of the porting process of the SCFW to new boards. The function board_get_pmic_info is where the mapping of resources to supplies happen, see: /*--------------------------------------------------------------------------*/ /* Get the pmic ids and switchers connected to SS. */ /*--------------------------------------------------------------------------*/ static void board_get_pmic_info(sc_sub_t ss,pmic_id_t *pmic_id, uint32_t *pmic_reg, uint8_t *num_regs) { /* Map SS/PD to PMIC switch */ switch (ss) { case SC_SUBSYS_A53 : pmic_init(); {/* PF8100_dual Card */ pmic_id[0] = PMIC_0_ADDR; pmic_reg[0] = PF8100_SW5; *num_regs = 1U; } break; case SC_SUBSYS_A72 : pmic_init(); {/* PF8100_dual Card */ pmic_id[0] = PMIC_0_ADDR; pmic_reg[0] = PF8100_SW3; pmic_id[1] = PMIC_0_ADDR; pmic_reg[1] = PF8100_SW4; *num_regs = 2U; } break; case SC_SUBSYS_GPU_0 : pmic_init(); {/* PF8100_dual Card */ pmic_id[0] = PMIC_1_ADDR; pmic_reg[0] = PF8100_SW1; pmic_id[1] = PMIC_1_ADDR; pmic_reg[1] = PF8100_SW2; *num_regs = 2U; } break; case SC_SUBSYS_GPU_1 : pmic_init(); {/* PF8100_dual Card */ pmic_id[0] = PMIC_1_ADDR; pmic_reg[0] = PF8100_SW3; pmic_id[1] = PMIC_1_ADDR; pmic_reg[1] = PF8100_SW4; *num_regs = 2U; } break; default : ; /* Intentional empty default */ break; } }‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ Only some subsystems have their own dedicated external power supplies, in the example above A cores and GPUs are the only ones with a dedicated external power supplies. Most of the other subsystems are powered from the main power supply and power gating happens internally, each subsystem contains different power domains that can be turned on/off to manage power consumption. The SCFW API used to power on/off resources is the following: sc_err_t sc_pm_set_resource_power_mode (sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_power_mode_t mode)‍‍‍‍‍ Where: ipc - is the interprocessor communication channel used to communicate with the SCU (obtained by calling sc_ipc_open). resource - is the resource that will have the power mode change mode - is the power mode to change to The available power mode options are the following: Power mode Voltage Clocks SC_PM_PW_MODE_OFF OFF All clocks off SC_PM_PW_MODE_STBY ON All clocks off SC_PM_PW_MODE_LP ON PLLs off resource running from XTAL SC_PM_PW_MODE_ON ON PLLs on In order to be able to access a resource it must be at least on SC_PM_PW_MODE_LP mode, since that mode has the resource voltage on and the clock is supplied by the 24MHz crystal. For more details please refer to the SCFW API document. Clocks Configuration As in the power management case, clocks are also organized in a distributed manner within the device. Each subsystem has it's own PLLs and all of them are clocked by the 24MHz crystal. The number of PLLs in each subsystem varies between all subsystems. To see how many PLLs are within a subsystem please refer to the datasheet of the device you are interested on. For instance on the datasheet of the i.MX8QXP on table 16 in Chapter 4.3.1: It can be seen that the GPU subsystem contains two PLLs, the ADMA subsystem contains 4 PLLs, Display Controller 3, etc... The SCFW API used to configure a clock is the following: sc_err_t sc_pm_set_clock_rate ( sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_pm_clock_rate_t ∗ rate )‍‍‍‍‍ Where: ipc - is the interprocessor communication channel used to communicate with the SCU (obtained by calling sc_ipc_open). resource - is the resource that will have the clock rate change clk - is the clock to set the rate to (each resource can have different clocks associated with it for instance the GPU resource has a clock associated for its shader and another for the GPU, this parameter is used to identify the clock) rate - this contains the desired clock rate, the SCFW will try to match the provided rate if not possible it will then set the closest possible value and return the value that was actually configured. To identify the clk that needs to be passed, please refer to the SCFW API chapter called "Clock List" That chapter contains a table with all the different clocks that are configurable by the SCFW, in the case of the GPUs for instance to select the rate for the Shader or GPU, either the SC_PM_CLK_MISC or SC_PM_CLK_PER options would have to be selected. Set=Y indicates the clock/PLL is not shared and the rate can be set via sc_pm_set_clock_rate(). Enable=Y indicates the clock is not auto gated and must be enabled via sc_pm_clock_enable(). As an example the following snippet configures the GPU_0 shader clock: sc_clock_rate_t shader_clk=700000000; // 700 MHz sc_pm_set_clock_rate(ipc, SC_R_GPU_0_PID0, SC_PM_CLK_MISC, &shader_clk);‍‍ System Controller Firmware 101 

UPDATE: Note that this document describes eIQ Machine Learning Software for the NXP L4.14 BSP release. Beginning with the L4.19 BSP, eIQ Software is pre-integrated in the BSP release and this document is no longer necessary or being maintained. For more information on eIQ Software in these releases (L4.19, L5.4, etc), please refer to the "NXP eIQ Machine Learning" chapter in the Linux User Guide for that specific release.  Original Post: eIQ Machine Learning Software for iMX Linux 4.14.y kernel series is available now. The NXP eIQ™ Machine Learning Software Development Environment enables the use of ML algorithms on NXP MCUs, i.MX RT crossover processors, and i.MX family SoCs. eIQ software includes inference engines, neural network compilers, and optimized libraries and leverages open source technologies. eIQ is fully integrated into our MCUXpresso SDK and Yocto development environments, allowing you to develop complete system-level applications with ease. Source download, build and installation Please refer to document NXP eIQ(TM) Machine Learning Enablement (UM11226.pdf) for detailed instructions on how to download, build and install eIQ software on your platform. Sample applications To help get you started right away we've posted numerous howtos and sample applications right here in the community. Please refer to eIQ Sample Apps - Overview. Supported platforms eIQ Machine learning software for i.MX Linux 4.14.y supports the L4.14.78-1.0.0 and L4.14.98-2.0.0 GA releases running on i.MX 8 Series Applications Processors. For more information on artificial intelligence, machine learning and eIQ Software please visit AI & Machine Learning | NXP.

Platform: i.mx8qm/qxp OS: imx-yocto-L4.14.98_2.0.0_ga Camera: max9286 deserializer <=> max96705 serializer  + ar0144 or: max9286 deserializer <=> max96705 serializer + ov9284 Note that currently only one camera is support and the serializer should be connected to the IN0 of max9286. Data format: ar0144: mono raw 12bit. ov9284: mono raw 10bit. On imx8qm/qxp the data will be recieved as raw 16bit and the valid data bit start from bit[13] to LSB. for mono raw 12bit the valid data bit is 0bxxdd_dddd_dddd_ddxx for mono raw 10bit the valid data bit is 0bxxdd_dddd_dddd_xxxx max9286 and max96705 configuration: dbl bws PXL_CRC/edc hven hibw lccen him should be the same on both sides, this can be achieved by pin or register configurations. The crossbar function of max96705 can be used to fix the reversed data bit. for example, reversed 12bit with dbl to 1. 0x20 0xb 0x21 0xa 0x22 0x9 ....... 0x2b 0x0 0x30 0xb 0x31 0xa .... 0x3b 0x0 0x20 to 0x2b and 0x30 to 0x3b are the registers of max96705. Patch apply: 1. push the kernel-patch to the kernel source and apply it. 2. reconfig the kernel setting, make sure there is only CONFIG_MAX9286_AR0144 or        CONFIG_MAX9286_WISSEN(ov9284) enabled, all other max9286 related are disabled. You can run menuconfig to achieve this. 3. For testing copy the vulkan-v4l2.tar to the board, and run vulkan-v4l2.     the source code is at https://github.com/sheeaza/vulkan-v4l2 branch ar0144 for ar0144, branch ov9284 for ov9284. =========== updated patch for data format.

The Android P9.0.0_2.0.0 GA (4.14.98 kernel) is now available on IMX software landing page. Overview -> i.MX BSP Updates and Releases -> Android -> Android P9.0.0_2.0.0 (4.14.98 kernel)    Files available:   # Name Description 1 android_p9.0.0_2.0.0-ga_docs.zip Android P9.0.0_2.0.0 Documentation 2 imx-p9.0.0_2.0.0-ga.tar.gz i.MX Android proprietary surce code for Android P9.0.0_2.0.0 3 android_p9.0.0_2.0.0-ga_image_8mmevk.tar.gz Prebuilt images with NXP extended features for the i.MX 8M Mini EVK 4 android_p9.0.0_2.0.0-ga_image_8mqevk.tar.gz Prebuilt images with NXP extended features for the i.MX 8M Quad EVK 5 android_p9.0.0_2.0.0-ga_image_8qmek.tar.gz Prebuilt images with NXP extended features for the i.MX8QMax and 8QXPlus MEK 6 fsl_aacp_dec_p9.0.0_2.0.0-ga.tar.gz AAC Plus Codec for P9.0.0_2.0.0_GA   Supported boards: i.MX 8MMini MEK Board i.MX 8MQuad EVK Board i.MX 8QuadMax MEK i.MX 8QuadXPlus MEK   Features and Known issues For features and known issues, please consult the Release Notes in detail.  ======================================================================================= The Android P9.0.0_2.1.0_AUTO GA (4.14.98 kernel) is now available on IMX software landing page. Overview -> i.MX BSP Updates and Releases -> Android AUTO-> Android P9.0.0_2.1.0_AUTO   Files available:   # Name Description 1 android_p9.0.0_2.1.0-auto-ga_docs.zip Android P9.0.0_2.1.0_AUTO  Documentation 2 imx-p9.0.0_2.1.0-auto-ga.tar.gz i.MX Android Automotive proprietary source code for Android P9.0.0_2.1.0_AUTO 3 android_p9.0.0_2.1.0-auto-ga_image_8qmek.tar.gz Prebuilt images with NXP extended features with the EVS function enabled in the Cortex-M4 CPU core for the i.MX 8QuadMax/8QuadXPlus MEK 4 android_p9.0.0_2.1.0-auto-ga_image_8qmek2.tar.gz Prebuilt images with NXP extended features for the i.MX8QMax and 8QXPlus MEK, without the EVS in M4 Core.   Supported boards: i.MX 8QuadMax MEK i.MX 8QuadXPlus MEK   Features and Known issues For features and known issues, please consult the Release Notes in detail.

i.MX8X 板级开发包镜像结构 ...................................... 3 2 创建 i.MX8QXP Linux 5.4.24 板级开发包编译环境 ..... 3 2.1 下载板级开发包 ....................................................... 3 2.2 创建yocto编译环境: ................................................. 5 2.3 独立编译 ............................................................... 10 3 i.MX8X SC firmware ................................................. 16 3.1 SC firmware 目录结构 ........................................... 16 3.2 SC firmware 启动流程 ........................................... 18 3.3 SC firmware定制 ................................................... 18 4 i.MX8X ATF .............................................................. 30 5 FSL Uboot 定制 ........................................................ 32 5.1 FDT支持 ............................................................... 33 5.2 DM(driver model)支持 ........................................... 38 5.3 Uboot目录 结构 ..................................................... 52 5.4 Uboot编译 ............................................................. 54 5.5 Uboot初始化流程 .................................................. 55 5.6 uboot 定制 ............................................................ 66 5.7 uboot debug信息 ................................................... 82

    On latest iMX8QXP MEK board, the hardware connected the SCU_GPIO0_00 and SCU_GPIO0_01 pins for SCU debug UART, and customer can enable "#define ALT_DEBUG_SCU_UART" from "imx-scfw-porting-kit-1.1/src/scfw_export_mx8qx_b0/platform/board/mx8qx_mek/board.c" to open the SCFW debug UART for early board bring up.     And if customer enabled "#define ALT_DEBUG_UART" from board.c, then SCFW will use ADC_IN2 and ADC_IN3 pins for debug UART.     In this document, it is another choice, SCFW can also use UART0_RX and UART0_TX pins as SCU debug UART for early board bring up. It is based on released "imx-scfw-porting-kit-1.1.tar.gz".     That means on early MEK boards and customer boards which haven't reserved debug UART for SCU, they can also check the SCFW boot log from UART0 port. "scfw-porting-kit-1.1-sc_uart-on-uart0.patch" is the reference patch for such modification. Enable "#define ALT_DEBUG_SCU_UART_ON_UART0" to make it work. Note: since UART0 pins had been used in SCFW, they can't be used in UBoot and linux kernel at the same time, so when debuging UBoot and Linux kernel, you need disable "ALT_DEBUG_SCU_UART_ON_UART0" in SCFW, or you can use other UART port and pins.

In defaut Linux BSP, NXP implemented LVDS to HDMI(it6263) and MIPI-DSI to HDMI(adv7535) bridge chip drivers. And these drivers need read the EDID from display, then apply the timing parameters to DRM driver. But for the use case that bridge chip -> Serializer -> Deserializer -> LCD Panel use case, there is no EDID. The attached are reference patches for such use case, it combined the bridge chip to panel directly, and no EDID is needed. The patches are tested on iMX8QXP MEK with bridge chip + panel mode, both of them can see the fb0 device under /sys/class/graphics/ folder, also can see card under  /sys/class/drm/. Display works fine with DTS selected 720P panel mode. [2020-06-24]: Add patches for L4.14.98 kernel: Android_Auto_P9.0.0_GA2.1.0_Kernel_No_EDID_IT6263.patch L4.14.98-iMX8QXP-MEK-ADV7535-MIPI-DSI-to-HDMI-bridge-chip-com.patch

Hello everyone, We have recently migrated our Source code from CAF (Codeaurora) to Github, so i.MX NXP old recipes/manifest that point to Codeaurora eventually will be modified so it points correctly to Github to avoid any issues while fetching using Yocto. Also, all repo init commands for old releases should be changed from: $ repo init -u https://source.codeaurora.org/external/imx/imx-manifest -b <branch name> [ -m <release manifest>] To: $ repo init -u https://github.com/nxp-imx/imx-manifest -b <branch name> [ -m <release manifest>] This will also apply to all source code that was stored in Codeaurora, the new repository for all i.MX NXP source code is: https://github.com/nxp-imx For any issues regarding this, please create a community thread and/or a support ticket. Regards, Aldo.

 This article instruct customer how to develop on i.MX8MP NPU and how to debug performance. 

   

  Anyone who want to use this solution should get reference design and firmware from Lontium. Hardware Here is the block diagram of LT9611UXC Demo Board. As the MIPI port of our EVK can provide 5V, 3V3 and 1V8.We can remove useless DC-DC chips from reference design. Below is the LT9611UXC Demo Board. Software Download the firmware into LT9611UXC. In Linux side, we need to drive the MIPI to output signals with standard timings of 1080P. Panel type diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 1732b5c72380..c6a829be541f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -696,13 +716,17 @@ &ldb_phy { &mipi_dsi { status = "okay"; + panel@0{ + compatible = "nxp,lt9611uxc"; + reg = <0>; + status = "okay"; }; }; &snvs_pwrkey { diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 4f78bbf63f33..90d99f12515b 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -4997,6 +4997,34 @@ struct panel_desc_dsi { unsigned int lanes; }; +static const struct drm_display_mode lt9611_panel_mode = { + .clock = 148500, + .hdisplay = 1920, + .hsync_start = 1920 + 88, + .hsync_end = 1920 + 88 + 44, + .htotal = 1920 + 88 + 44 + 148, + .vdisplay = 1080, + .vsync_start = 1080 + 4, + .vsync_end = 1080 + 4 + 5, + .vtotal = 1080 + 4 + 5 + 36, +}; + +static const struct panel_desc_dsi lt9611_panel = { + .desc = { + .modes = &lt9611_panel_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 62, + .height = 110, + }, + .connector_type = DRM_MODE_CONNECTOR_DSI, + }, + .flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_VIDEO_SYNC_PULSE, + .format = MIPI_DSI_FMT_RGB888, + .lanes = 4, +}; + static const struct drm_display_mode auo_b080uan01_mode = { .clock = 154500, .hdisplay = 1200, @@ -5201,6 +5229,9 @@ static const struct panel_desc_dsi osd101t2045_53ts = { static const struct of_device_id dsi_of_match[] = { { + .compatible = "nxp,lt9611uxc", + .data = &lt9611_panel, + },{ .compatible = "auo,b080uan01", .data = &auo_b080uan01 }, {