QTool is a PC software tool that works with QN9080 USB dongle to assist in the development of BLE projects with the QN9080. You control the dongle via the QTool software, which issues and receives FSCI (Framework Serial Communication Interface) formatted commands over a virtual COM port. The dongle can then act either as a master or a slave to a QN9080DK board over BLE.  Before using the BLE dongle with QTool though, the firmware on the QN9080 Dongle must be updated. The updated firmware can be found inside the QTool installation directory, and you will need to put the dongle into bootloader mode to drag-and-drop new firmware on it. Updating the Firmware on the QN9080 Dongle. 1. Install QTool: https://www.nxp.com/webapp/sps/download/license.jsp?colCode=Connectivity-QTool-Setup   2. Plug the QN9080 Dongle into a USB port on your computer 3. Using a wire, connect TP5 to ground. You can use either TP4 or the USB shield for GND. 4. While that wire is connected, press the reset button on the dongle. This will now put the dongle into bootloader mode. 5. A drive will enumerate on your computer named “CRP_DISABLD”     6. You can now remove the wire 7. Delete the firmware.bin file found in that drive 8. Drag-and-drop the firmware.bin file found in C:\NXP\Connectivity QTool\bin files into that enumerated drive. 9. Once done copying, unplug and replug in the USB Dongle, and the new firmware will now be running.  Installing the QN9080 Dongle Driver The dongle will enumerate as a USB CDC COM device. If the CDC driver is not automatically detected, you will need to manually install the driver. 1. Right-click Computer and choose Properties, the System Management window appears. 2. Click Device Manager and navigate to MCU VIRTUAL COM DEMO      3. Right-click the device MCU VIRTUAL COM DEMO and choose Update Driver Software 4. Click the  Browse my computer for driver software option in the window. 5. Click Browse button to go to the folder  C:\NXP\Connectivity QTool\drivers 6. Click the Next button at the bottom to install the driver.  7. After the driver is installed you will see the Virtual Com Port device under the Ports category    Using QTool: Now that the QN9080 dongle has the updated firmware and has the correct driver installed, you can follow the instructions in the QTool documentation found at C:\NXP\Connectivity QTool\UM11085.pdf Related documentation: QN908x Quick Start Guide QN908x DK User's Guide

FRDM-KW36 Software Development Kit (SDK) includes drivers and examples of FlexCAN module for KW36 which can be easily configured for a custom communication. For example, if user want to change the default baud rate from FlexCAN driver demo examples then the only needed change is the default value on "config->baudRate" and "config->baudRateFD" from "FLEXCAN_GetDefaultConfig" function (See Figure 1). Segments within a bit time will be automatically configured to obtain the desired baud rate. By default, demos are configured to work with CAN FD communication. Figure 1. FRDM-KW36's default baudrate from flexcan_interrupt_transfer driver example Even so, there are cases where segments within a bit time are not well configured and it's necessary that user configure segments manually. An example occurs by setting the maximum FD baud rate "3.2MHz" using the 32MHz xtal or "2.6MHz" using a 26MHz xtal where demo reports an error. See Figure 2. Figure 2. Error by setting maximum baud rate When this error occurs, the fix is on setting the timing config parameters correctly by including the definition of SET_CAN_QUANTUM on application source file (see Figure 3) and then declare and initialize the timing config parameters shown in Figure 4. Figure 3. SET_CAN_QUANTUM define Figure 4. Custom timing config parameters For this example we are going to show how to calculate timing config parameters in an scenario where a CAN FD communication is used with baud rate of 500kHz on nominal phase and 3.2MHz on FD phase. See Figure 5.  To do it, we need to calculate Time Quanta and value of segments within the bit time.    Figure 5. Custom CAN FD baudrate KW36 Reference Manual in chapter "37.4.8.7 Protocol timing" shows the segments within a bit time for CAN nominal phase configured in "CAN_CTRL1" register (see Figure 6), and segments for FD phase configured in CAN_FDCBT register (see Figure 7). Figure 6. Segment within a bit time for CAN nominal phase Figure 7. Segment within a bit time for CAN FD phase Before calculating the value of segments, first we need to calculate the Time Quanta which is the atomic number of time handled by the CAN engine. The formula to calculate Time Quanta is shown in Figure 8 taken from KW36 Reference Manual. Figure 8. Time Quanta Formula CANCLK can be selected by CLKSRC bits on CAN_CTRL1 register as shown in Figure 9, where the options are Peripheral clock=20MHz or Oscillator clock (16MHz if using 32MHz xtal or 13MHz if using 26MHz xtal). The recomiendation is to use the Oscillator clock due to peripheral clock can have jitter that affect communication.  Figure 9. CAN clocks To select the Oscillator clock, search for flexcanConfig.clkSrc definition and set it to kFLEXCAN_ClkSrcOsc as shown in Figure 10. Figure 10. CANCLK selection Next step is selecting the PRESDIV value for nominal phase and FPRESDIV for FD phase. You have to select the right value to achieve the TQ needed to obtain the configured baudrate. For this example, let's set FPRESDIV value to 0 and PRESDIV value to 3. TQ calculation for nominal phase: TQ = (PRESDIV + 1) / CANCLK = (3 + 1) / 16000000 = 0.00000025 TQ calculation for FD phase: TQ = (FPRESDIV + 1) / CANCLK = (0 + 1) / 16000000 = 0.0000000625 The bit rate, which defines the rate of CAN message is given by formula shown in Figure 11 taken from KW36 Reference Manual. Figure 11. CAN Bit Time and Bit Rate Formulas With this info and with our TQ calculated, we can deduce that we need: For Nominal phase: 8 = Number of Time Quanta in 1 bit time For FD phase: 5 = Number of Time Quanta in 1 bit time Now, let's define the value of segments. For nominal phase: Bit Time =  (number of Tq in 1 bit time) x Tq CAN Bit Time = (1 + (PROPSEG + PSEG1 + 2) + (PSEG2 + 1) ) x Tq CAN Bit Time = (1 + (1 + 2  + 2) + (1 + 1) ) x Tq = 8 x 0.00000025 =  Baud rate = 1/ CAN Bit Time = 500KHz For FD phase: CAN Bit Time = (number of Tq in 1 bit time) x Tq CAN Bit Time = (1 + (FPROPSEG + FPSEG1 + 1) + (FPSEG2 + 1) ) x Tq CAN Bit Time = (1 + (0 + 1 + 1) + (1 + 1) ) x Tq = 5 x Tq =  0.0000003125 Bit Rate = 1/CAN Bit Time = 1 / 0.0000003125 =  3.2MHz To finish, just update the calculated values on your firmware on flexcanConfig.timingConfig structure.  Notes: FRDM-KW36 Software Development Kit (SDK) can be downloaded from MCUXpresso webpage. FlexCAN driver examples are located in path: "SDK_2.2.0_FRDM-KW36\boards\frdmkw36\driver_examples" from your downloaded FRDM-KW36 SDK. Take in consideration that not all the baud rates are achievables and will depend on the flexcan clock and segment values used.

Introduction When a software update is requested by an OTAP Client (a device that receives a software update, commonly Bluetooth LE Peripheral) from the OTAP Server (a device that sends a software update, commonly Bluetooth LE Central), you may want to preserve some data previously acquired, such as bonding information, trimming values for the system oscillators, or probably NVM data for your application. This document guides you in performing OTAP updates preserving the flash data content of your interest. This document is intended for developers familiarized with OTAP custom Bluetooth LE service, for more information, you can take a look at the following post: Reprogramming a KW36 device using the OTAP Client Software.   OTAP Header and Sub-elements OTAP Protocol implements a format for the software update that is composed of a header and a defined number of sub-elements. The OTAP Header describes general information about the software update and it has a defined format shown in the following figure. For more information about the header fields, you can go to 11.4.1 Bluetooth Low Energy OTAP header chapter of the Bluetooth Low Energy Application Developer's Guide document included in the SDK at <SDK_2.2.X_FRDM-KW36_Download_Path>\docs\wireless\Bluetooth                              Each Sub-element contains information for a specific purpose. You could implement your proprietary fields for your application (For more information about sub-element fields, you can go to 11.4.1 Bluetooth Low Energy OTAP header chapter of the Bluetooth Low Energy Application Developer's Guide document included in the SDK at <SDK_2.2.X_FRDM-KW36_Download_Path>\docs\wireless\Bluetooth). OTAP includes the following sub-elements: Image File Sub-element Value Field Lenght (bytes) Description Upgrade Image  Variable This sub-element contains the actual binary executable image which is copied into the flash memory of the OTAP Client device. The maximum size of this sub-element depends on the target hardware. Sector Bitmap 32 This sub-element contains a sector bitmap of the flash memory of the target device which tells the bootloader which sectors should be overwritten and which leave intact. The format of this field is the least-significant bit first for each byte with the least significant bytes and bits standing for the lowest memory sections of the flash.  Image File CRC 2 This is a 16-bit CRC calculated over all elements of the image file except this field itself. This element must be the last sub-element in an image file sent over the air.   OTAP Sector Bitmap Sub-element Field The KW36 Flash is partitioned into: One 256 KB Program Flash (P-Flash) array divided into 2 KB sectors with a flash address range from 0x0000_0000 to 0x0003_FFFF. One 256 KB FlexNVM array divided in 2 KB sectors, flash address ranges from 0x1000_0000 to 0x1003_FFFF with an Alias memory with address range 0x0004_0000 to 0x0007_FFFF. The Bitmap sub-element is 256 bits of length, in terms of the KW36 flash, each bit represents a 2KB sector covering the address range from 0x0 - 0x0007_FFFF (P-Flash to FlexNVM Alias address range), where 1 means that such sector should be erased and 0 means that such sector should be preserved. The Bitmap field is used by the OTAP Bootloader to obtain the address range which should be erased before programming the KW36 with the software update, so it must be configured before sending a software update to leave intact the address range of memory that contain data of your interest and erase only the address range that will be overwritten by the software update.        For example: Suppose that a developer wants to preserve the address range between 0x7D800 - 0x7FFFF and the address range between 0x0 - 0x1FFF, and the left memory must be erased. The address range between 0x7D800 - 0x7FFFF corresponds to the 5 top flash sectors and the address range between 0x0 - 0x1FFF is the lowest 4 sectors. So, it means that bits between 256 and 252 (256, 255, 254, 253 and 252) and bits between 4 and 1 (4,3,2 and 1) should be set to 0, that way OTAP Bitmap for this example is: 0x07FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0   Configuring OTAP Bitmap to Protect an Address Range with NXP Test Tool Download and install Test Tool for Connectivity products in NXP's web site Open NXP Test Tool 12 software on your PC. Go to "OTA Updates -> OTAP Bluetooth LE" Then load your image file for the software update clicking on the "Browse..." button (NXP Test Tool only accepts .bin and .srec files). You can configure the OTAP Bitmap selecting the "Override sector bitmap" checkbox and changing the default value by your new bitmap value. Once you have configured the bitmap, select "Save...".   Then, a window will be displayed to select the destination to save the .bleota file. Provide a name to identify this file. You can use this file with IoT Toolbox App for Android and iOS to update the software using OTAP. This new .bleota file contains the bitmap that tells to the OTAP Bootloader which sectors will be erased and which sectors will be preserved.          

This document takes i.MXRT 1060 evkc and iw610 M.2 module as example to share how to setup manufactory mode in i.MXRT platform for NXP wifi product.  Hardware Host platform: i.MXRT 1060 evkc Wi-Fi chip: iw610 M.2 evk Software RT1060EVKC SDK 25.12.00 MFG TOOL: MFG-SD-IW610-MF-LABTOOL-Native-BRG-WIN-X86-2.0.0.39.0-18.80.5.p77

To generate a hello world (suppose) example for KW47-EVK for IAR toolchain. We asume that IAR toolchain is already installed. Set IAR_DIR environment variable. In Windows, this can be done via Edit environment variables system option. Example: IAR_DIR=C:\iar\ewarm-9.60.1.    Note: IAR toolchain version may change. Type the following commands on your MCUXSDK workspace: cd mcuxsdk west build -b kw47evk ./examples/demos_apps/hello_world --toolchain=iar -t standalone_project -Dcore_id=cm33_core0 --pristine -d ./build/kw47evk/kw47evk_standalone_hello_world_iar​ IAR project should have been generated on  MCUXSDK_WS/mcuxsdk/build/kw47evk/kw47evk_standalone_hello_world_iar/iar directory. IAR project has .eww file extension.     Relevant links IDE Project Generation: https://mcuxpresso.nxp.com/mcuxsdk/latest/html/develop/build_system/IDE_Project.html# Note: Ruby is required for this feature. Typically, this tool is installed via MCUXpresso Installer. However, if having issues with this tool refer to the next link: Ruby Environment Setup: https://mcuxpresso.nxp.com/mcuxsdk/latest/html/develop/build_system/IDE_Project.html#ruby-environment-setup Suppose you want to generate a hello world example for KW47-EVK for IAR toolchain as the previous example, but this time LPTMR driver is required for low-power timer operating purposes. We asume that IAR toolchain is already installed and IAR_DIR variable is already set. The easiest way to accomplish this is to add the lptmr Kconfig symbols with ‘yes’ value at Board-Application level (Refer to Kconfig User Guide). In this case, the target prj.conf file is located on  MCUXSDK_WS/mcuxsdk/examples/_boards/kw47evk/demo_apps/hello_world.​ Edit this file and add the LPTMR required symbols:  CONFIG_MCUX_COMPONENT_driver.lptmr=y CONFIG_MCUX_COMPONENT_component.lptmr_adapter=y​       Type the following command on your MCUXSDK workspace:  west build -b kw47evk ./examples/demo_apps/hello_world --toolchain=iar -t standalone_project -Dcore_id=cm33_core0 --pristine -d ./build/kw47evk/kw47evk_standalone_hello_world_iar IAR project should have been generated on MCUXSDK_WS/mcuxsdk/build/kw47evk/kw47evk_standalone_hello_world_iar/iar directory. IAR project has .eww file extension. This time LPTMR drivers should be included in iar/drivers/lptmr          

When performing Bluetooth LE RF testing on KW47 and MCXW72 devices, it may be necessary to configure the transmitter output power through a vendor-specific HCI command. NXP's Test Tool provides a convenient way to send HCI commands during Direct Test Mode (DTM) validation and characterization. Although the Test Tool is still commonly referenced in documentation and application workflows, it is no longer actively maintained. As a result, the default HCI command XML definitions included with the tool do not correctly support the vendor-specific Tx power command required by KW47 and MCXW72 devices. The default Test Tool XML does not correctly define the vendor-specific HCI_VENDOR_CONFIG_TX_POWER command for KW47 and MCXW72 devices. As a result, the command is not available in the GUI. Edit BLE HCI 5.0 1.6.1.xml (typically located in C:\nxp\Test Tool 12.9.2.2\Xml) and replace the command definition with the XML snippet provided in this article. Alternatively, replace the original XML file with the updated file attached to this article. <Vendor_Commands> <GroupDesc>Vendor_Commands</GroupDesc> <Cmd> <CmdName>HCI_VENDOR_CONFIG_TX_POWER</CmdName> <CmdDesc>HCI_VENDOR_CONFIG_TX_POWER Desc. OgB: FD OcB: 2D </CmdDesc> <CmdSync>01</CmdSync> <CmdHeader>3F 012D</CmdHeader> <CmdParms> <Parm> <ParmName>tx_power</ParmName> <ParmDesc>tx_power Desc</ParmDesc> <ParmSize>1</ParmSize> <ParmType>tInt</ParmType> <ParmLastValue>00</ParmLastValue> <ParmDefaultValue>00</ParmDefaultValue> </Parm> <Parm> <ParmName>Channel</ParmName> <ParmDesc>type Desc</ParmDesc> <ParmSize>1</ParmSize> <ParmType>tInt</ParmType> <ParmLastValue>00</ParmLastValue> <ParmDefaultValue>00</ParmDefaultValue> </Parm> <Parm> <ParmName>NotUsed</ParmName> <ParmDesc>Not Used</ParmDesc> <ParmSize>2</ParmSize> <ParmType>tInt</ParmType> <ParmLastValue>00</ParmLastValue> <ParmDefaultValue>00</ParmDefaultValue> </Parm> </CmdParms> </Cmd> </Vendor_Commands>​ After updating the XML file and restarting Test Tool, HCI_VENDOR_CONFIG_TX_POWER should appear in the GUI. HCI_VENDOR_CONFIG_TX_POWER command parameters: tx_power[1]: Supported values are 0x00 (0 dBm), 0x07 (7 dBm), and 0x0A (10 dBm). Channel[1]: Supported values are 0x00 (applies to advertising channels) and 0x01 (applies to non-advertising channels). NotUsed[2]: Reserved parameter. Always set this field to 0x0000.

The clock tolerance for CAN FD at high baud rates is generally considered to be tight compared to lower baud rates, meaning that the clock frequency needs to be very precise to ensure reliable communication; this is due to the high data rate requiring precise bit timing. CAN generally requires crystal or PLL clock source due to accuracy requirements, on KW45/7 that is limited to 32 MHz crystal (SOSC) since there is no PLL available. However, the FRO192 (FIRC) can be fine trimmed to the SOSC crystal as reference, in a closed loop configuration. When operating in closed loop the FRO192 accuracy is +/-0.25%. The FRO192 when operating in open loop (default) will not be accurate enough for CAN-FD (+/-3%). Closed loop operation is enabled while SCG0→FIRCCSR[FIRCTRUP] = 1 and SCG0→FIRCCSR[FIRCTREN] =1. The auto trim continues as long as those bits are set (for example if change in temperature causes the FRO192clock frequency to drift). Once locked, only the fine trim bits would be updated on subsequent corrections. Refer to code snippet below for correct clock configuration: #include "clock_config.h" #include "fsl_clock.h" const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN = { .freq = 32000000U, /* System Oscillator frequency: 32000000Hz */ .monitorMode = kSCG_SysOscMonitorDisable, /* System OSC Clock Monitor is disabled */ .enableMode = kSCG_SoscEnable, /* System OSC Enable */ }; const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN = { .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */ .divBus = (uint32_t)kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */ .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */ .src=(uint32_t)kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */ }; static const scg_firc_trim_config_t FircTrimConfig_BOARD_BootClockRUN = { .trimMode = kSCG_FircTrimUpdate, /* FIRC trim is enabled and trim value update is enabled */ .trimsrc=kSCG_FircTrimSrcSysOsc, /* Trim source is System OSC */ .trimDiv = 31U, /* Divided by 32 */ .trimCoar = 0U, /* Trim value, see Reference Manual for more information */ .trimFine = 0U, /* Trim value, see Reference Manual for more information */ }; const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN = { .enableMode = kSCG_FircEnable, /* Fast IRC is enabled */ .range = kSCG_FircRange96M, /* 96 Mhz FIRC clock selected */ .trimConfig = &FircTrimConfig_BOARD_BootClockRUN, }; /* Unlock FIRC and SOSC control status registers */ CLOCK_UnlockFircControlStatusReg(); CLOCK_UnlockSysOscControlStatusReg(); /* Init FIRC */ CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN); /* Set SCG to FIRC mode */ CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN); /* Wait for clock source switch finished */ do { CLOCK_GetCurSysClkConfig(&curConfig); } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src); /* Initializes SOSC according to board configuration */ (void)CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN); /* Set the XTAL0 frequency based on board settings */ CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq); /* For 6 mbps baud rate requires FRO192M as FlexCAN source clock */ CLOCK_SetIpSrc(kCLOCK_Can0, kCLOCK_IpSrcFro192M); CLOCK_SetIpSrcDiv(kCLOCK_Can0, kSCG_SysClkDivBy1); The maximum supported baud rate for KW47 and MCXW72 devices is 6 Mbps. Although higher rates may be achievable on some SoCs, 6 Mbps is the highest baud rate supported by the device clock specifications.  For simplicity, the FlexCAN driver APIs can be used to configure the CAN FD baud rate, as shown in the following code snippet: #include "fsl_flexcan.h" #define EXAMPLE_CAN CAN0 #define USE_CANFD (1) #define RX_MESSAGE_BUFFER_NUM (0) #define TX_MESSAGE_BUFFER_NUM (1) #define BYTES_IN_MB kFLEXCAN_64BperMB /* For 6 Mbps use case. FRO192 must be selected as clock source */ #define EXAMPLE_CAN_CLK_FREQ CLOCK_GetFreq(kCLOCK_ScgFircClk) #define USE_IMPROVED_TIMING_CONFIG (1) flexcan_config_t flexcanConfig; /* Get FlexCAN module default Configuration. */ /* * flexcanConfig.clksrc=kFLEXCAN_ClkSrc0; * flexcanConfig.bitRate = 1000000U; * flexcanConfig.bitRateFD = 2000000U; * flexcanConfig.maxMbNum = 16; * flexcanConfig.enableLoopBack = false; * flexcanConfig.enableSelfWakeup = false; * flexcanConfig.enableIndividMask = false; * flexcanConfig.disableSelfReception = false; * flexcanConfig.enableListenOnlyMode = false; * flexcanConfig.enableDoze = false; */ FLEXCAN_GetDefaultConfig(&flexcanConfig); /* Manually override default CAN FD config to 1 Mbps for nominal rate and 6 Mbps for data rate */ flexcanConfig.bitRate = 1000000U; flexcanConfig.bitRateFD = 6000000U; #if (defined(USE_IMPROVED_TIMING_CONFIG) && USE_IMPROVED_TIMING_CONFIG) flexcan_timing_config_t timing_config; memset(&timing_config, 0, sizeof(flexcan_timing_config_t)); if (FLEXCAN_FDCalculateImprovedTimingValues(EXAMPLE_CAN, flexcanConfig.bitRate, flexcanConfig.bitRateFD, EXAMPLE_CAN_CLK_FREQ, &timing_config)) { /* Update the improved timing configuration*/ memcpy(&(flexcanConfig.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); } #endif FLEXCAN_FDInit(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ, BYTES_IN_MB, true);    

This post provides guidance on how to update the NBU firmware on MCX W72 and KW47 devices through several methods: Bootloader Host Application (blhost), Secure Provisioning Tool, LinkServer. The Narrow Band Unit (NBU) is a dedicated compute subsystem for the Narrowband Radio, present in select NXP wireless microcontrollers. It is comprised of an Arm® Cortex®-M33 and associated peripherals that, in conjunction with the Bluetooth Unit, support the Bluetooth LE protocol. Running at 96 MHz alongside a 2.4 GHz transceiver, the NBU operates independently from the main application core, offloading all radio processing from the primary CPU and freeing it for application tasks. While the NBU allows for flexibility for evolving requirements, firmware to implement radio protocols is intended to be developed and delivered by NXP. Note: It is important that the NBU firmware version matches the SDK version of the application. After downloading the SDK and before running any wireless examples, update the NBU firmware using the binaries provided in the SDK folder. The NBU binary file is located in the SDK folder. Go to the SDK root folder and open the path: path_to_SDK\mcuxsdk\middleware\wireless\ble_controller\bin   Prerequisites To follow this guide, the following environment is required: Software Setup Bootloader Host Application (blhost). Download here. MCUXpresso Secure Provisioning Tool. Download here. LinkServer for Microcontrollers. Download here. Hardware Setup Development boards associated with the MCX W72 or KW47 microcontroller families may be used. The ISP button varies by board and is referred to as ISP_button  throughout this guide: Development board ISP_button FRDM-MCXW72 SW3 MCXW72-LOC SW4 KW47-EVK SW4 KW47-LOC SW4   To set the board to the Bootloader ISP mode, press and hold the ISP_button , connect the development board via the MCU-Link connector to the PC, then release ISP_button .   Bootloader Host Application (blhost) Place the board in ISP mode by pressing and holding ISP_button . Connect the USB cable to the MCU-Link connector and release ISP_button after the connection is established. Verify the COM port assigned to the board by opening Device Manager in Windows and searching for Ports (COM & LPT). Identify and note the corresponding COM port number. Open a command prompt and change the directory to the location of the blhost.exe file: (BLHost_root_location)\blhost_2.6.7\bin\win Verify communication by running the following command, making sure to replace COMX with the COM port assigned to your device: blhost.exe -p COMX get-property 1 Update the NBU firmware image. First, erase the NBU memory: blhost.exe -p COMX flash-erase-all 2 Write the new firmware image using the following command. The write-memory command uses 0x48800000 as the start address, which corresponds to the NBU memory base. Provide the full path to the binary file, or alternatively, copy the .bin file into the same directory as blhost.exe to simplify the command: blhost.exe -p COMX write-memory 0x48800000 <nbu_binary>.bin   MCUXpresso Secure Provisioning Tool Create a workspace for the device. To use the keys same as the development board, select the processor relevant to the FRDM/EVK board. Place the board in ISP mode by pressing and holding ISP_button . Connect the USB cable to the MCU-Link connector and release ISP_button after the connection is established. To verify communication, click the UART tab, refresh the Port field selection and select the assigned COM Port identified. Click Test connection and confirm that the result displays OK. In the toolbar, select the boot type as Plain unsigned or Plain with CRC. In the Build Image view, load the binary file in Source executable image, enter the start address as  0x48800000  (which corresponds to the NBU memory base), and click Build image. Navigate to the Write Image view, select Use built image, and click Write image. A success message appears when the NBU firmware loading is complete.   LinkFlash Tool For this method, a LinkServer debug probe must be available on the board. The steps on how to install the CMSIS-DAP/SEGGER J-link firmware are available here. Navigate to the main LinkServer folder in your computer and execute the  LinkFlash.exe  file. Place the board in ISP mode by pressing and holding ISP_button . Connect the USB cable to the MCU-Link connector and release ISP_button after the connection is established. In the LinkFlash tool, after the device is connected, click the Refresh button to update and set the probe target of the board. Go to the Program tab, click Browse, select the NBU firmware file, and enter the start address  0x48800000 . Ensure to check the boxes Mass erase before programming and Reset target after programming. To load the NBU firmware, click Program.  

What is NAN? Neighbor Awareness Networking (NAN), also known as Wi-Fi Aware, is a mechanism defined by the Wi-Fi Alliance. NAN is an additional Wi-Fi interface to micro-AP (uAP), Station (STA), and Wi-Fi direct (wfd) that allows for quick discovery without the connection-association flow. The interface named: nan0.In this demo test, NAN is used to Wi-Fi locate and/or range. NXP Wi-Fi Products Supports NAN: Currently we have our IW612, IW611,AW611 and AW693 support NAN feature on Linux OS, and the remote devices should also be Linux OS or Android OS. Currently we do not support for remote device which running iOS. Below is the Release Notes showing which product in our NXP supports NAN feature. https://github.com/nxp-imx/mwifiex/blob/doc_WCT_release/doc/Release_Notes/Linux_RN/topics/wi_fi_radio.md Caution: There is typo in above release note. Actually IW610 doesn't support NAN feature. Demo setup: In this doc, the test is based on 2 IW612 module: Murata 2EL M.2 module on I.MX93-EVK which is running Linux OS, the Linux kernel is L6.12.49. IW612's driver and FW version is: SDIW612---18.99.8.p3--MM6X18542.p8-(FP92), and the nanapp in this release could not outout wls message, official working nanapp will be in next release, available in the end of March/2026. wifi_mod_para.conf SDIW612 = { cfg80211_wext=0xf max_vir_bss=1 cal_data_cfg=none ps_mode=2 auto_ds=2 host_mlme=1 drv_mode=0x17 fw_name=nxp/sduart_nw61x_v1.bin.se } Copy correct version's nanapp and mlanutl and mlanwls to 2 boards, and add execute permission. root@imx93evk:~# chmod +x nanapp root@imx93evk:~# chmod +x mlanutl root@imx93evk:~# chmod +x mlanwls Copy correct FWand driver: mlan.ko + moal.ko(Cross compiled with L6.12.49 linux kernel BSP, not included in this doc). After the I.MX93-EVK board boot up, need to unload the default L6.12.49's Wi-Fi driver, then load the newer L6.18.2 Wi-Fi driver and FW. The whole process is shown as follow: The generated wls_leader.log and wls_follower.log files contain location information. The Wireshark sniffer contains NAN-related packets. Please see attached .pdf file for more detailed steps and logs outputs.   How to configure to use Wireshark capture Sniffer logs On Ubuntu PC 24.04.2 LTS? Below is the commands for your reference. sudo iw dev //Check your Wi-Fi card name. Here is:wlp111s0 for me. sudo ifconfig wlp111s0 down sudo systemctl stop NetworkManager sudo killall wpa_supplicant //Here need to stop NetworkManager and wpa_supplicant, otherwise, after we configure wlp111s0 into monitor mode, these 2 service will automatically change it to managed mode. sudo iwconfig wlp111s0 mode monitor //set wlp111s0 into monitor mode sudo iwconfig //check whether set into monitor mode successfully. Here should show Mode:monitor sudo wireshark //Need to use sudo permission to run Wireshark, otherwise, could not use Wireshark to capture sniffer. Then choose wlp111s0 to capture sniffer. Reference link: Neighbor Awareness Networking (NAN) -Application note (confidential) https://github.com/nxp-imx/mwifiex/blob/doc_WCT_release/doc/Release_Notes/Linux_RN/topics/wi_fi_radio.md   Best regards, Christine.

Be aware that it is necessary to work with the matching narrow band unit (NBU) image for the SDK version of the application you are working with. This means that when you download your SDK, prior to loading any wireless SDK example, update your NBU image with the provided binaries in the following folder of the SDK: ../middleware/wireless/ble-controller/bin   Here you will find the image for the NBU firmware:   To update the NBU, you may use the LinkFlash tool as follow: Open the path to LinkFlash tool. Usually, this path would be: C:\nxp\LinkServer_xx.x.xx ​ Select  KW47B42ZB7xxxA:KW47-EVK  as device, serial wire debug (SWD) as protocol and 0x48800000 as address. Check the 'Mass erase before programming' checkbox. Select ' kw47_nbu_ble_all_hosted.bin ' as image file. Press the 'Program' button and wait for the flash operation to be completed.    

This post provides guidance on how to port the example projects from the NXP NCI 2.0 NFC library to the MCXW71 Wireless MCU using SPI interface to communicate with PN7160 SPI EVK. To follow this guide, please use the following environment: MCUXpresso IDE 25.06.136. FRDM-MCXW71 SDK v25.12.00 (last available for MCUXpresso IDE). FRDM-MCXW71. OM27160B1 (PN7160 SPI EVK). Hardware Setup. The MCXW71 complies with the Arduino header standard as the OM27160B1 board, therefore you can connect directly the shield over the FRDM-MCXW71 as the pin connection match among both, allowing an easy connection between the devices. Take into consideration that this setup forces us to use the LPSPI1 instance of the MCXW71, it is possible to use another instance, but we would not be able to connect the boards directly, rather we would need to do the connections with jumpers.   Downloading base projects and adapting for MCXW71 port. To start with the porting work, download the NXP-NCI example project from this page. This compressed file contains the base project for different boards that will allow us to do the required modifications to add support for the MCXW71. Once downloaded, extract the SW6705 file into a known path (e.g. the Downloads folder) to later import the project to the IDE. The extracted folder should contain a .zip file with the examples that we will later import to the IDE. Download the FRDM-MCXW71's SDK from the SDK Builder page, make sure to select the 25.12.00 version, as it is the latest SDK available to use along the MCUXpresso IDE. Now we have to import the NXP-NCI2.0_MCUXpresso_examples.zip file we previously extracted to the IDE's workspace, to do so, click on the Import project(s) from file system and in the Project archive (zip) tab, browse for the extracted file of step 1 (NXP-NCI2.0_MCUXpresso_examples.zip) and click on Next >. NOTE: Don’t worry if the IDE shows an error message for not having the SDKs of the default boards (iMXRT1170, LPC55S6x, LPC82x) or having a different version, close the warning message, we only need these examples to copy the NCI library and example files. Your workspace should now look like the following image: Import the hello_world example from the FRDM-MCXW71 SDK: Add the SPI drivers to the imported project by right clicking over the project, hover the cursor over the SDK Management option and select the option Manage SDK Components: Select the driver, click Ok and if you are asked to refresh files accept it, after this you should be able to see the driver in the "drivers" folder of the project. Copy the contents of the source folder of the iMXRT1170 project, as well as the NfcLibrary folder and paste them into the imported hello_world project:   Make sure to delete the hello_world.c and hello_word.mex files as we won't need it again. After this process your project should look like the following image: To avoid compiling issues, exclude from the build the files nfc_example_P2P.c and nfc_example_RW.c, to do so right click on the file, go to Resource Configurations and select Exclude from Build… and select for all configurations. Do this for each file. Add the preprocessor macro: BOARD_NXPNCI_INTERFACE_SPI, as this is used by the example to select the interface with the board. To do this, right-click on the project and select Properties, then drop-down the C/C++ Build option and go to the Settings tab. Here, add the macro in the Preprocessor option, click on Apply and accept the index rebuild. Add the root folder in C/C++ General > Paths and Symbols > Source Location tab, click on Ok and then Apply: Still in Paths and Symbols, go to the Includes tab and add the source, TML and tool folders from workspace, click Ok and Apply. Make sure to add them one by one. Now, go to C/C++ Build > Settings > Includes and add the following folders from Workspace. You can select all of them and add them at the same time or also do it one by one. Once done, click on Apply and Apply and Close. If you are asked to rebuild the index, do it. "${workspace_loc:/${ProjName}/source/TML}" "${workspace_loc:/${ProjName}/source/tool}" "${workspace_loc:/${ProjName}/NfcLibrary}" "${workspace_loc:/${ProjName}/NfcLibrary/inc}" "${workspace_loc:/${ProjName}/NfcLibrary/NdefLibrary}" "${workspace_loc:/${ProjName}/NfcLibrary/NdefLibrary/inc}" "${workspace_loc:/${ProjName}/NfcLibrary/NdefLibrary/src}" "${workspace_loc:/${ProjName}/NfcLibrary/NxpNci20}" "${workspace_loc:/${ProjName}/NfcLibrary/NxpNci20/inc}" "${workspace_loc:/${ProjName}/NfcLibrary/NxpNci20/src}" Source Code Changes. In the board folder, open the board.h file and add the following definitions to refer to the peripherals and clocks to be used. Please notice that you may change the LPSPI instance, however you would need to connect jumpers instead of connecting directly the shield over the FRDM. #ifdef BOARD_NXPNCI_INTERFACE_SPI #define BOARD_NXPNCI_SPI_CLOCK (CLOCK_GetIpFreq(kCLOCK_Lpspi1)) #define BOARD_NXPNCI_SPI_INSTANCE (LPSPI1) #define BOARD_NXPNCI_SPI_BAUDRATE (400000) #endif #define BOARD_NXPNCI_IRQ_PORT (GPIOC) // J2.10 - GPIO0 [PN7160] - IRQ -> J2.10 GPIOC0 [MCXW71] #define BOARD_NXPNCI_VEN_PORT (GPIOA) // J4.1 - GPIO1 [PN7160] - VEN -> J1.8 GPIOA21 [MCXW71] #define BOARD_NXPNCI_DWL_PORT (GPIOA) // J4.2 - GPIO2 [PN7160] - REQ -> J1.7 GPIOA20 [MCXW71] #define BOARD_NXPNCI_IRQ_PIN (0U) #define BOARD_NXPNCI_VEN_PIN (21U) #define BOARD_NXPNCI_DWL_PIN (20U) Now we need to add the required clock, peripheral and pin initialization for our board. To do this, go to the hardware_init.c file inside the board folder, and overwrite the BOARD_InitHardware function with the following: void BOARD_InitHardware(void) { BOARD_InitPins(); BOARD_BootClockRUN(); BOARD_InitDebugConsole(); CLOCK_SetIpSrc(kCLOCK_Lpspi1, kCLOCK_IpSrcFro192M); CLOCK_SetIpSrcDiv(kCLOCK_Lpspi1, kSCG_SysClkDivBy16); }   To add the correct pin multiplexing and configuration for our SPI and GPIO pins, go to the pin_mux.c file (also in the board folder) and overwrite the BOARD_InitPins function with the following: void BOARD_InitPins(void) { /* Clock Configuration: Peripheral clocks are enabled; module does not stall low power mode entry */ CLOCK_EnableClock(kCLOCK_GpioA); CLOCK_EnableClock(kCLOCK_GpioC); CLOCK_EnableClock(kCLOCK_PortA); CLOCK_EnableClock(kCLOCK_PortB); CLOCK_EnableClock(kCLOCK_PortC); /*IF SHORTING SH11, SH12, SH13, SH14 needed for LPSPI1*/ const port_pin_config_t portb0_pin46_config = {/* Internal pull-up resistor is enabled */ (uint16_t)kPORT_PullUp, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPSPI0_PCS0 */ (uint16_t)kPORT_MuxAlt2, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTB0 (pin 46) is configured as LPSPI1_PCS0 */ PORT_SetPinConfig(PORTB, 0U, &portb0_pin46_config); const port_pin_config_t portb1_pin47_config = {/* Internal pull-up resistor is enabled */ (uint16_t)kPORT_PullUp, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPSPI0_SIN */ (uint16_t)kPORT_MuxAlt2, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTB1 (pin 47) is configured as LPSPI1_SIN */ PORT_SetPinConfig(PORTB, 1U, &portb1_pin47_config); const port_pin_config_t portb3_pin1_config = {/* Internal pull-up resistor is enabled */ (uint16_t)kPORT_PullUp, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPSPI0_SOUT */ (uint16_t)kPORT_MuxAlt2, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTB3 (pin 1) is configured as LPSPI1_SOUT */ PORT_SetPinConfig(PORTB, 3U, &portb3_pin1_config); const port_pin_config_t portb2_pin48_config = {/* Internal pull-up resistor is enabled */ (uint16_t)kPORT_PullUp, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPSPI0_SCK */ (uint16_t)kPORT_MuxAlt2, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTA19 (pin 14) is configured as LPSPI1_SCK */ PORT_SetPinConfig(PORTB, 2U, &portb2_pin48_config); /*IF SHORTING SH11, SH12, SH13, SH14 needed for LPSPI1*/ const port_pin_config_t irq_pin = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullUp, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as PTC0 */ (uint16_t)kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTC0 (pin 37) is configured as PTC0 */ PORT_SetPinConfig(PORTC, 0U, &irq_pin); const port_pin_config_t ven_pin = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as PTA20 */ (uint16_t)kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTA20 (pin 17) is configured as PTA20 */ PORT_SetPinConfig(PORTA, 20U, &ven_pin); const port_pin_config_t req_pin = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as PTA21 */ (uint16_t)kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTA21 (pin 18) is configured as PTA21 */ PORT_SetPinConfig(PORTA, 21U, &req_pin); const port_pin_config_t portc2_pin39_config = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPUART1_RX */ (uint16_t)kPORT_MuxAlt3, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTC2 (pin 39) is configured as LPUART1_RX */ PORT_SetPinConfig(PORTC, 2U, &portc2_pin39_config); const port_pin_config_t portc3_pin40_config = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPUART1_TX */ (uint16_t)kPORT_MuxAlt3, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTC3 (pin 40) is configured as LPUART1_TX */ PORT_SetPinConfig(PORTC, 3U, &portc3_pin40_config); }   To add the required interfacing APIs specific of our chip, we need to modify the tml.c file from the TML folder, in this file overwrite the functions: INTF_INIT, INTF_WRITE and INTF_READ with the following: static void INTF_INIT(void) { lpspi_master_config_t userConfig; uint32_t srcFreq = 0; /*SPI configuration*/ LPSPI_MasterGetDefaultConfig(&userConfig); userConfig.baudRate = BOARD_NXPNCI_SPI_BAUDRATE; srcFreq = BOARD_NXPNCI_SPI_CLOCK; userConfig.whichPcs = (lpspi_which_pcs_t)kLPSPI_Pcs0; userConfig.pcsActiveHighOrLow = (lpspi_pcs_polarity_config_t)kLPSPI_PcsActiveLow; /*Initialize SPI*/ LPSPI_MasterInit(BOARD_NXPNCI_SPI_INSTANCE, &userConfig, srcFreq); } static status_t INTF_WRITE(uint8_t *pBuff, uint16_t buffLen) { uint8_t temp[1000]; temp[0] = 0x7F; memcpy(temp+1, pBuff, buffLen); masterXfer.txData = temp; masterXfer.rxData = NULL; masterXfer.dataSize = buffLen+1; masterXfer.configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterPcsContinuous | kLPSPI_MasterByteSwap;; return LPSPI_MasterTransferBlocking(BOARD_NXPNCI_SPI_INSTANCE, &masterXfer); } static status_t INTF_READ(uint8_t *pBuff, uint16_t buffLen) { status_t status; uint8_t temp[257]; temp[0] = 0xFF; masterXfer.txData = temp; masterXfer.rxData = temp; masterXfer.dataSize = buffLen+1; masterXfer.configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterPcsContinuous | kLPSPI_MasterByteSwap;; status = LPSPI_MasterTransferBlocking(BOARD_NXPNCI_SPI_INSTANCE, &masterXfer); if(status == kStatus_Success) memcpy(pBuff, temp+1, buffLen); SDK_DelayAtLeastUs(10, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); return status; } #endif   We also need to overwrite the functions: tml_Init, tml_DeInit and tml_Reset to adapt them to use the specific APIs for the GPIOs of our board. static Status tml_Init(void) { gpio_pin_config_t in_config = {kGPIO_DigitalInput, 0}; gpio_pin_config_t out_config = {kGPIO_DigitalOutput, 0}; GPIO_PinInit(BOARD_NXPNCI_IRQ_PORT, BOARD_NXPNCI_IRQ_PIN, &in_config); GPIO_PinInit(BOARD_NXPNCI_VEN_PORT, BOARD_NXPNCI_VEN_PIN, &out_config); GPIO_PinInit(BOARD_NXPNCI_DWL_PORT, BOARD_NXPNCI_DWL_PIN, &out_config); INTF_INIT(); return SUCCESS; } static Status tml_DeInit(void) { GPIO_PortClear(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); return SUCCESS; } static Status tml_Reset(void) { /* Set DWL_REQ low for NCI protocol */ GPIO_PortClear(BOARD_NXPNCI_DWL_PORT, 1U << BOARD_NXPNCI_DWL_PIN); GPIO_PortClear(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); Sleep(10); GPIO_PortSet(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); Sleep(10); return SUCCESS; }   Finally, modify the main file so it uses the APIs to initialize our board clocks and pins: #include <stdio.h> #include <string.h> #include "app.h" #include "board.h" #include "pin_mux.h" #include "fsl_debug_console.h" extern void nfc_example (void); int main(void) { BOARD_InitHardware(); #ifdef BOARD_NXPNCI_INTERFACE_I2C PRINTF("\nRunning the NXP-NCI2.0 example (I2C interface)\n"); #else PRINTF("\nRunning the NXP-NCI2.0 example (SPI interface)\n"); #endif nfc_example(); } Testing the example. At this point we have everything set to build and flash our example with SPI interface, you may proceed to build and debug/flash the example by pressing the blue beetle button: Once the example is flashed, open a serial terminal such as Teraterm with the following settings: Baudrate: 115200. Data: 8 bits. Parity: None. Stop bits: 1 bit. No flow control. While running, the example should output the following logs to the terminal: When a tag is placed near the antenna, the example should print the tag information in the terminal as shown:

This article discusses the different use cases and configuration of the errata "ERR053377: FlexCAN: Message Buffer (MB) and Enhanced RX FIFO Filter Element (ERFFEL) Memory Corruption". The errata is impacting Messabe Buffers (MB) and Enhanced RX FIFO Filter Elements (ERFFEL), the impact of each MB or ERFFEL depends on the configuration of the payload buffer, MB and/or ERFFEL. In this post, we plan to provide some examples of such configuration and impact on the FlexCAN IP.  Taking a 64-byte payload as an example, the following configurations illustrate the trade-off between the number of Message Buffers (MBs) and acceptance filters: /* ERR053377: This errata explains affected words depends on MB payload size, this example applies for MB configured for 64-byte payload */ #define BYTES_IN_MB kFLEXCAN_64BperMB FLEXCAN_FDInit(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ, BYTES_IN_MB, true); 1. MB0 is not used, MB1 is used. In this configuration, ERFFEL[0–29] can be fully utilized as acceptance filters, while MB1–MB6 are available as Message Buffers, maximum ERFCR[NFE] is 14. The following code can be used as reference for the driver configuration for this case.  /* Config fifo filters to make it accept STD frame with ID 0x123 ~ 0x140. Used ERFFEL[0–29], ERFCR[NFE]=14 */ uint32_t rxEnFifoFilter[] = {FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x123, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x124, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x125, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x126, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x127, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x128, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x129, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12E, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12F, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x130, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x131, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x132, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x133, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x134, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x135, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x136, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x137, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x138, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x139, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13E, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13F, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x140, 0, 0x3F, 0)}; flexcan_enhanced_rx_fifo_config_t rxEhFifoConfig; flexcan_rx_mb_config_t mbConfig; /* Setup Enhanced Rx FIFO. */ rxEhFifoConfig.idFilterTable = rxEnFifoFilter; rxEhFifoConfig.idFilterPairNum = sizeof(rxEnFifoFilter) / sizeof(rxEnFifoFilter[0]) / 2U; rxEhFifoConfig.extendIdFilterNum = 0; rxEhFifoConfig.fifoWatermark = RX_MESSAGE_COUNT - 1U; /* Reduce the frequency to enter IRQ. */ rxEhFifoConfig.dmaPerReadLength = kFLEXCAN_19WordPerRead; rxEhFifoConfig.priority = kFLEXCAN_RxFifoPrioHigh; FLEXCAN_SetEnhancedRxFifoConfig(EXAMPLE_CAN, &rxEhFifoConfig, true); rxFifoXfer.framefd = &rxFrame[0]; rxFifoXfer.frameNum = RX_MESSAGE_COUNT; /* Set Rx Masking mechanism for MB. Only accept data frame with desired ID. */ FLEXCAN_SetRxMbGlobalMask(EXAMPLE_CAN, FLEXCAN_RX_MB_STD_MASK(0x7FFU, 0, 0)); #define RX_MESSAGE_BUFFER_1 (1U) /* Setup Rx Message Buffer 1. */ mbConfig.format = kFLEXCAN_FrameFormatStandard; mbConfig.type = kFLEXCAN_FrameTypeData; mbConfig.id = FLEXCAN_ID_STD(0x121U); FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_1, &mbConfig, true); 2. MB0 and MB1 are not used. In this case, ERFFEL[0–31] are available for acceptance filtering, and MB2–MB6 are reserved as Message Buffers, maximum ERFCR[NFE] is 15. The following code can be used as reference for the driver configuration for this case.  /* Config fifo filters to make it accept STD frame with ID 0x123 ~ 0x142. Used ERFFEL[0–31], ERFCR[NFE]=15 */ uint32_t rxEnFifoFilter[] = {FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x123, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x124, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x125, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x126, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x127, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x128, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x129, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12E, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12F, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x130, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x131, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x132, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x133, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x134, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x135, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x136, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x137, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x138, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x139, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13E, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13F, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x140, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x141, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x142, 0, 0x3F, 0)}; flexcan_enhanced_rx_fifo_config_t rxEhFifoConfig; /* Setup Enhanced Rx FIFO. */ rxEhFifoConfig.idFilterTable = rxEnFifoFilter; rxEhFifoConfig.idFilterPairNum = sizeof(rxEnFifoFilter) / sizeof(rxEnFifoFilter[0]) / 2U; rxEhFifoConfig.extendIdFilterNum = 0; rxEhFifoConfig.fifoWatermark = RX_MESSAGE_COUNT - 1U; /* Reduce the frequency to enter IRQ. */ rxEhFifoConfig.dmaPerReadLength = kFLEXCAN_19WordPerRead; rxEhFifoConfig.priority = kFLEXCAN_RxFifoPrioHigh; FLEXCAN_SetEnhancedRxFifoConfig(EXAMPLE_CAN, &rxEhFifoConfig, true); rxFifoXfer.framefd = &rxFrame[0]; rxFifoXfer.frameNum = RX_MESSAGE_COUNT; 3. MB0 and MB1 are both used. Under this configuration, only ERFFEL[0–11] can be used as acceptance filters. ERFFEL[12–31] are not available, while MB0–MB6 can be used as Message Buffers, maximum ERFCR[NFE] is 5. The following code can be used as reference for the driver configuration for this case.  /* Config fifo filters to make it accept STD frame with ID 0x123 ~ 0x12E. Used ERFFEL[0–11], ERFCR[NFE]=5 */ uint32_t rxEnFifoFilter[] = {FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x123, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x124, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x125, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x126, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x127, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x128, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x129, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12E, 0, 0x3F, 0)}; flexcan_enhanced_rx_fifo_config_t rxEhFifoConfig; flexcan_rx_mb_config_t mbConfig; /* Setup Enhanced Rx FIFO. */ rxEhFifoConfig.idFilterTable = rxEnFifoFilter; rxEhFifoConfig.idFilterPairNum = sizeof(rxEnFifoFilter) / sizeof(rxEnFifoFilter[0]) / 2U; rxEhFifoConfig.extendIdFilterNum = 0; rxEhFifoConfig.fifoWatermark = RX_MESSAGE_COUNT - 1U; /* Reduce the frequency to enter IRQ. */ rxEhFifoConfig.dmaPerReadLength = kFLEXCAN_19WordPerRead; rxEhFifoConfig.priority = kFLEXCAN_RxFifoPrioHigh; FLEXCAN_SetEnhancedRxFifoConfig(EXAMPLE_CAN, &rxEhFifoConfig, true); rxFifoXfer.framefd = &rxFrame[0]; rxFifoXfer.frameNum = RX_MESSAGE_COUNT; /* Set Rx Masking mechanism for MB. Only accept data frame with desired ID. */ FLEXCAN_SetRxMbGlobalMask(EXAMPLE_CAN, FLEXCAN_RX_MB_STD_MASK(0x7FFU, 0, 0)); #define RX_MESSAGE_BUFFER_0 (0U) /* Setup Rx Message Buffer 0. */ mbConfig.format = kFLEXCAN_FrameFormatStandard; mbConfig.type = kFLEXCAN_FrameTypeData; mbConfig.id = FLEXCAN_ID_STD(0x120U); FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_0, &mbConfig, true); #define RX_MESSAGE_BUFFER_1 (1U) /* Setup Rx Message Buffer 1. */ mbConfig.format = kFLEXCAN_FrameFormatStandard; mbConfig.type = kFLEXCAN_FrameTypeData; mbConfig.id = FLEXCAN_ID_STD(0x121U); FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_1, &mbConfig, true); Recommendation: To achieve a balanced trade-off between the number of Message Buffers and acceptance filters, Option 1 is recommended.

This post will cover how to install the CMSIS-DAP/SEGGER J-link firmware for the KW47-EVK and FRDM-MCXW72 using NXP’s MCU-LINK installer. CMSIS-DAP Installation for KW47-EVK Place a jumper on JP20 1-2 while the board is disconnected  Connect the board using a USB-A to USB-C cable between the host PC and the KW47-EVK board’s J14 connector, the D13 red LED should turn ON, indicating that the board is in ISP mode.                         Double click the script called program_CMSIS or program_JLINK  to execute the script. These scripts are found on the following path: C:\NXP\MCU-LINK_installer_3.167\scripts​ ​Note: MCU-Link installer version may vary. Press any key to execute the script, if the board entered ISP mode correctly, the board will be programmed with the selected debug probe firmware:    for FRDM-MCXW72  Place a jumper on JP5 1-2 while the board is disconnected    Connect the board using a USB-A to USB-C cable between the host PC and the FRDM-MCXW72 board’s J10 connector, the ISP_EN_ML INK red LED should turn ON, indicating that the board is in ISP mode.                                                              Double click the script called program_CMSIS to open the command window. This script is found on the following path:  C:\NXP\MCU-LINK_installer_3.167\scripts​​​  Note: MCU-Link installer version may vary.   Press any key to execute the script, if the board entered ISP mode correctly, the board will be programmed with the CMISIS-DAP firmware:                              Once the sequence finishes, the command window will display a completion message like the example below:    Remove the ISP jumper (JP5). Then reboot the board by disconnecting it from the host PC and reconnecting it again. After reconnecting, the ISP_EN_MLINK red LED should be OFF, and the USB_ACT green LED should be ON.    

This pages is used to log key items related with KW4X products evaluation, development with SDK, power and RF performance evaluation, etc.

What's DPP? DPP:Device Provisioning Protocol It is also called: Wi-Fi Easy Connect.   The DUT is a device that needs to join the network. It actively initiates DPP authentication (Initiator + Enrollee), which is configured by CTT1, and finally joins the Wi-Fi network provided by CTT2 (Responder + AP) as a STA.   DPP Role introduction： CTT1 (Configurator) Reads DUT's bootstrap key Coordinates DPP Authentication/Configuration Sends Wi‑Fi credentials to the DUT DUT (Initiator + Enrollee + STA) Is the device being provisioned Initiates DPP Authentication toward CTT2 Receives Wi‑Fi credentials from CTT1 Connects as a STA to the AP on CTT2 CTT2 (Responder + AP + Enrollee) Responds to DUT’s DPP Authentication messages Operates as an AP using hostapd The DUT will join this AP after provisioning   Below is the process flow： 1.Add a Configurator and generate QR code on CTT1 (configurator). 2.Authenticate the DUT on DUT(STA) 3.Generate the QR Code and get URI on CTT2 4.Enter the QR Code on CTT1 and authenticate 5.Update AP configuration on CTT2 6.The connection between the DUT (STA) and CTT2 (AP) is successful.     Reference: https://docs.nxp.com/bundle/RM00297/page/connectivity-features/topics/wi-fi_easy_connect_dpp.html Wi-Fi Easy Connect Specification   The red fonts in the pdf are commands. The green fonts in the pdf are comments. CTT1：Configurator Typically, it's a mobile phone or PC used to scan QR codes and issue Wi-Fi credentials. IMX93-EVK+IW612 module   imx93evk login: root root@imx93evk:~# uname -a Linux imx93evk 6.12.34-lts-next-gbe78e49cb433 #1 SMP PREEMPT Wed Sep  3 05:59:19 UTC 2025 aarch64 GNU/Linux root@imx93evk:~# cat /lib/firmware/nxp/wifi_mod_para.conf     SDIW612 = { cfg80211_wext=0xf max_vir_bss=1 cal_data_cfg=none ps_mode=2 auto_ds=2 host_mlme=1 drv_mode=0x17 fw_name=nxp/sduart_nw61x_v1.bin.se }   root@imx93evk:~# vi wpa_supplicant.conf root@imx93evk:~# cat wpa_supplicant.conf ctrl_interface=/var/run/wpa_supplicant ctrl_interface_group=0 update_config=1 dpp_config_processing=2     modprobe moal mod_para=nxp/wifi_mod_para.conf   root@imx93evk:~# wpa_supplicant -i mlan0 -D nl80211 -c wpa_supplicant.conf -B & [1] 678 root@imx93evk:~# Successfully initialized wpa_supplicant rfkill: Cannot open RFKILL control device   [1]+  Done                    wpa_supplicant -i mlan0 -D nl80211 -c wpa_supplicant.conf -B root@imx93evk:~# root@imx93evk:~# root@imx93evk:~# wpa_cli wpa_cli v2.11-M005 Copyright (c) 2004-2024, Jouni Malinen <[email protected]> and contributors   This software may be distributed under the terms of the BSD license. See README for more details.     Selected interface 'mlan0'   Interactive mode   > DPP_CONFIGURATOR_ADD 1 > SET dpp_configurator_params " conf=sta-dpp configurator=1" OK > DPP_BOOTSTRAP_GEN type=qrcode chan=81/1 mac=fc:84:a7:51:87:fc //MAC address of CTT1 itself. 1 > DPP_BOOTSTRAP_GET_URI 1  //Attention here, after this command, will generate a QR code, which will be use on DUT with command:DPP_QR_CODE DPP:C:81/1;M:fc84a75187fc;V:2;K:MDkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDIgAD/bYibd4JdGvnK1etdgX/z4P+aJE2ztv89Q8xwjmbZNc=;; > DPP_LISTEN 2412 role=configurator OK   //Hold on here, and now go to DUT side to authenticate the DUT with above QR Code. After authenticate on DUT, will auto output below logs.   <3>DPP-RX src=20:4e:f6:bb:08:d9 freq=2412 type=0 <3>DPP-TX dst=20:4e:f6:bb:08:d9 freq=2412 type=1 <3>DPP-TX-STATUS dst=20:4e:f6:bb:08:d9 freq=2412 result=SUCCESS <3>DPP-RX src=20:4e:f6:bb:08:d9 freq=2412 type=2 <3>DPP-AUTH-SUCCESS init=0 pkhash=74a40ec058ac8c7f7acb6589253e76f5d1a9582359353bcd5e6983ee97c3a382 own=1 peer=-1 <3>DPP-CONF-REQ-RX src=20:4e:f6:bb:08:d9 <3>DPP-BAND-SUPPORT 81,82,83,84,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130 <3>DPP-RX src=20:4e:f6:bb:08:d9 freq=2412 type=11 <3>DPP-CONF-SENT conf_status=0   //Now continue, after you generate the QR Code and get URI on CTT2. Enter the QR Code on CTT1 and authenticate: > DPP_QR_CODE DPP:C:81/1;M:02e93a0db8cd;V:2;K:MDkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDIgACQOp5kWO1ex4L2U5rRXdS9yPYWA9NdRXTsuT+v5L/jvc=;; 2 //On successfully adding QR Code, a bootstrapping info id is returned as shown 2 in above command and should input in below command DPP_AUTH_INIT > DPP_AUTH_INIT peer=2 conf=ap-dpp configurator=1 OK //Now go to CTT2 to update AP configurations. <3>DPP-TX dst=02:e9:3a:0d:b8:cd freq=2412 type=0 <3>DPP-TX-STATUS dst=02:e9:3a:0d:b8:cd freq=2412 result=SUCCESS <3>DPP-RX src=02:e9:3a:0d:b8:cd freq=2412 type=1 <3>DPP-AUTH-DIRECTION mutual=0 <3>DPP-TX dst=02:e9:3a:0d:b8:cd freq=2412 type=2 <3>DPP-TX-STATUS dst=02:e9:3a:0d:b8:cd freq=2412 result=SUCCESS <3>DPP-AUTH-SUCCESS init=1 pkhash=22233c6d83a272944eeb9788870b0b564b46ba8d48fd80787f5cc22bcec95c87 own=-1 peer=2 <3>DPP-CONF-REQ-RX src=02:e9:3a:0d:b8:cd <3>DPP-RX src=02:e9:3a:0d:b8:cd freq=2412 type=11 <3>DPP-CONF-SENT conf_status=0     > list_networks network id / ssid / bssid / flags > quit root@imx93evk:~# cat /proc/mwlan/adapter0/mlan0/info driver_name = "wlan" driver_version = SDIW612---18.99.3.p26.7-MM6X18540.p7-(FP92) interface_name="mlan0" firmware_major_version=18.99.3 uuid = 1653948cf99e5b2bbe5ad9b851d6151a bss_mode ="Managed" media_state="Disconnected" mac_address="fc:84:a7:51:87:fc" multicast_count="2" essid="" bssid="00:00:00:00:00:00" channel="0" region_code = "00" multicast_address[0]="33:33:00:00:00:01" multicast_address[1]="01:00:5e:00:00:01" num_tx_bytes = 0 num_rx_bytes = 0 num_tx_pkts = 0 num_rx_pkts = 0 num_tx_pkts_dropped = 0 num_rx_pkts_dropped = 0 num_tx_pkts_err = 0 num_rx_pkts_err = 0 carrier off tx queue 0:  stopped tx queue 1:  stopped tx queue 2:  stopped tx queue 3:  stopped === tp_acnt.on:0 drop_point:0 === ====Tx accounting==== [0] Tx packets     : 0 [0] Tx packets last: 0 [0] Tx packets rate: 0 [0] Tx bytes       : 0 [0] Tx bytes last  : 0 [0] Tx bytes rate  : 0Mbps [1] Tx packets     : 0 [1] Tx packets last: 0 [1] Tx packets rate: 0 [1] Tx bytes       : 0 [1] Tx bytes last  : 0 [1] Tx bytes rate  : 0Mbps [2] Tx packets     : 0 [2] Tx packets last: 0 [2] Tx packets rate: 0 [2] Tx bytes       : 0 [2] Tx bytes last  : 0 [2] Tx bytes rate  : 0Mbps [3] Tx packets     : 0 [3] Tx packets last: 0 [3] Tx packets rate: 0 [3] Tx bytes       : 0 [3] Tx bytes last  : 0 [3] Tx bytes rate  : 0Mbps [4] Tx packets     : 0 [4] Tx packets last: 0 [4] Tx packets rate: 0 [4] Tx bytes       : 0 [4] Tx bytes last  : 0 [4] Tx bytes rate  : 0Mbps Tx amsdu cnt            : 0 Tx amsdu cnt last       : 0 Tx amsdu cnt rate       : 0 Tx amsdu pkt cnt        : 0 Tx amsdu pkt cnt last : 0 Tx amsdu pkt cnt rate : 0 Tx intr cnt             : 1 Tx intr last        : 0 Tx intr rate        : 0 Tx pending          : 0 Tx xmit skb realloc : 0 Tx stop queue cnt : 0 ====Rx accounting==== [0] Rx packets     : 0 [0] Rx packets last: 0 [0] Rx packets rate: 0 [0] Rx bytes       : 0 [0] Rx bytes last  : 0 [0] Rx bytes rate  : 0Mbps [1] Rx packets     : 0 [1] Rx packets last: 0 [1] Rx packets rate: 0 [1] Rx bytes       : 0 [1] Rx bytes last  : 0 [1] Rx bytes rate  : 0Mbps [2] Rx packets     : 0 [2] Rx packets last: 0 [2] Rx packets rate: 0 [2] Rx bytes       : 0 [2] Rx bytes last  : 0 [2] Rx bytes rate  : 0Mbps [3] Rx packets     : 0 [3] Rx packets last: 0 [3] Rx packets rate: 0 [3] Rx bytes       : 0 [3] Rx bytes last  : 0 [3] Rx bytes rate  : 0Mbps [4] Rx packets     : 0 [4] Rx packets last: 0 [4] Rx packets rate: 0 [4] Rx bytes       : 0 [4] Rx bytes last  : 0 [4] Rx bytes rate  : 0Mbps Rx amsdu cnt             : 0 Rx amsdu cnt last        : 0 Rx amsdu cnt rate        : 0 Rx amsdu pkt cnt         : 0 Rx amsdu pkt cnt last : 0 Rx amsdu pkt cnt rate : 0 Rx intr cnt      : 7 Rx intr last        : 0 Rx intr rate        : 0 Rx pending          : 0 Rx pause            : 0 Rx rdptr full cnt   : 0 root@imx93evk:~#     DUT：Initiator + Enrollee + STA The device you want it to join the network. IMX8MQ-EVK+88W8997 module     root@imx8mqevk:~# uname -a Linux imx8mqevk 6.12.49-lts-next-gdf24f9428e38 #1 SMP PREEMPT Fri Nov 21 03:24:46 UTC 2025 aarch64 GNU/Linux   root@imx8mqevk:~# cat /lib/firmware/nxp/wifi_mod_para.conf   PCIE8997 = {         cfg80211_wext=0xf         max_vir_bss=1         cal_data_cfg=none         ps_mode=1         auto_ds=1         host_mlme=1         fw_name=nxp/pcieuart8997_combo_v4.bin }     root@imx8mqevk:~# cat wpa_supplicant.conf ctrl_interface=/var/run/wpa_supplicant ctrl_interface_group=0 update_config=1 dpp_config_processing=2   root@imx8mqevk:~# modprobe moal mod_para=nxp/wifi_mod_para.conf     root@imx8mqevk:~# wpa_supplicant -i mlan0 -D nl80211 -c wpa_supplicant.conf -B & [1] 799 root@imx8mqevk:~# Successfully initialized wpa_supplicant rfkill: Cannot open RFKILL control device   [1]+  Done                    wpa_supplicant -i mlan0 -D nl80211 -c wpa_supplicant.conf -B root@imx8mqevk:~# wpa_cli wpa_cli v2.11-M005 Copyright (c) 2004-2024, Jouni Malinen <[email protected]> and contributors   This software may be distributed under the terms of the BSD license. See README for more details.     Selected interface 'mlan0'   Interactive mode   > DPP_QR_CODE DPP:C:81/1;M:fc84a75187fc;V:2;K:MDkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDIgAD/bYibd4JdGvnK1etdgX/z4P+aJE2ztv89Q8xwjmbZNc=;; 1 > DPP_AUTH_INIT peer=1 role=enrollee OK <3>DPP-TX dst=fc:84:a7:51:87:fc freq=2412 type=0 <3>DPP-TX-STATUS dst=fc:84:a7:51:87:fc freq=2412 result=SUCCESS <3>DPP-RX src=fc:84:a7:51:87:fc freq=2412 type=1 <3>DPP-AUTH-DIRECTION mutual=0 <3>DPP-TX dst=fc:84:a7:51:87:fc freq=2412 type=2 <3>DPP-TX-STATUS dst=fc:84:a7:51:87:fc freq=2412 result=SUCCESS <3>DPP-AUTH-SUCCESS init=1 pkhash=6785abbd108e5ef6fe780819634ef620fc6eb71715b92b07f393e58af7afa0b6 own=-1 peer=1 <3>GAS-QUERY-START addr=fc:84:a7:51:87:fc dialog_token=199 freq=2412 <3>GAS-QUERY-DONE addr=fc:84:a7:51:87:fc dialog_token=199 freq=2412 status_code=0 result=SUCCESS <3>DPP-CONF-RECEIVED <3>DPP-CONFOBJ-AKM dpp <3>DPP-CONFOBJ-SSID test <3>DPP-CONNECTOR eyJ0eXAiOiJkcHBDb24iLCJraWQiOiJWV0hoQmp0enJVZ0xTSjhpTTJDRmRtNkxPQ0FFWHVCSWJEU3hzMEhaSDhnIiwiYWxnIjoiRVMyNTYifQ.eyJncm91cHMiOlt7Imdyb3VwSWQiOiIqIiwibmV0Um9sZSI6InN0YSJ9XSwibmV0QWNjZXNzS2V5Ijp7Imt0eSI6IkVDIiwiY3J2IjoiUC0yNTYiLCJ4IjoibjBQbXlSMVhUUE14WUNiM2tqYjF1Yjh3Q055bUUtREFTcE4tZ2I0ZDhDcyIsInkiOiJfbmlkd1V6NkFkM1AySy1RYVJuXzZTem9KYlJWRGt3d0VYeTdZU2JoMDU4In19.kfVVpSaFNaTfoLVE5Yu16bLMfpSlVXGlul07FNwQ7gLPlYOTGS5lbOLwCTkP246kSC1Wn-8MWSUXpxgpSpsX2A <3>DPP-C-SIGN-KEY 3039301306072a8648ce3d020106082a8648ce3d0301070322000226d58dd75a168da8b901b47e01694868af2158d57db2984784349e12768e668b <3>DPP-PP-KEY 3039301306072a8648ce3d020106082a8648ce3d03010703220002a0008bd0723f2723408ef53550f5cbc55785ea625ec5265d81e16c0cd45a5e3a <3>DPP-NET-ACCESS-KEY 30770201010420cedd6e85e66768b1a8e14e2e048fd54b7f09277195c3db3f6b1887e8b449e872a00a06082a8648ce3d030107a144034200049f43e6c91d574cf3316026f79236f5b9bf3008dca613e0c04a937e81be1df02bfe789dc14cfa01ddcfd8af906919ffe92ce825b4550e4c30117cbb6126e1d39f <3>CTRL-EVENT-NETWORK-ADDED 0 <3>DPP-NETWORK-ID 0 <3>DPP-TX dst=fc:84:a7:51:87:fc freq=2412 type=11 <3>DPP-TX-STATUS dst=fc:84:a7:51:87:fc freq=2412 result=SUCCESS <3>CTRL-EVENT-SCAN-STARTED <3>CTRL-EVENT-SCAN-RESULTS <3>WPS-AP-AVAILABLE <3>CTRL-EVENT-NETWORK-NOT-FOUND <3>CTRL-EVENT-SCAN-STARTED <3>CTRL-EVENT-SCAN-RESULTS <3>WPS-AP-AVAILABLE <3>CTRL-EVENT-NETWORK-NOT-FOUND <3>CTRL-EVENT-SCAN-STARTED <3>CTRL-EVENT-SCAN-RESULTS <3>WPS-AP-AVAILABLE <3>CTRL-EVENT-NETWORK-NOT-FOUND > DPP_STOP_LISTEN OK   //All commands on DUT side finished until here. Now go to CTT2 side to continue, generate the QR Code and get URI on CTT2.   <3>CTRL-EVENT-SCAN-RESULTS <3>DPP-TX dst=02:e9:3a:0d:b8:cd freq=2412 type=5 <3>DPP-TX-STATUS dst=02:e9:3a:0d:b8:cd freq=2412 result=SUCCESS <3>DPP-RX src=02:e9:3a:0d:b8:cd freq=2412 type=6 <3>PMKSA-CACHE-ADDED 02:e9:3a:0d:b8:cd 0 <3>DPP-INTRO peer=02:e9:3a:0d:b8:cd status=0 version=2 <3>SME: Trying to authenticate with 02:e9:3a:0d:b8:cd (SSID='test' freq=2412 MHz) <3>Trying to associate with 02:e9:3a:0d:b8:cd (SSID='test' freq=2412 MHz) <3>Associated with 02:e9:3a:0d:b8:cd <3>CTRL-EVENT-SUBNET-STATUS-UPDATE status=0 <3>EAPOL-RX 02:e9:3a:0d:b8:cd 99 <3>EAPOL-RX 02:e9:3a:0d:b8:cd 195 <3>WPA: Key negotiation completed with 02:e9:3a:0d:b8:cd [PTK=CCMP GTK=CCMP] <3>CTRL-EVENT-CONNECTED - Connection to 02:e9:3a:0d:b8:cd completed [id=0 id_str=] > list_networks network id / ssid / bssid / flags 0       test    any     [CURRENT] > quit root@imx8mqevk:~# cat /proc/mwlan/adapter0/mlan0/info driver_name = "wlan" driver_version = PCIE8997--16.92.21.p153.7-MM6X16540.p33-GPL-(FP92) interface_name="mlan0" firmware_major_version=16.92.21 bss_mode ="Managed" media_state="Connected" mac_address="20:4e:f6:bb:08:d9" multicast_count="4" essid="test" bssid="02:e9:3a:0d:b8:cd" channel="1" region_code = "00" multicast_address[0]="33:33:00:00:00:01" multicast_address[1]="01:00:5e:00:00:01" multicast_address[2]="33:33:ff:bb:08:d9" multicast_address[3]="33:33:00:00:00:fb" num_tx_bytes = 2458 num_rx_bytes = 350 num_tx_pkts = 19 num_rx_pkts = 3 num_tx_pkts_dropped = 0 num_rx_pkts_dropped = 0 num_tx_pkts_err = 0 num_rx_pkts_err = 0 carrier on tx queue 0:  started tx queue 1:  started tx queue 2:  started tx queue 3:  started === tp_acnt.on:0 drop_point:0 === ====Tx accounting==== [0] Tx packets     : 0 [0] Tx packets last: 0 [0] Tx packets rate: 0 [0] Tx bytes       : 0 [0] Tx bytes last  : 0 [0] Tx bytes rate  : 0Mbps [1] Tx packets     : 0 [1] Tx packets last: 0 [1] Tx packets rate: 0 [1] Tx bytes       : 0 [1] Tx bytes last  : 0 [1] Tx bytes rate  : 0Mbps [2] Tx packets     : 0 [2] Tx packets last: 0 [2] Tx packets rate: 0 [2] Tx bytes       : 0 [2] Tx bytes last  : 0 [2] Tx bytes rate  : 0Mbps [3] Tx packets     : 0 [3] Tx packets last: 0 [3] Tx packets rate: 0 [3] Tx bytes       : 0 [3] Tx bytes last  : 0 [3] Tx bytes rate  : 0Mbps [4] Tx packets     : 0 [4] Tx packets last: 0 [4] Tx packets rate: 0 [4] Tx bytes       : 0 [4] Tx bytes last  : 0 [4] Tx bytes rate  : 0Mbps Tx amsdu cnt            : 0 Tx amsdu cnt last       : 0 Tx amsdu cnt rate       : 0 Tx amsdu pkt cnt        : 0 Tx amsdu pkt cnt last : 0 Tx amsdu pkt cnt rate : 0 Tx intr cnt             : 18 Tx intr last        : 0 Tx intr rate        : 0 Tx pending          : 0 Tx xmit skb realloc : 19 Tx stop queue cnt : 0 ====Rx accounting==== [0] Rx packets     : 0 [0] Rx packets last: 0 [0] Rx packets rate: 0 [0] Rx bytes       : 0 [0] Rx bytes last  : 0 [0] Rx bytes rate  : 0Mbps [1] Rx packets     : 0 [1] Rx packets last: 0 [1] Rx packets rate: 0 [1] Rx bytes       : 0 [1] Rx bytes last  : 0 [1] Rx bytes rate  : 0Mbps [2] Rx packets     : 0 [2] Rx packets last: 0 [2] Rx packets rate: 0 [2] Rx bytes       : 0 [2] Rx bytes last  : 0 [2] Rx bytes rate  : 0Mbps [3] Rx packets     : 0 [3] Rx packets last: 0 [3] Rx packets rate: 0 [3] Rx bytes       : 0 [3] Rx bytes last  : 0 [3] Rx bytes rate  : 0Mbps [4] Rx packets     : 0 [4] Rx packets last: 0 [4] Rx packets rate: 0 [4] Rx bytes       : 0 [4] Rx bytes last  : 0 [4] Rx bytes rate  : 0Mbps Rx amsdu cnt             : 0 Rx amsdu cnt last        : 0 Rx amsdu cnt rate        : 0 Rx amsdu pkt cnt         : 0 Rx amsdu pkt cnt last : 0 Rx amsdu pkt cnt rate : 0 Rx intr cnt      : 67 Rx intr last        : 0 Rx intr rate        : 0 Rx pending          : 0 Rx pause            : 0 Rx rdptr full cnt   : 0 root@imx8mqevk:~#                       CTT2 (AP)：Responder + AP + Enrollee IMX8MPlus EVK + 88W8997 module   root@imx8mpevk:~# uname -a Linux imx8mpevk 6.12.49-lts-next-gdf24f9428e38 #1 SMP PREEMPT Fri Nov 21 03:24:46 UTC 2025 aarch64 GNU/Linux       root@imx8mpevk:~# cat /lib/firmware/nxp/wifi_mod_para.conf   PCIE8997 = {         cfg80211_wext=0xf         max_vir_bss=1         cal_data_cfg=none         ps_mode=1         auto_ds=1         host_mlme=1         fw_name=nxp/pcieuart8997_combo_v4.bin }   root@imx8mpevk:~# hostapd hostapd.conf -B & [1] 1731 root@imx8mpevk:~# HT (IEEE 802.11n) with WPA/WPA2 requires CCMP/GCMP to be enabled, disabling HT capabilities rfkill: Cannot open RFKILL control device uap0: interface state UNINITIALIZED->ENABLED uap0: AP-ENABLED   [1]+  Done                    hostapd hostapd.conf -B root@imx8mpevk:~# hostapd_cli hostapd_cli v2.11-M005 Copyright (c) 2004-2024, Jouni Malinen <[email protected]> and contributors   This software may be distributed under the terms of the BSD license. See README for more details.     Selected interface 'uap0'   Interactive mode > DPP_BOOTSTRAP_GEN type=qrcode chan=81/1 mac=02:e9:3a:0d:b8:cd //MAC address of CTT2 itself and returned 1 is bootstrap info id which require to get QR code in below command. 1> DPP_BOOTSTRAP_GET_URI 1 //Attention here, after this command, will generate a QR code, which will be use on CTT1 with command:DPP_QR_CODE. Then directly go to CTT1 to enter the QR Code. DPP:C:81/1;M:02e93a0db8cd;V:2;K:MDkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDIgACQOp5kWO1ex4L2U5rRXdS9yPYWA9NdRXTsuT+v5L/jvc=;;>     //Hold on here, and now go to CTT1 to authenticate this AP with above QR Code. After authenticate on CTT1 with QR Code, will auto output below logs. Pay attention on the keys and connectors info, will use them later when you update the AP.   > <3>DPP-RX src=fc:84:a7:51:87:fc freq=2412 type=0 <3>DPP-TX dst=fc:84:a7:51:87:fc freq=2412 type=1 <3>DPP-TX-STATUS dst=fc:84:a7:51:87:fc result=SUCCESS <3>DPP-RX src=fc:84:a7:51:87:fc freq=2412 type=2 <3>DPP-AUTH-SUCCESS init=0 pkhash=8b3e0f88b70610446a84f53ea9d792f5631b2b87e30cd219a8059c6f7893c501 own=1 peer=-1 <3>GAS-QUERY-START addr=fc:84:a7:51:87:fc dialog_token=0 freq=2412 <3>GAS-QUERY-DONE addr=fc:84:a7:51:87:fc dialog_token=0 freq=2412 status_code=0 result=SUCCESS <3>DPP-CONF-RECEIVED <3>DPP-CONFOBJ-AKM dpp <3>DPP-CONFOBJ-SSID test <3>DPP-CONNECTOR eyJ0eXAiOiJkcHBDb24iLCJraWQiOiJWV0hoQmp0enJVZ0xTSjhpTTJDRmRtNkxPQ0FFWHVCSWJEU3hzMEhaSDhnIiwiYWxnIjoiRVMyNTYifQ.eyJncm91cHMiOlt7Imdyb3VwSWQiOiIqIiwibmV0Um9sZSI6ImFwIn1dLCJuZXRBY2Nlc3NLZXkiOnsia3R5IjoiRUMiLCJjcnYiOiJQLTI1NiIsIngiOiJEbVRmSVFTRFNPVXVkVFBkN0pobEQtQ2xOa0U3U2lEWmctLWpYeGdNRXRJIiwieSI6Iml2NlVCc1J0YXhGSEpzcEtPbWFQSktqUmNDTFV5REh6WHFFeWtLbkhsOGcifX0.vEzfQywitO8AMvmcXenL_qidmkNl7t_jen2YW9OV8M5OID9jmTu-GqVUUkMEQE7R7Ja5vGnOMQ2-x-h7qyRKIQ <3>DPP-C-SIGN-KEY 3039301306072a8648ce3d020106082a8648ce3d0301070322000226d58dd75a168da8b901b47e01694868af2158d57db2984784349e12768e668b <3>DPP-NET-ACCESS-KEY 307702010104200be4b069c34a39d844fca856dd1e583a729e74f394370a4da8bc7d68d0dfadc2a00a06082a8648ce3d030107a144034200040e64df21048348e52e7533ddec98650fe0a536413b4a20d983efa35f180c12d28afe9406c46d6b114726ca4a3a668f24a8d17022d4c831f35ea13290a9c797c8 <3>DPP-TX dst=fc:84:a7:51:87:fc freq=2412 type=11 <3>DPP-TX-STATUS dst=fc:84:a7:51:87:fc result=SUCCESS   //Now update AP configurations on CTT2: //First disable AP: > disable <3>AP-DISABLED OK   //Update AP parameters: > set ssid test OK > set wpa 2 OK > set wpa_key_mgmt DPP OK > set ieee80211w 2 OK > set rsn_pairwise CCMP OK > set dpp_connector eyJ0eXAiOiJkcHBDb24iLCJraWQiOiJWV0hoQmp0enJVZ0xTSjhpTTJDRmRtNkxPQ0FFWHVCSWJEU3hzMEhaSDhnIiwiYWxnIjoiRVMyNTYifQ.eyJncm91cHMiOlt7Imdyb3VwSWQiOiIqIiwibmV0Um9sZSI6ImFwIn1dLCJuZXRBY2Nlc3NLZXkiOnsia3R5IjoiRUMiLCJjcnYiOiJQLTI1NiIsIngiOiJEbVRmSVFTRFNPVXVkVFBkN0pobEQtQ2xOa0U3U2lEWmctLWpYeGdNRXRJIiwieSI6Iml2NlVCc1J0YXhGSEpzcEtPbWFQSktqUmNDTFV5REh6WHFFeWtLbkhsOGcifX0.vEzfQywitO8AMvmcXenL_qidmkNl7t_jen2YW9OV8M5OID9jmTu-GqVUUkMEQE7R7Ja5vGnOMQ2-x-h7qyRKIQ OK > set dpp_csign 3039301306072a8648ce3d020106082a8648ce3d0301070322000226d58dd75a168da8b901b47e01694868af2158d57db2984784349e12768e668b OK > set dpp_netaccesskey 307702010104200be4b069c34a39d844fca856dd1e583a729e74f394370a4da8bc7d68d0dfadc2a00a06082a8648ce3d030107a144034200040e64df21048348e52e7533ddec98650fe0a536413b4a20d983efa35f180c12d28afe9406c46d6b114726ca4a3a668f24a8d17022d4c831f35ea13290a9c797c8 OK   //Re-enable the AP after updates: > enable <3>AP-ENABLED OK   //just wait here, it will output below logs after some seconds. > <3>DPP-RX src=20:4e:f6:bb:08:d9 freq=2412 type=5 <3>DPP-TX dst=20:4e:f6:bb:08:d9 freq=2412 type=6 status=0 <3>DPP-TX-STATUS dst=20:4e:f6:bb:08:d9 result=SUCCESS <3>AP-STA-CONNECTED 20:4e:f6:bb:08:d9 dpp_pkhash=74a40ec058ac8c7f7acb6589253e76f5d1a9582359353bcd5e6983ee97c3a382 <3>EAPOL-4WAY-HS-COMPLETED 20:4e:f6:bb:08:d9 > quit > root@imx8mpevk:~# cat /proc/mwlan/adapter0/uap0/info driver_name = "uap" driver_version = PCIE8997--w8997o-V4, RF878X, FP92, 16.92.21.p153.7-MM6X16540.p33-GPL-(FP92) interface_name="uap0" firmware_major_version=16.92.21 media_state="Connected" mac_address="02:e9:3a:0d:b8:cd" num_tx_bytes = 462 num_rx_bytes = 2248 num_tx_pkts = 4 num_rx_pkts = 20 num_tx_pkts_dropped = 0 num_rx_pkts_dropped = 0 num_tx_pkts_err = 60 num_rx_pkts_err = 0 carrier on tx queue 0:  started tx queue 1:  started tx queue 2:  started tx queue 3:  started tkip_mic_failures = 0 ccmp_decrypt_errors = 0 wep_undecryptable_count = 0 wep_icv_error_count = 0 decrypt_failure_count = 0 mcast_tx_count = 20 failed_count = 3 retry_count = 0 multiple_retry_count = 0 frame_duplicate_count = 0 rts_success_count = 0 rts_failure_count = 0 ack_failure_count = 30 rx_fragment_count = 55 mcast_rx_frame_count = 18 fcs_error_count = 401368 tx_frame_count = 22 rsna_tkip_cm_invoked = 0 rsna_4way_hshk_failures = 0 === tp_acnt.on:0 drop_point:0 === ====Tx accounting==== [0] Tx packets     : 0 [0] Tx packets last: 0 [0] Tx packets rate: 0 [0] Tx bytes       : 0 [0] Tx bytes last  : 0 [0] Tx bytes rate  : 0Mbps [1] Tx packets     : 0 [1] Tx packets last: 0 [1] Tx packets rate: 0 [1] Tx bytes       : 0 [1] Tx bytes last  : 0 [1] Tx bytes rate  : 0Mbps [2] Tx packets     : 0 [2] Tx packets last: 0 [2] Tx packets rate: 0 [2] Tx bytes       : 0 [2] Tx bytes last  : 0 [2] Tx bytes rate  : 0Mbps [3] Tx packets     : 0 [3] Tx packets last: 0 [3] Tx packets rate: 0 [3] Tx bytes       : 0 [3] Tx bytes last  : 0 [3] Tx bytes rate  : 0Mbps [4] Tx packets     : 0 [4] Tx packets last: 0 [4] Tx packets rate: 0 [4] Tx bytes       : 0 [4] Tx bytes last  : 0 [4] Tx bytes rate  : 0Mbps Tx amsdu cnt            : 0 Tx amsdu cnt last       : 0 Tx amsdu cnt rate       : 0 Tx amsdu pkt cnt        : 0 Tx amsdu pkt cnt last : 0 Tx amsdu pkt cnt rate : 0 Tx intr cnt             : 22 Tx intr last        : 0 Tx intr rate        : 0 Tx pending          : 0 Tx xmit skb realloc : 64 Tx stop queue cnt : 0 ====Rx accounting==== [0] Rx packets     : 0 [0] Rx packets last: 0 [0] Rx packets rate: 0 [0] Rx bytes       : 0 [0] Rx bytes last  : 0 [0] Rx bytes rate  : 0Mbps [1] Rx packets     : 0 [1] Rx packets last: 0 [1] Rx packets rate: 0 [1] Rx bytes       : 0 [1] Rx bytes last  : 0 [1] Rx bytes rate  : 0Mbps [2] Rx packets     : 0 [2] Rx packets last: 0 [2] Rx packets rate: 0 [2] Rx bytes       : 0 [2] Rx bytes last  : 0 [2] Rx bytes rate  : 0Mbps [3] Rx packets     : 0 [3] Rx packets last: 0 [3] Rx packets rate: 0 [3] Rx bytes       : 0 [3] Rx bytes last  : 0 [3] Rx bytes rate  : 0Mbps [4] Rx packets     : 0 [4] Rx packets last: 0 [4] Rx packets rate: 0 [4] Rx bytes       : 0 [4] Rx bytes last  : 0 [4] Rx bytes rate  : 0Mbps Rx amsdu cnt             : 0 Rx amsdu cnt last        : 0 Rx amsdu cnt rate        : 0 Rx amsdu pkt cnt         : 0 Rx amsdu pkt cnt last : 0 Rx amsdu pkt cnt rate : 0 Rx intr cnt      : 28229 Rx intr last        : 0 Rx intr rate        : 0 Rx pending          : 0 Rx pause            : 0 Rx rdptr full cnt   : 0 root@imx8mpevk:~#            

Most available example applications use UART as the serial interface for terminal communication. This approach is commonly chosen because a terminal provides a simple and efficient method for interacting with the application during development and debugging. The KW47-EVK supports two CAN/CAN-FD interface; as well as two UART interfaces accessible through the onboard USB-to-UART bridge.  The corresponding SoC peripheral instances are CAN0 and CAN1 for the CAN/CAN‑FD interfaces, and LPUART0 and LPUART1 for the UART interfaces. Since the LPUART1 serial interface and the CAN1 interface are routed to the same pins (PTC2 and PTC3) at the board level, and both functions can be enabled through header configuration, external isolation is required to ensure correct operation and prevent interference from other onboard components. If CAN1 must be enabled and your application also requires a serial terminal interface, then LPUART0 must be used as the serial interface.To enable both CAN1 and LPUART0 on the KW47‑EVK, follow the steps below: Changes required on hardware CAN Node A CAN Node B Pin name Board jumper Pin name Board jumper CANH J21 - 1 CANH J21 - 1 CANL J21 - 2 CANL J21 - 2 GND J21 - 4 GND J21 - 4 P12V J21 - 3 P12V J21 - 3  Note: Plug in the 12V power supply on J9 to supply the P5V_CAN. LPUART0 interface connection Functionality Board jumper Connection configuration LIN_RX JP11 2 - 3 LIN_TX JP12 2 - 3 UART_RX_USB selector JP16 2 - 3 UART_TX_USB selector JP17 2 - 3 CAN_RX_1 selector JP56 1 - 2 CAN_TX_1 selector JP57 1 - 2   Changes required on software Note: These steps assume you are using a FlexCAN SDK example application. If your application requires enabling CAN1 instead of the default CAN0, update the following configuration in your project’s source code: 1. In board.c, modify the LPUART instance, kCLOCK_Lpuart1 -> kCLOCK_Lpuart0: /* Initialize debug console. */ void BOARD_InitDebugConsole(void) { uint32_t uartClkSrcFreq = 0U; /* Set LPUART0 clock source */ CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcFro192M); uartClkSrcFreq = CLOCK_GetIpFreq(kCLOCK_Lpuart0); DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); } 2. In board.h, modify the LPUART instance definitions: BOARD_DEBUG_UART_BASEADDR LPUART1 -> LPUART0 BOARD_DEBUG_UART_INSTANCE 1U -> 0U BOARD_DEBUG_UART_CLK_FREQ kCLOCK_Lpuart1 -> kCLOCK_Lpuart0 /* The UART to use for debug messages. */ #define BOARD_USE_LPUART #define BOARD_DEBUG_UART_TYPE kSerialPort_Uart #define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART0 #define BOARD_DEBUG_UART_INSTANCE 0U #define BOARD_DEBUG_UART_CLK_FREQ (CLOCK_GetIpFreq(kCLOCK_Lpuart0)) 3. In hardware_init.c, modify the CAN instance to CAN1 at FlexCAN functional clock configuration: void BOARD_InitHardware(void) { BOARD_InitPins(); BOARD_BootClockRUN(); BOARD_InitDebugConsole(); /* FRO192M is configured as CAN1 functional clock in this example but other clock options may be available */ CLOCK_SetIpSrc(kCLOCK_Can1, kCLOCK_IpSrcFro192M); CLOCK_SetIpSrcDiv(kCLOCK_Can1, kSCG_SysClkDivBy1); } 4. In app.h, modify the EXAMPLE_CAN definition to CAN1: #define EXAMPLE_CAN CAN1 #define USE_CANFD (1) #define RX_MESSAGE_BUFFER_NUM (0) #define TX_MESSAGE_BUFFER_NUM (1) 5. In pin_mux.c, modify pin multiplexing configuration to enable CAN1 and LPUART0 pins respectively. You can copy and paste the below code to replace BOARD_InitPins function: void BOARD_InitPins(void) { /* Clock Config: Peripheral clocks are enabled; module does not stall low power mode entry */ CLOCK_EnableClock(kCLOCK_PortA); CLOCK_EnableClock(kCLOCK_PortC); const port_pin_config_t porta16_pin11_config = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPUART0_RX */ (uint16_t)kPORT_MuxAlt6, /* Does not invert */ (uint16_t)kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTA16 (pin 11) is configured as LPUART0_RX */ PORT_SetPinConfig(PORTA, 16U, &porta16_pin11_config); const port_pin_config_t porta17_pin12_config = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPUART0_TX */ (uint16_t)kPORT_MuxAlt6, /* Does not invert */ (uint16_t)kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTA17 (pin 12) is configured as LPUART0_TX */ PORT_SetPinConfig(PORTA, 17U, &porta17_pin12_config); const port_pin_config_t portc2_pin39_config = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as CAN1_RX */ (uint16_t)kPORT_MuxAlt11, /* Does not invert */ (uint16_t)kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTC2 (pin 39) is configured as CAN1_RX */ PORT_SetPinConfig(PORTC, 2U, &portc2_pin39_config); const port_pin_config_t portc3_pin40_config = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as CAN1_TX */ (uint16_t)kPORT_MuxAlt11, /* Does not invert */ (uint16_t)kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTC3 (pin 43) is configured as CAN1_TX */ PORT_SetPinConfig(PORTC, 3U, &portc3_pin40_config); } Run your demo application Connect a USB cable between the host PC and the KW47-EVK board J14. Open a serial terminal on PC for each board with the following settings: 115200 baud rate 8 data bits No parity One stop bit No flow control Download the program to the target board Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.

The KW43 product family is a low-power, secure, single-chip wireless MCU that integrates a high performance, Bluetooth Low Energy, Bluetooth Channel Sounding, EdgeLock Secure Accelerators, and various MCU peripherals targeted for Automotive applications. The KW43 family utilizes an Arm® Cortex®-M33 core (Armv8-M architecture) running up to 96 MHz for customer applications. The family includes memory configurations of up to 1.5MB flash and 256 KB SRAM across all listed part numbers. All devices in the family integrate a state-of-the-art, scalable security architecture including Arm’s TrustZone®-M, a resource domain controller and an isolated EdgeLock Secure Accelerators supporting hardware cryptographic accelerators, random number generators and key generation, storage, and management along with secure debug. All members of the KW43 family are designed to be compliant to a SESIP Level 3 certification following the Arm PSA Level 3 profile. KW43 uses dual Arm Core Cortex-M33 (‘CM33’) and supports multiple interfaces and security features. One is for application and system use and other is for radio link layer and both cores share a common flash of 1.5 MB. The devices include a full certified Bluetooth LE 6.x controller stack with support for up to 10 simultaneous connections in any controller/peripheral combination. The multiprotocol radio subsystem integrated in the KW43 Family is energy efficient and is designed for Wi-Fi coexistence. The radio is supported with tested software stacks for Bluetooth Low Energy for standalone and hosted applications to enable a range of Automotive, IoT and industrial applications. There is also software and hardware support for 2.4 GHz proprietary protocols. To address ranging requirements, the Localization Engine (LCE) is integrated into the system for enhanced localization performance. The KW43 series is supported by the MCUXpresso Developer Experience to optimize, ease and help accelerate embedded system development. Early access program The KW43 is in pre-production, developers can get started today with the KW45/KW47, which is pin and software compatible.   you can request access contacting NXP sales team - Pascal Bernard ([email protected]) Join KW47 early access program here: KW43 Early Access Training Bluetooth Low energy 6.0 NXP Introduction Interested in Bluetooth technology? Bluetooth® Low Energy Primer – Essential reading for understanding BLE fundamentals. Bluetooth® Specifications – Full list of standards, protocols, and technical documents. Awards and Recognition - Every year, the Bluetooth Special Interest Group (SIG) celebrates the hard work and commitment of working groups, committee members, and contributors who have been recognized by their peers as making a difference in advancing Bluetooth technology.  2024: Channel Sounding 2025: Channel sounding amplitude-based attack resilience, LE test mode enhancements and Ranging profile and service.  Bluetooth Feature Overview Bluetooth_5.0_Feature_Overview  Bluetooth_5.1_Feature_Overview  Bluetooth_5.2_Feature_Overview Bluetooth_5.3_Feature_Overview Bluetooth_5.4_Feature_Overview Bluetooth_6_Feature_Overview Bluetooth_6.1_Feature_Overview Bluetooth_6.2_Feature_Overview Bluetooth_6.3_Feature_Overview RF Switch Comparison Absorptive/Reflective Standards Comparison ETSI / FCC / ARIB requirements BLE Channel Sounding  - Overview BLE Channel Sounding - RF Hardware BLE Channel Sounding - ANSYS Modeling Tools  BLE Channel Sounding - Antenna Prototypes Validation Measurements Equipment Wireless Equipment: This article provides the links to the Equipment that helps to the project development  Useful Links How to import and run demo examples with MCUXpresso for Visual Studio Code: This article gives information on how to import and run demo examples from the new SDK with ARM GCC toolchain, in MCUXpresso for Visual Studio Code. [MCUXSDK] How to use GitHub SDK for KW4x, MCXW7x, MCXW2x - NXP Community this community post provides step by step how to use GitHub SDK [MCUXSDK] GitHub SDK - Documentation for Bluetooth LE platforms - NXP Community this community post provides the documentation for BLE platforms.  How to use the HCI_bb on Kinetis family products and get access to the DTM mode:  This article is presenting two parts: How to flash the HCI_bb binary into the Kinetis product. Perform RF measurement using the R&S CMW270 BLE HCI Application to set transmitter/receiver test commands: This article provides the steps to show how user could send serial commands to the device. Bluetooth LE HCI Black Box Quick Start Guide: This article describes a simple process for enabling the user controls the radio through serial commands.

Hello, all, Bellow you can find the necessary steps to enable dual monitor mode on our Wi-Fi chip: 88W9098. This procedure is helpful for using 88W9098's dual interfaces in monitor mode to simultaneously capture Wi-Fi sniffer logs in different band . Below is my test environment: Hardware: I.MX8MQ-EVK M.2 AzureWave PCIe XM458 module Software: Linux kernel version: L6.6.52 (prebuilt image for I.MX8MQ-EVK) Device Tree: imx8mq-evk-pcie1-m2.dtb Wi-Fi/BT Driver & Firmware: Version: PCIE9098--17.92.1.p149.81-MM6X17540.p33-(FP92) Firmware: nxp/pcieuart9098_combo_v1.bin Configuration: Edit wifi_mod_para.conf and add: mon_filter=0x27 max_vir_bss=2 Example configuration: PCIE9098_0 = { cfg80211_wext=0xf max_vir_bss=2 cal_data_cfg=none ps_mode=1 auto_ds=1 host_mlme=1 mon_filter=0x27 fw_name=nxp/pcieuart9098_combo_v1.bin } PCIE9098_1 = { cfg80211_wext=0xf max_vir_bss=2 cal_data_cfg=none ps_mode=1 auto_ds=1 host_mlme=1 mon_filter=0x27 fw_name=nxp/pcieuart9098_combo_v1.bin } Compile tcpdump Compile libpcap: wget https://www.tcpdump.org/release/libpcap-1.10.4.tar.gz tar -xvf libpcap-1.10.4.tar.gz cd libpcap-1.10.4 ./configure --host=arm-linux-gnueabihf --prefix=/opt/tcpdump make Output: libpcap.so.1.10.4 Compile tcpdump: wget https://www.tcpdump.org/release/tcpdump-4.99.4.tar.gz tar -xvf tcpdump-4.99.4.tar.gz cd tcpdump-4.99.4/ ./configure --host=arm-linux-gnueabihf --prefix=/opt/tcpdump --with-pcap=/opt/tcpdump make Output: tcpdump Deploy to Board: Copy libpcap.so.1.10.4 and tcpdump to the board Add execute permission: chmod +x tcpdump Dual Monitor Mode on 88W9098 Load the Wi-Fi drivers and firmware： modprobe moal mod_para=nxp/wifi_mod_para.conf Monitor Interface Setup 5 GHz (mlan0): iw mlan0 interface add mon0 type monitor ip link set mon0 up ip link set mlan0 down iw mon0 set channel 36 ./tcpdump -i mon0 -w capture_5g.pcap & ./tcpdump -r capture_5g.pcap 2.4 GHz (mmlan0): iw mmlan0 interface add mon1 type monitor ip link set mon1 up ip link set mmlan0 down iw mon1 set channel 6 ./tcpdump -i mon1 -w capture_2g.pcap & ./tcpdump -r capture_2g.pcap Simultaneous Capture ./tcpdump -i mon0 -w capture_5g.pcap & ./tcpdump -i mon1 -w capture_2g.pcap & Stop Capture killall tcpdump Read Captures ./tcpdump -r capture_5g.pcap ./tcpdump -r capture_2g.pcap Reference link: https://docs.nxp.com/bundle/RM00297/page/connectivity-features/topics/monitor_mode.html   Best regards, Christine.

In daily work, many customers are asking how to develop Mifare Desfire EV3. Yes, it is true that the Mifare Desfire EV3 is a highly secure product, and the related application documents are complicated and difficult for customers to use or take too much time to research, so I want to share them with you.

This article shares 2 step by step methods to create P2P connections between 2 IW612 modules. One is not setting pin code, another is setting pin code. And also shares local test results and printed logs for your reference. The basic environment: Hardware: 2 IW612 modules(Murata LBES5PL2EL) + I.MX93-EVK Software: Linux 6.12.20 Wi-Fi Driver and FW version = SDIW612---w9177o-V1, SDIO, FP99, 18.99.3.p25.7-MM6X18537.p9-GPL-(FP92) As a reference, you can also test on other NXP's Wi-Fi products based on Linux OS.   Best regards, Christine.