Overview The Sensorless High-Speed SR Motor Control Reference Design based on the NXP® low-cost MC56F8013 digital signal controller (DSC) deals with a 2-phase switch reluctance (SR) motor sensorless drive for vacuum cleaners and other air movement applications. The application is a speed-open loop SR drive without any position or speed sensor needs Uses a sensorless control method based on current peak detection and a patented start-up algorithm (Patent No. US6448736 B1) The control technique allows the SR motor more than 100 000 RPM The application is primarily for vacuum cleaners, although it can be used for any application with a high-speed drive (50 000 RPM) Features High-speed 2-phase SR motor sensorless control based on a current peak detection Designed for vacuum cleaner applications Capable of running SR motors at more than 100.000 RPM (tested with SR motor designed for 60 000 RPM) Single direction rotation enabled by asymmetric of 2-phase SR motor Speed open loop Start-up from any position using alignment and patented algorithm (Patent No. US6448736 B1) Start-up time and maximum speed depends on SR motor parameters Manual interface and FreeMASTER control page for monitoring, control and tuning Block Diagram Design Resources

This post entry provides a detailed description of how a Bluetooth Low Energy (BLE) pairing solution via NFC was developed using two of our reference development boards: The NTAG I 2 C plus kit for Arduino pinout The Freedom KW41Z board. This document has been structured as follows: NFC for easy one-tap pairing solution NFC pairing is one popular feature you can find in cameras, speakers, printer, routers, wearables and many more. Just bringing two NFC-enabled devices close together is all it takes to create a connection. Just to mention a few of examples, with just a swipe you can: Connect your phone to a wireless speaker. Connect your new devices to the home network. Connect accessories to the control unit. In all these scenarios… NFC and Bluetooth are a perfect combination, since the pairing process with NFC becomes: Faster compared to the traditional pairing methods. Easier, reducing technical support More reliable, making sure you connect to the right device. The technical basis for this “tap to connect” process is provided in the NFC Connection Handover specification running atop the NFC Forum protocol stack. It defines a framework of messages and data containers that allow bootstrapping of alternative (i.e., other than NFC) carrier connections in a standardized way. For this reason, NFC pairing solution offers a unified user experience and interoperability across different manufacturers.  NFC solutions to implement secure simple pairing There are two types of solutions recommended to add NFC pairing functionality to designs: NFC static pairing with NTAG 213 The first solution is embedding an NTAG 213 NFC label. In such a case, the pairing credentials need to be previously loaded in to the tag memory as well as in the device MCU during manufacturing. NFC dynamic pairing with NTAG I2C plus The second solution is embedding an NTAG I 2 C plus tag. In such a case, the pairing credentials can be dynamically updated by the device MCU during the product lifetime. In addition, other features such as an automatic wake-up field detection signal are possible. Precisely, the combination of a passive NFC interface with a contact I2C interface allows the product to behave as a tag and be read via NFC and to connect to a host or application processor via  I 2 C. In addition, NDEF messages can be generated and updated by the host MCU depending on the application requirements. Later, these NDEF messages can be read by any NFC phone, including iOS devices with the latest OS version. Hardware setup Mapping the previous diagram to the demo hardware, we have: The NTAG I 2 C plus tag, using the Arduino pinout kit The MCU, using Kinetis KW41Z. The applicatiob logic, which updates the NDEF contents based on different use cases. Some details about the hardware used in the next sections: Kinetis KW41Z The Kinetis KW41Z is a high integrated chip with multi-protocol radio features enabling Bluetooth Low Energy (BLE) and 802.15.4 radio protocols such as Thread. KW41Z has as large memory of 512KB that can support multiple radio protocols running in a single application instace and implements nine low-power modes and a wide operating voltage range (0.9V/4.2V), for optimum current consumption. Finally, the software support package includes: BLE, Thread and 802.15.4 generic network stacks, several sample demo apps, support for RTOS and full integration in MCUXpresso. The Kinetis KW41Z evaluation is supported with the FRDM-KW41Z development board. The board main components are: a reference crystal, an accelerometer, an Arduino header, some LEDs and buttons, a JTAG and OpenSDA connectors,and an external flash memory. NTAG I2C plus kit for Arduino pinout The NTAG I 2 C plus Arduino kit consist of two PCBs stacked together: The upper PCB is the antenna board with the connected tag The lower PCB is an interface adaptor board to the Arduino pinout. This kit can be used to connect and evaluate the NTAG I 2 C plus  into many popular MCUs with Arduino compliant headers, for example:  Kinetis (e.g. KW41Z, i.MX (e.g. UDOO Neo, i.MX 6UL, i.MX 6 ULL, i.MX 7D) and LPC MCUs (e.g. LPCXpresso MAX, V2 and V3 boards). The kit support package includes several software examples, including the BT pairing example based on KW41Z.  The OM29110ARD is a generic interface board which offers support for connection to any PCB implementing Arduino connectors. It exposes: 3.3V and 5V power supply pins. I 2 C , SPI and UART host interfaces. Generic GPIOs (e.g. to be used for field detect, interrupts, reset pins or others) As such, it allows the NTAG I 2 C plus to be plugged into Arduino devices seamlessly. Once the NTAG I 2 C plus  board is stacked on the KW41Z, the pining routing between the two boards is as follows. It uses:  The  I 2 C  interface pins. The 3.3V supply pin. One GPIO is routed for the field detection pin. The Vout, for the energy harvesting pin. The ground reference. BLE pairing with NFC on KW41Z and NTAG I2C plus This section details how the Bluetooth Low Energy (BLE) pairing with NFC on KW41Z and NTAG I 2 C plus works. The following block diagram is a simplified representation of the demo that shows: The Bluetooth and NFC interfaces The buttons and LEDs involved in the process. Starting BLE advertising After SW4 is pressed: The application goes from IDLE to searching mode, advertising the BLE device The LED 3 starts blinking in RED color. Writing BLE pairing NDEF message Once the BLE advertising is activated, the next step is for the KW41 to write the pairing message into the NTAG I 2 C  plus memory. After SW3 is pressed: The KW41 uses the  I 2 C interface with the NTAG I 2 C plus to load a pre-defined NDEF message with the BLE pairing details. At the same time, the LED 4 is set to GREEN. Pairing with the BLE device While the LED 4 is set to green, the BLE pairing message is exposed through the NTAG I 2 C plus  RF interface. During this interval, any NFC-enabled device: Can read out the NDEF pairing message. Pass the BT credentials to the Android system or the host processor. And automatically create a Bluetooth link according to the exchanged network credentials. In case of an Android system, no third-party implementation is needed on this part as long as the pairing message follows the NFC Forum specifications. Writing default NDEF message Once the pairing information is read out of the NTAG I²C plus, the KW41Z removes the pairing content and turns back to normal operation mode. In addition, in this specific demo, the NDEF pairing message is programmed to remain in the NTAG I²C plus memory for only ten seconds. After these 10 seconds: The green LED is switched off. And the pairing NDEF message is overwritten by the default NDEF about the NTAG I²C plus demo app. Video The following video shows how the Bluetooth Low Energy (BLE) pairing with NFC on KW41Z and NTAG I 2 C plus works. How to integrate NTAG I2C plus into FRDM-KW41Z hid_device sample project In this section, we describe, step by step, how NFC is integrated in an existing default demo application taken from the KW41Z support package.   FRDM-KW41Z startup In the board website, there are very clear instructions on how to get started www.nxp.com/demoboard/FRDM-KW41Z. For instance: How to test KW41Z. How to get the tools, in our case: MCUXpresso, and the SDK for KW41Z. How to import, build and runn the examples included in the SDK for KW41Z, in our case: the ones inside the wireless_examples folder Importing FRDM-KW41Z SDK and hid_device sample project After that, we import the FRDM-KW41Z SDK and we import the sample project used as a basis for adding NTAG I 2 C plus support, this is the hid_device example located under the wireless/Bluetooth folder. Importing NTAG I2C plus middelware The NTAG I 2 C plus  middleware can be easily imported as a new folder in the project tree using the MCUXpresso File / Import menu. Once imported, the internal structure of the middleware should have this structure: HAL_I2C: The HAL_I2C files support access to the Kinetis I 2 C interface. HAL_ISR:  The HAL_ISR files support the interrupt handling and callback registration for the Kinetis MCU. HAL_NTAG: The HAL_NTAG source files provide an API that allow you to communicate with the NTAG chip and implements the NTAG command set to perform memory access operations from the I 2 C interface.  For instance, this API can be used to perform: Read / Write memory operations on EEPROM and SRAM (for example, to read data, you just need to indicate the memory address and length of the data to be read) Read / Write access to NTAG I 2 C plus registers (for example, you just need to indicate the register macro to be read). Functions for enabling the pass-through mode and handling the data exchange between interfaces (setting the data transfer direction is as easy as using this function). HAL_TMR: The HAL_TMR files support access to the timing hardware of the Kinetis MCU. Adding / changing GPIO pin settings All pin and GPIO settings are defined within the pin_mux.c file. For our application, the I 2 C pins need and a GPIO for the field detection need to be enabled.  Regarding the host interface: the I 2 C  pins for NTAG communication are configured using the BOARD_InitI2C() function, it sets the required I 2 C  port (port 0 for this MC) and set the right mode for the clock (SCL) and data (SDA) lines. Regarding the field detection: it is defined within the source code even though it is not used so far. It is left defined for future use. Within the pin_mux.c file, there are other functions which initialize; for instance, the buttons, LEDs, etc. These functions are called during the hardware initialization. NTAG I2C plus software and hardware initialization We move to the main_application, where some pieces of code need to be added. All code that has been added, is inside the #ifdef NTAG_I2C clause. First, we added: The I 2 C_driver and the ntag_app header files . The ntag_handle handler declaration. Then, the HW initialization is performed calling I2C_initDevice and the NFC_Initdevice() function is called to fill the  ntag_handle software handler. HID_device demo extensions The BLE demo application is written in the hid_device.c file and the whole behavior is handled in this file. The C-code printout in the blue box  below shows the content of the BleApp_HandleKeys() function, which handles the BLE activity and the changes made related to the NFC use case. Similarly, all new code additions are within the #ifdef NTAG_I2C clause. Mainly, the BleApp_HandleKeys() function function was extended to: Copy the pairing NDEF message to the NTAG I 2 C plus chip when the button SW3 is pressed. Set the LED 3 to green while the pairing NDEF message is available. Start a timer counter from the moment the SW3 button is pressed In addition, when the time counter is expired (expiration was defined to 10 seconds): The memory content of the NTAG I 2 C plus chip is overwritten by default NDEF message. The LED 3 is set to off. NDEF message for BLE pairing definition The last part missing to cover the NFC integration into the KW41Z refers to the files created within the application to declare the NDEF pairing and NDEF messages. The NFC Data Exchange Format (NDEF) is the NFC Forum specification defining an interoperable, common data format for information stored in NFC tags and NFC devices. The spec also details how to enable tags to deliver instructions to an NFC device so that the device will perform a specific action when a particular tag is read (open a browser, initiate a phone call, pairing, etc.). Every NDEF message can be automatically processed by any NFC device and execute the appropriate action without requiring the installation of any customized software / application and independently of the hardware manufacturer. There are several NDEF record formats that you can use in your implementation. Each NDEF record indicates to the application processor which kind of payload the message carries. In our demo app, the default NDEF message used belongs to a smart poster record and the NDEF pairing message, follows the protocol defined in the NFC Forum connection handover specification. Going to the source code, two application files for the NDEF handling were created: The app_ntag.h declares the two NDEF messages used in this demo. The app_ntag.c, implements a function which writes the NDEF message into the tag. As mentioned, the NDEF used for this BLE pairing was built according to the Connection Handover and BT secure simple pairing specifications and rules. On the image below, we copied the declaration of the NDEF pairing message. This is actually the hex bytes that are written into the tag memory. To highlight son relevant parts: We find the capability container and the NDEF TLV. These two fields are used by the NFC device to detect if the tag is loaded with NDEF formatted data into a Type 2 tag (like the NTAG I 2 C plus). After that, we find the record type name. This is the MIME type for the Bluetooth out of band pairing (written in its ASCII representation). It is followed by the device Bluetooth MAC address, and the complete local name (Freescale HID). The terminator TLV In case you are interested to know more about the NDEF message structure, you can check the NFC Forum specifications The data (MAC address 00:04:9F:00:00:04 & device name FSL_HID) read by the NFC device is sent to the Bluetooth controller to establish the Bluetooth connection. Default NDEF message definition  The NDEF used as thedefault_ndef message consist of two records: The first record was built according to the SmartPoster specification from the NFC Forum, which describe how to store a plain message followed by an URL. The second record is what is called Android Application record. On the image below, we copied the declaration of the NDEF default message. To highlight son relevant parts:   As the NDEF BLE message, the first data fields we find correspond to the container and the NDEF TLV structure for a Type 2 Tag. Then, we find the smart poster record, which includes a text field. In this example, it codes the text “NTAG I2C Explorer”  and a URI field which codes a the NTAG Explorer kit website URL. After that, we find the Android application record, which is used to automatically launch the app  or, if the app is not installed, redirect the user to Google Play. Finally, the terminator TLV. After 10 seconds, the application removes the BLE pairing NDEF and replaces it by the above described NDEF message. This can be easily demonstrated by tapping the phone after these 2 seconds, and validate that the NTAG I 2 C plus demo is automatically opened. Video recorded session   Available resources BLE pairing with NFC on KW41 and NTAG I 2 C plus source code www.nxp.com/downloads/en/snippets-boot-code-headers-monitors/SW4223.zip NTAG I 2 C plus kit for Arduino pinout www.nxp.com/demoboard/OM23221ARD FRDM-KW41Z board www.nxp.com/demoboard/FRDM-KW41Z

Overview This reference design shows the simplicity of a soft modem design, how few resources of the processor it takes, and how well it performs on USA average lines. This design omits the standard telecommunications Codec, instead of using PWM for output and ADC for input. Since both peripherals are readily available on one 56F8300/100 series device, along with more processing power than required from the single core, the design is a true one-chip, one-core system that includes telecommunications ability with room for even more system functionality. Ideal for advanced motion control, home appliances, medical monitoring, fire and security systems, power management, smart relays, and POS terminals. Features Hybrid architecture facilitates implementation of V.21 and V.22bis modem, control, and signal processing functions in one chip Consumes only 7.5 MIPS for the modem function - Only 15K words of Flash for the complete modem application and test harness High-performance, secured Flash memory eliminates the need for external storage devices Extended temperature range allows for operation of non-volatile memory in harsh environments Flash memory emulation of EEPROM eliminates the need for external non-volatile memory 32-bit performance with 16-bit code density On-chip voltage regulator and power management reduces overall system cost Off-chip memory expansion capabilities allow for glueless interfacing with the additional memory of external devices, without sacrificing performance Boots directly from Flash, providing additional application flexibility High-performance PWM with programmable fault capability simplifies design and promotes compliance with safety regulations PWM and ADC modules are tightly coupled to reduce processing overhead; only one of each is used by the modem General purpose input/output (GPIO) pins support application-specific needs Simple in-application Flash memory programming via Enhanced OnCE or serial communication Block Diagram Board Design Resources

This doc expain how to use eMMC from user space, contents as follows: 目录 1 eMMC的分区情况 ...................................................... 2 2 S32G+BSP29上默认的eMMC启动 ............................ 3 2.1 eMMC硬件设计 .................................................. 3 2.2 eMMC的镜像烧写办法与启动 ............................. 6 2.3 增加MMC内核测试工具 .................................... 10 3 eMMC GP功能的测试 .............................................. 10 3.1 eMMC GP功能的说明 ....................................... 10 3.2 eMMC GP功能的测试 ....................................... 11 4 eMMC RPMB功能的测试 ......................................... 13 4.1 eMMC RPMB功能的说明 ................................. 13 4.2 eMMC RPMB功能的测试 ................................. 15

Explore the MC34937, an industrial-grade 3-phase gate pre-driver for BLDC and PMSM motor control. The MC34937 can support 12V, 24V, and 36V motor control applications and easily interfaces to standard MCUs and DSPs. The demo shows the implementation of the MC34937 with Kinetis Microcontrollers E in a 36V battery-operated electric bike (eBike) application. This same system can be modified to be used in other industrial applications such as electric garden tools, industrial fans and pumps, and electric wheelchairs. Features Demo shows capability of Kinetis KE02 connecting to an MC34937 Motor Driver MC34937 able to drive 12V, 24V, 36V, 48V systems Featured NXP Products Kinetis E - KE02Z64 MC34937 3-phase gate pre-driver Block Diagram MC34937 Schematics and Software:

IEEE 1588协议简单理解        IEEE 1588 是一个精密时间协议 (PTP)，用于同步计算机网络中的时钟。 在局域网中，它能将时钟精确度控制在亚微秒范围内，使其适于测量和控制系统。 IEEE 1588 标准为时钟分配定义了一个主从式架构，由一个或多个网段及一个或多个时钟组成。 ​       TSN 网络中时间同步协议使用 IEEE 802.1AS 协议，它基于 IEEE 1588 协议进行精简和修改，也称为 gPTP 协议。 ​       IEEE 1588 协议简称精确时钟协议 PTP（Precision Timing Protocol），它的全称是“网络测量和控制系统的精密时钟同步协议标准”（IEEE 1588 Precision Clock Synchronization Protocol）。其工作的基本原理，是通过主从节点之间进行同步数据帧的发送，记录数据帧的发送时间和接收时间信息进行，并且将该时间信息添加到该数据帧中。从节点获取这些时间信息，并计算从节点本地时钟与主时钟的时间偏差和网络节点之间的传输延时，对本地时钟进行纠正，使之与主节点时钟同步。一个 PTP 网络只能存在一个主时钟。 ​ PTP 协议主要分为两大部分来实现时钟同步功能： ​ 1、建立同步体系： ​       协议使用最佳主时钟算法（Best Master Clock Algorithm，BMCA），通过选取主时钟，建立主从拓扑关系，进而在整个 PTP 网络中建立起同步体系。 ​ 2、同步本地时钟： ​       协议使用本地时钟同步算法（Local Clock Synchronization Algorithm，LCS），通过 PTP 数据报文在网络主从节点之间的交换，计算各从节点本地时钟与主时钟间的时间偏差，调整本地时钟，使之与主时钟同步。 IEEE 1588v1 ​       整个 PTP 网络内的时钟可按照其上 PTP 通信端口的数目来划分成普通时钟（Ordinary Clock，OC）与边界时钟（Boundary Clock，BC）：普通时钟只存在一个，而边界时钟则存在多个。一般在确定性不高的网络节点处使用边界时钟，例如交换机或者路由器一般用作边界时钟，如下图所示。在每个端口上，PTP 通信都是独立进行的。 1、边界时钟： ​      边界时钟上只允许存在一个从端口，与上级节点的主端口通信，将其本地时钟与级主端口进行同步。其余端口为主端口，与下游节点的从端口进行通信。边界时钟可以连接不同的网络协议。 ​ 2、同步体系建立流程： ​   （1）初始状态，各个节点端口会在指定的时间内侦听网络中的 Sync 数据帧； 若接收到 Sync 数据帧，节点端口将根据最佳主时钟算法决定端口状态。若没有收到 Sync 数据帧，该节点状态变更为 Pre_Master，并将自己假定为主时钟节点。此时节点端口状态表现为主时钟，但是并不发送 Sync 帧。 ​   （2）端口状态在一定时间内保持 Pre_Master： 若在端口指定时间内接收到 Sync 数据帧，则该端口状态由最佳主时钟算法决定。 若判定端口为主时钟，则将周期性地发送 Sync 帧；若判定为从时钟，则接受 Sync 帧，并计算偏差，纠正本地时钟。 ​ 若在该时间段内端口没有收到 Sync 数据帧，则将状态变更为主时钟，并且开始定时发送 Sync 数据帧。 ​   （3）主时钟和从时钟的状态随着时钟性能与运行状态的变化而变化。下图展示了 BMCA 中状态转移。 3、时间同步建立流程： ​ 如下图PTP同步原理         如图所示，Master为网路中的同步时钟源，可以认为其与UTC或者GPS时无限接近。Slave为网络中需要被同步设备。假设从Master到Slave的路径符合对称路径，那么路径上的延时我们设Delay，然后设备Master和设备Slave之间待同步的时间差值为Offset，即Slave比Master在同一时刻慢Offset。         Slave设备根据算出的Offset即可以进行本地时钟校准。但是1588V1协议依赖于链路的对称性，即Master到Slave与Slave到Master时延一致，这在实际网络状况下很难满足，故需要额外的不对称算法进行链路延时差计算和补偿校准。   IEEE 1588v2 ​IEEE1588V2在IEEE1588V1版本上做了改进和扩展。主要包括： ​ 1.新增点到点路径延时测量的独立消息模式。 端口 A 与端口 B 间的路径延迟时间 Delay 为： ​        在 PTPv1 中，平均路径延迟测量时通过 Sync 帧与 Delay_Req 帧配合使用的，但是在 PTPv2 中却不需要 Sync 帧的参与，仅通过 PDelay_Req 数据帧系列来进行测量。这是一个独立的延迟测量过程，不依赖 Sync 帧和同步体系建立的参与，使得测量精度有所提高，并且可以经过多次测量求得平均值得到更为准确的路径延迟。另一方面，如果网络中的同步体系发生改变，这时不需要重新计算该节点间的路径延迟，直接使用之前已测得的延迟数据，大大增强了协议执行的效率，使得协议更为方便灵活。在PTPv2 中，利用 PDelay_req 数据帧系列已成为主要的测量路径延迟方法。 ​ 2、新增透明时钟模型 ​        在 PTPv1 中，网络中间节点均采用边界时钟模型。与网络中唯一的主时钟，即一个普通时钟连接的边界时钟，其上唯一的从端口接收主节点发送的同步数据帧，与主时钟实现同步，其余的主端口和与之相连的其他边界时钟发送同步数据帧，最后同步到网络边缘的普通时钟，这样便实现了整个网络的时间同步。这种方法虽然可行，但是由于这种方式是逐级同步，所以距离主时钟越远的节点，同步精度越低。 ​        当网络中的一些节点不需要进行时钟同步或者不具备同步功能时，便可采用透明时钟模型。透明时钟不像 BC/OC 模式那样，需要每个节点都与主时钟进行同步，它的端口只对协议数据帧进行转发，并将计算出的数据帧滞留时间添加在校正域中。这种方式将 PTP 数据帧的处理变得更为简单，降低了网络中 PTP 协议的实施难度，同时提高了各从节点的同步精度。 ​ 透明时钟有模型两种：端对端透明时钟，和点对点透明时钟。 ​     （1）端对端（E2E）透明时钟 ​ E2E 透明时钟对网络中普通数据帧不做任何处理，仅进行转达让其正常通过。但是对于 PTP 事件数据帧，则将他们从接收端口到发送端口间的驻留延迟时间累加到数据帧中的修正域，用以弥补 PTP 数据帧在经过其自身所带来的延迟误差。 ​     （2）点对点（P2P）透明时钟 ​ 点对点（P2P）透明时钟只转发特定的 PTP 报文，包括 Sync 帧、Follo_Up 帧和Announce 帧等。并且会采用 Pdelay_Req 数据帧系列计算每个端口与所连接的端口间的路径延迟时间，再与端口间延迟时间合并添加到时间修正域，来补偿数据帧从源端口到点对点透明时钟出端口的时间延迟。 ​ 3、增加单步时钟模型 ​        单步时钟模型解决了 Follow_Up 帧与 Sync 帧匹配问题。PTP 协议基本的同步过程采用双步模式，即主时钟节点发送 Sync 帧，和带有 Sync 帧发送时间的Follow_Up帧。这种方式虽然能提高 Sync 帧时间戳标记的精度，提高同步效果，但是在网络负载较大的情况下，数据帧很有可能发生丢失或者阻塞，造成两种数据帧的匹配出现差错。 ​        在 PTP 数据帧中设置一个标志，来使用单步模式，将 Sync 帧的发送时间与数据帧中的时间标签的差值作为传输延迟，并将其累加到修正域中。这样主时钟便通过单独的 Sync 帧而不需要 Follow_Up 进行时间的同步校准工作。 ​        单步模式可以减少网络流量，提高网络负载较大时同步的可靠性。单步模式需要额外的辅助硬件，来帮助计算时间修正值并将其累加到校正域中，这对网络的实时性有比较高的要求。 BMCA ​        BMCA，即最佳主时钟算法，它选择网络中性能最佳的时钟作为主时钟，并以 此建立网络拓扑，生成同步体系，进而实现时钟同步功能。 ​        最佳主时钟的选取是通过Announce帧在网络中各节点的传输，比较各个节点上的时钟属性（比如是否将时钟指定为主或者从时钟），用于标识精度的时钟等级，以及用于标识时钟源类型的时钟类型（比如铷钟、铯钟等），还有表示时钟偏移、方差等的时钟特性、时钟地址以及时钟端口号等特征来选择最佳主时钟，当其他时钟特征都一样是，协议会将端口号最小的节点时钟作为主时钟。IEEE 1588协议会以主时钟节点作为根节点形成树形拓扑结构，并且为避免生成回路，那些竞争失败的节点端口，协议将他们定义为被动或者禁用状态。

Overview This reference design demonstrates speed control of the 3-Phase Switched Reluctance (SR) motor with Hall position sensor using the NXP® 56F80x or 56F83XX Digital Signal Controllers (DSCs). It helps start development of the SR drive dedicated to the targeted application The DSC runs main control algorithm; when the start command is accepted, the state of the Hall sensors position signals is sensed and the individual motor phases are powered in order to start the motor in the requested direction of rotation without rotor alignment According to the determined switching pattern and the calculated duty cycle, the on-chip PWM module generates the PWM signals for the SR motor power stage Features Speed Control of an SR motor with position Hall sensors Targeted 56F80X, 56F83XX, and 56F81XX Digital Signal Controllers Running on a 3-Phase SR HV Motor Control Development Platform (115/230VAC) Running on a 3-phase SR LV Motor Control Development Platform (12V DC) The control technique: voltage control with a speed closed loop Hall sensors position reference for commutation Start from any motor position without rotor alignment Manual interface FreeMASTER software control interface and monitor Fault protection Block Diagram Board Design Resources

Combining NXP's wireless MCU with NFC controller allows to build a BLE-NFC bridge. It allows demonstrating transmission of NFC data over BLE, acting then as a king of Magic NFC remote. This demonstrator is built assembling the OM5578: Development Kits for PN7150 Plug’n Play NFC Controller (OM5578/PN7150ARD version including Arduino compatible connectors). on top of the FRDM-KW41Z: Freedom Development Kit for Kinetis ® KW41Z/31Z/21Z MCUs (minimum version B1 since previous versions have a pin conflict on the Arduino connector) Alternatively the Rigado R41Z Eval Board can be used as replacement to the FRDM-KW41Z To complete the demonstration, an android phone is used as BLE counterpart. It shall run the modified version of Kinetis BLE Toolbox android application including the NFC demo part. This dedicated version of the Kinetis BLE Toolbox android application is available for download from the files attached to this document. Below is a video of the demo. As shown, it demonstrate capabilities to control the NFC discovery remotely (via BLE) from the phone. Then, if tapping a card on the bridge, the related information including the content is conveyed through BLE to the phone and get displayed by the app. Additionally, the app can configure a message to be shared whenever an NFC reader (e.g. NFC phone) tap the bridge. The K41Z firmware of this demo is built based on the wireless UART example from MCUXpresso Software Development Kit (SDK), and updated with the porting of the NXP-NCI MCUXpresso example. The complete MCUXpresso project is given in source code in the attached files. To replicate the demo, just import it in an MCUXpresso workspace by selecting "Existing Projects into Workspace", then browsing to the BLE-NFC_bridge_MCUXpressoProject.zip file. Select the frdmkw41z_BLE-NFC_bridge from the "Project Explorer" view, and click on the blue bug icon to build, flash and debug the program.

This doc explain how to configure a new LPDDR4 and test it on S32G, contents as follows: 目录 1    硬件资源，文档及工具下载... 2 1.1    硬件资源... 2 1.2    内存配置测试相关的文档... 2 1.3    内存配置与压力测试工具. 3 2    内存设计要求... 3 3    LPDDR4基础... 3 3.1    基本知识... 3 3.2    Inline ECC.. 4 4    硬件连接... 6 5    S32G+LPDDR4内存配置与测试步骤... 8 5.1    配置LPDDR4初始化寄存器设置... 9 5.2    使用内存测试工具初始化PHY及生成DDRC配置Uboot源代码    11 5.3    生成DDRC配置ATF源代码(从BSP32开始) 14 5.4    测试内存... 18 5.5    其它尺寸的LPDDR4配置... 19 6    测试失败的DEBUG.. 24 7    内存参数应用到Uboot中... 25 8    内存参数应用到ATF中... 25 9    附录... 25 9.1    一个重要的DDR TOOL bug Fix. 25 9.2    Uboot DDR测试工具... 26 9.3    Kernel DDR测试工具... 27 9.4    附DDR tool测试项截图... 28   Contents 1    Hardware Materials, Docs and Tools Needed. 2 1.1    Hardware resource. 2 1.2    Related docs of memory configuration and test 2 1.3    Memory configuration and test tools. 3 2    Memory Hardware Design Requirement 3 3    LPDDR4 Basics. 3 3.1    Basic Knowledge. 3 3.2    Inline ECC.. 5 4    Hardware Design. 7 5    S32G+LPDDR4 Memory Configuration and Test Steps. 8 5.1    Configure LPDDR4 DDRC Register Settings. 9 5.2    Use the Memory Test Tool to Initialize the PHY and Generate the DDRC Configuration Uboot Source Code  12 5.3    Generate ddrc configuration ATF source code (starting from bsp32) 15 5.4    Memory Test 19 5.5    Other size LPDDR4 configurations. 20 6    Debug of the Fails of Test 25 7    Modify the DDRC register settings in Uboot 26 8    Modify the DDRC register settings in ATF. 26 9    Appendix. 26 9.1    A importance DDR TOOL bug Fix. 26 9.2    Uboot DDR Test Tools. 27 9.3    Kernel DDR Test Tool 28 9.4    Attached Screenshot of DDR Tool Test Items. 29

Overview NXP ®  offers solutions for the growing unmanned vehicle market in both civil and defense designs, supporting functions such as control, motion, vision, navigation, and communication. Target applications include: Unmanned Aerial Vehicle Unmanned Ground Vehicle Unmanned Underwater Vehicle Construction, demolition, inspection, or mining robot Firefighting or rescue robot Reference Designs NXP Product Link PX4 Robotic Drone FMU https://www.nxp.com/design/designs/px4-robotic-drone-fmu-rddrone-fmuk66:RDDRONE-FMUK66  KV Series Quad Motor Control https://www.nxp.com/design/designs/kv-series-quad-motor-control:KINETIS-DRONE-REFERENCE-DESIGN Block Diagram Recommended Products NXP Product Link MCU Kinetis® V Series: Real-time Motor Control & Power Conversion MCUs based on Arm® Cortex®-M0+/M4/M7 | NXP  LPC54000|Power Efficient 32-bit Microcontrollers (MCUs)|Cortex®-M4 Core | NXP  i.MX RT1060 MCU/Applications Crossover MCU | Arm® Cortex®-M7, 1MB SRAM | NXP  i.MX 6Solo Applications Processors | Single Arm® Cortex®-A9 @ 1GHz | NXP  i.MX 6Dual Applications Processors | Dual Arm® Cortex®-A9 @1.2GHz | NXP  i.MX 6Quad Applications Processors | Quad Arm® Cortex®-A9 | NXP  Wireless Connectivity Bluetooth®Smart/Bluetooth Low Energy | NXP  Interfaces In-Vehicle Network | NXP  I²C, SPI, Serial Interface Devices | NXP  USB Interfaces | NXP  NFC Reader NFC Readers | NXP  Wireless Power Wireless Power | NXP  Motor Driver GD3000 |3-phase Brushless Motor Pre-Driver | NXP  Voltage Regulator Linear Voltage Regulators | NXP  Switch Detector Signal Conditioners | NXP  Sensors Sensors | NXP  Tools and Software NXP Product Link i.MX RT1060 Evaluation Kit i.MX RT1060 Evaluation Kit | NXP  i.MX RT1020 Evaluation Kit i.MX RT1020 Evaluation Kit | NXP  SABRE Board for Smart Devices Based on the i.MX 6Quad Applications Processors i.MX 6Quad SABRE Development Board | NXP  i.MX RT1064 Evaluation Kit i.MX RT1064 Evaluation Kit | NXP  Kinetis® KV3x TWR-KV31F120M|Tower System Board|Kinetis® MCUs | NXP  i.MX RT1015 i.MX RT1015 Evaluation Kit | NXP  3-Phase Motor Control Low-Voltage, 3-Phase Motor Control Tower System Module | NXP  i.MX RT1050 Evaluation Kit i.MX RT1050 Evaluation Kit | NXP  NXP HoverGames drone kit including RDDRONE-FMUK66 and peripherals KIT-HGDRONEK66: NXP drone kit | NXP  Kinetis KV4x TWR-KV46F150M|Tower System Board|Kinetis MCUs | NXP  BSP, Drivers, and Middleware NXP Product Link Android OS for i.MX Applications Processors Android OS for i.MX Applications Processors | NXP  Embedded Linux for i.MX Applications Processors Embedded Linux for i.MX Applications Processors | NXP  MCUXpresso Software Development Kit (SDK) MCUXpresso SDK | Software Development for Kinetis, LPC, and i.MX MCUs | NXP  MCUXpresso Config Tools - Pins, Clocks, Peripherals MCUXpresso Config Tools|Software Development for NXP Microcontrollers (MCUs) | NXP 

Overview This drive application allows vector control of an AC Induction Motor (ACIM) running in a closed-speed loop without a speed/position sensor at a low cost and serves as an example of AC induction vector control drive design using an NXP ®  56F8013 with Processor Expert ®  software support. ACIM is ideal for appliance and industrial applications This design uses sensorless FOC to control an ACIM using the 56F8013 device, which can accommodate the sensorless FOC algorithm The motor control system is flexible enough to implement complex motion protocols while it drives a variable load. The system illustrates the features of the 56F8013 in motor control Features General: The motor control algorithm employs Stator-Flux-Oriented Control (SFOC) Power stage switches are controlled by Space Vector Pulse Width Modulation (SVPWM) No position information devices or stator flux measurement are used, a sensorless speed method is employed The motor is capable of forward and reverse rotation and has a speed range from 50rpm to 3000rpm The user controls motion profiles, rotation direction, and speed. The RS-232 communication supports further R&D by enabling the easy tuning of control parameters The motor drive system is designed to create minimal acoustic noise Active power factor correction which reduces the negative effects of the load on the power grid in conducted noise and imaginary power Design is low cost General Benefits: Improved End System Performance Energy savings Quieter operation Improved EMI performance System Cost savings Enhanced Reliability Performance: Input voltage: 85 ~265VAC Input frequency: 45 ~65HZ Rating bus voltage: 350V Rating output power: 500W Switch frequency of PFC switch: 100KHZ Switch frequency of inverter: 10KHZ Power factor: >95% Efficiency: >90% Communications: RS232 port for communication with optoisolation Visual Interface: Multi-segment LED indicators Block Diagram Board Design Resources

Speed development time when designing your portable medical device with NXP's Healthcare Analog Front End (AFE) reference platform which includes a complete hardware platform, schematics and software.  Based on the Kinetis Microcontroller K53 measurement. Demo Owner: dr.josefernandezv Demo Owner: aleguzman Features Speed development time when designing your portable medical device with NXP's Healthcare Analog Front End (AFE) reference platform which includes a complete hardware platform, schematics and software NXP offers a complete development platform based on the Tower System, which eases the development of medical applications with a fully integrated set of solutions that reduces the design effort The Medical suitcase is composed of six different analog front ends, each one focused on a specific medical application. Applications included are, 1-Lead ECG, pulse oximeter, blood pressure monitor, glucometer, spirometer, and ultrasound digital stethoscope Featured NXP Products K50_100: Kinetis K50 Measurement 100 MHz MCUs Healthcare Analog Front End( AFE) Block Diagram

Overview This reference design of a 3-phase Permanent Magnet Synchronous Motor (PMSM) sensorless vector control drive and a Brushless DC (BLDC) Motor drive without position encoder coupled to the motor shaft uses the NXP® 56F8013 with Processor Expert® software support. PMSM/BLDC motor are excellent choices for many appliances and industrial applications that require low cost and high-performance variable speed operation This design will employ sensorless FOC to control a PMSM and a sensorless algorithm to control BLDC The hardware design supports both motor types with the algorithms fully implemented digitally via software running on the 56F8013 DSC Features General: For PMSM the motor control algorithm employs Field-Oriented Control (FOC). The power stage switches are controlled by means of Space Vector Pulse Width Modulation (SVPWM) The feedback hardware elements are limited to the motor stator phase currents and the bus voltage. No position information devices or stator flux measurement are used; sensorless speed methods are employed The Motor is capable of forward and reverse rotation and has a speed range of 500rpm to 6000rpm The user controls motion profiles, rotation direction, and speed. The RS-232 communication supports further R&D by enabling the easy tuning of control parameters The motor drive system is designed to create minimal acoustic noise Active power factor correction which reduces the negative effects of the load on the power grid in conducted noise and imaginary power Design is low cost General Benefits: Improved End System Performance Energy savings Quieter operation Improved EMI performance System Cost savings Enhanced Reliability Performance: Input voltage: 85 ~265VAC Input frequency: 45 ~65HZ Rating bus voltage: 350V Rating output power: 500W Switch frequency of PFC switch: 100KHZ Switch frequency of inverter: 10KHZ Power factor: >95% Efficiency: >90% Communications: RS232 port for communication with optoisolation Visual Interface: Multi-segment LED indicators Block Diagram Board Design Resources

本文说明S32G在Linux中如何使用内存读写工具来发起一个HSE Server服务请求，以确认HSE是否正常工作。本说明的目的旨在在极端缺少Debug手段的情况下，确认HSE的状态。 目录 1    背景说明与参考资料... 2 1.1  背景说明... 2 1.2  参考资料... 2 2    启动包含HSE的Linux镜像... 3 3    HSE服务代码逻辑与寄存器状态... 3 3.1  HSE Demo示例... 3 3.2  IDEL情况下MU寄存器状态... 6 4    使用Linux memtool命令来访问HSE. 10 4.1  检查HSE状态... 10 4.2  准备hseSrvDescriptor_t数据结构... 10 4.3  申请HSE服务... 11 5    其它建议... 12

  本文说明S32G  RDB2板Linux板级开发包BSP32 的ATF细节，以帮助客户了解S32G的ATF是如何运行的，以及如何修改到客户的新板上。   从BSP32开始，默认启动需要ATF支持，所以部分定制需要移动到ATF中，Uboot会简单很多。 请注意本文为培训和辅助文档，本文不是官方文档的替代，请一切以官方文档为准。   目录如下： 目录 1    S32G Linux文档说明... 2 2    创建S32G RDB2 Linux板级开发包编译环境... 3 2.1  创建yocto编译环境: 3 2.2  独立编译... 8 3    NXP ATF 原理... 13 3.1  AArch64 Exception Leve: 13 3.2  ATF原理... 14 3.3  ATF目录 结构... 16 3.4  ATF初始化流程... 25 3.5  NXP ATF的SCMI支持... 28 3.6  NXP ATF的PSCI支持... 32 3.7  NXP ATF OPTEE接口（未来增加）... 36 4    ATF 定制... 36 4.1  修改 DDR配置... 36 4.2  修改调试串口与IOMUX定制说明... 39 4.3  启动eMMC定制说明... 48 4.4  I2C与PMIC定制说明... 58

         LittleVgl作为一款开源免费的嵌入式GUI得到越来越多工程师的厚爱，我们可以看到很多小型HMI项目或者一些开源社区都在使用它作为GUI的框架，同时也受益于用户群的不断扩大以及一些半导体原厂的青睐（通俗点就是说有赞助有钱儿了），LittleVgl本身也在快速的不断更新迭代，易用的组件和相关的辅助开发工具在不断的增加，而RT1050/1060/1170系列作为一款带有LCD控制器的平台，自然成为了LittleVgl最佳的载体之一了。         LittleVgl本身的组件已经很丰富了，但是遗憾的是一直没有加入对中文输入法Keyboard的支持（看了下它在Github上的Contributor List没有华人），这让它在我们国内的应用有了一些限制（注意在某组件上显示中文和真正的中文输入法是不同的概念），所以本项目旨在解决该问题，即把一个简单轻量的中文输入法框架嵌入到LittleVgl并跑在RT1050平台上，并把它开源开放出来，所以不要小看了我的“公益心”，哈哈。下图是该示例设计的UI界面        下面进入正题，首先把测试环境给出来，方便有兴趣有能力的朋友可以自行搭建（当然应一部分偷懒的强烈需求，我随本文档也附赠了完整的移植好的工程），然后我再一步一步地给出如何移植这套框架到用户自己的工程里，当然我已经把代码本身做了很多优化，尽量减小环境依赖，力求最少步骤的移植过程，理论上来讲不太会出现移植后编译出一堆Error的问题，咳咳。。。下面我们赶紧开整吧： 测试环境： SDK版本：SDK_v2.9.1 SDK参考例程：boards\evkbimxrt1050\littlevgl_examples\littlevgl_demo_widgets LittleVgl版本：v7.4.0 IDE工具：Keil_v5.31 开发板：MIMXRT1050-EVK + 480*272 RGB LCD屏 软件说明： 我们先看下这套中文输入法所需的几个文件，如下图所示，.c和.h文件加起来一共7个，其中nxp_logo.c只是我额外加的一个NXP的官方logo图标转成的C数组文件供littleVgl调用显示，属于锦上添花的东西，可有可无，真正跟输入法相关的是剩下的6个文件，下面我们逐一介绍下这几个文件的作用： 1. qwerty_py.c/.h：        实际上这两个文件才是这套全键盘拼音中文输入法的核心框架，实现了对输入的拼音字母进行索引匹配对应的汉字候选列表，这部分我是移植了如下链接中网友分享的代码，所以这两个文件我的角色只是一个大自然搬运工，不过说实话我是很感激该网友的无私分享的（这也是我一直推崇开源分享精神的源动力），之前对平时使用的各种输入法里面的算法原理一直充满好奇，直到看了这篇文章后才豁然开朗，“So that is what it is!”，让我获益匪浅（可能人的学习曲线和知识体系就是这样一点一滴的积累吧），而且更关键的是，如果让我继续往下开发诸如拼音联想和多汉字输入等功能的话，我更多关心的可能只是逻辑搭建的工作量问题，而不是纠结于Yes or No的问题了，因为咱已经了解了其最底层的工作原理了，所以很多复杂的事情，我们如果能抽丝剥茧的找到其最底层的本质（虽然这真的很难），那很多让人抓耳挠腮的问题很快就可以理清思路。说到这里我思维又发散了，呵呵，我想起让Linus Torvalds等一波老大神们一直头疼的Linux内核维护后继无人的问题，其实我的个人理解有很大一部分原因是如今的Linux太庞大了以至于几乎没有后辈的人对Linux的理解能赶上这些老辈大神，而这些老辈大神的最大优势是他们创建了Linux最早期的底层框架而且难能可贵的是一直在follow Linux每个版本的历史。总之，推荐大家看看如下这篇文章吧（实际上主要内容也都是代码），希望能各有所获； https://www.amobbs.com/thread-5668320-1-1.html?_dsign=0939dcbd 2. lv_chs_keyboard.c/.c文件：        这部分就是我的工作了（咱也不能啥都搬运…，这是体现咱的value的东西不是），我把它当作littleVgl的一个补充组件来写的，里面的大多数API参考官方littlevgl的lv_keyboard.c，所谓的文章开头的嵌入中文输入法到LittleVgl GUI环境中实际上就是这两个文件干的活，即将上面提到qwerty.c/.h实现的拼音输入法与LittleVgl框架结合到一块，起到一个桥梁的作用，所以如果你想把这套中文输入法嵌入到其他GUI环境中的话（比如emWin，GUIX，TouchGFX等），那主要的工作就是参考这两个文件的内容了； 3. lv_font_NotoSansCJKsc_Regular.c字体文件：        虽然littleVgl官方源码包里自带了一个中文字体文件（\lvgl\src\lv_font\lv_font_simsun_16_cjk.c），但是它只包含了1000个左右最常用的字，我实际体验了下很多我们想用的字都找不到，所以这个时候就需要自己去做一个更全一点的字体库了。这里面涉及到两个问题需要考虑，第一是很多我们常见的中文字体是收费的（咱PC机的Microsoft Office套件里的中文字体都是微软付费买的，所以咱也理解下早年正版Windows为啥辣么贵了，那你问为啥现在便宜了？因为人家现在不靠这个赚钱了呗），第二个是字体转换工具的问题，我们网上找到的字体都是TTF或者OTF格式的，但littleVgl是不认的，需要转换成它支持的字体格式。        对于第一个问题，我网上搜了好久最终选择了目前用的比较多的Google开源免费的字体，Google真乃金主也，它维护的网站里面字体各种各样啥都有且是开源免费的，如下链接，我选择的是NotoSansCJKsc字体（最后面的sc表示simplified Chinese，简体中文），然后它里面又包含了各种字形（regular, bold, light等），可以根据需要自行选择，整个包很大（100多MB），拆分成不同字形的就小了（每个14~16MB左右）； https://www.google.com/get/noto/        对于第二个字体转换工具的问题，LittleVgl官方自带了一个字体转换工具（online font converter）,我个人觉着不太好用（对OTF字体支持的不行），这里推荐阿里大神自己做的一个LittleVgl字体转换工具（LvglFontTool），非常方便好用，且支持加入Awesome图标； http://www.lfly.xyz/forum.php?mod=viewthread&tid=24&extra=page%3D1        关于字体这部分我需要再补充个问题，就是它占用的memory大小，毕竟我们是在嵌入式MCU平台Flash和RAM的资源是受限的，如下图所示，该字体文件占用大概1Mbytes的rodata空间（即可寻址的Flash空间，当然该大小可以通过在上图转换工具中增减一些文字来调 整），所以在移植本套输入法之前需要预留足够的Flash空间，当然对RT平台来说这部分还好，毕竟其本身就外扩至少几MB空间的QSPI Flash作为存储空间的。 4. lv_demo_chineseinput.c/.h文件：        这两个文件属于应用层实现了，主要关注该文件中下图的ta_event_cb函数（即textarea事件的callback，点击文本框的输入时回调），在里面我们需要按照1，2，3去调用即可（这三步的API均在lv_chs_keyboard.c/h文件里实现）；        至此，这套全键盘拼音中文输入法框架所需的几个文件就介绍完了，用户只需要把这几个文件放到自己的工程设置好文件搜索路径，并参考随本文档附带的代码工程示例，再结合自己产品的GUI样式，把这套中文输入法嵌入到自己应用当中。

  Overview   NXP provides full solutions to power high-end payment terminals. NXP is at the forefront of contact and contactless payment solutions and is a leader in providing security solutions for the banking and payment industries. Combining NXP's portfolio of microprocessors, microcontrollers, interface peripherals and connectivity solutions can help to create a feature rich and easy-to-use payment terminal or tablet solution.   Block Diagram     Recommended Products   Category Name MCU Arm® Cortex®-M4|Kinetis K81 150 MHz 32-bit MCUs | NXP  Arm® Cortex®-M4 core + DSP up to 150 MHz, 16 kB CPU CacheAdvanced public key crypto and tamper detection. Low-power peripherals and DMA for continuous system operation in reduced power stat. Ideal for entry level, highly secure POS terminals. i.MX 6UltraLite Applications Processor | Single Arm® Cortex®-A7 @ 696 MHz | NXP  Cortex-A7 @ 696 MHz, 128 kB L2 cache. Security Block: TRNG, Crypto Engine (AES with DPA, TDES/SHA/RSA), Tamper Monitor, Secure Boot, SIMV2/EVMSIM X 2, OTF DRAM. Encryption, PCI4.0 precertification. Ideal for high-end, high-quality HMI POS terminals. LPC55S6x|Arm® Cortex®-M33|32-bit Microcontrollers (MCUs) | NXP  Cortex-M33 processor, running at a frequency of up to 100 MHz. Security features: Arm TrustZone, PRINCE module, AES-256, SHA2, Physical Unclonable Function, RNG, 128-bit UUID, and Secure GPIO. Ideal for entry level, highly secure POS terminals.   Category Name NFC Contact Readers | NXP  Highly versatile family of ISO7816 compatible contact reader ICs. NFC - Near Field Communication | NXP  Wide range of NFC and reader ICs for physical access systems, POS terminals, PC solutions, eGovernment applications, public transport schemes, Pay TV solutions, eMetering, gaming, industrial and white goods applications. PN5180 | Full NFC Forum-compliant frontend IC | NXP  Optimized for POS terminal applications, allows to achieve compliancy to EMVCo 3.0 analog and digital and implements a high-power NFC frontend.   Category Name Power Management DC-to-DC Solutions | NXP  Highly integrated and cost-effective power conversion solution. BC3770 | 2 A Switch-Mode Li-ion/polymer Battery Charger | NXP  Power Supplies and Package Programmable charge parameters via I2C compatible interface High-efficiency synchronous switching regulator Extensive protection Power Management Integrated Circuits (PMICs) | NXP  The new PF series of PMICs brings advanced levels of configurability and programmability in a system level PMIC solution, enabling a single device to be easily configured to provide power to a wide range of processors and peripherals.   Category Name Secure Arm® Cortex®-M0+|Kinetis KL8x Ultra-Low Power MCUs | NXP  The K8x Arm® Cortex®-M4 MCUs are designed with expandable memory & advanced security capabilities targeting IOT applications such as payment & identification. Kinetis® K8x Secure Microcontrollers (MCUs) based on Arm® Cortex®-M4 Core | NXP  The K8x Arm® Cortex®-M4 MCUs are designed with expandable memory & advanced security capabilities targeting IOT applications such as payment & identification.   Category Name Peripheral I²C LED Controllers ICs | NXP  Our I2C LED controllers enable core functions in some of today’s most ubiquitous devices and applications. Load Switches | NXP  Integrated Type C functionality, Fast Reverse Current Protection and Recovery, High Voltage Tolerance. Bluetooth®Smart/Bluetooth Low Energy | NXP  Highly integrated SoCs with up to 512 KB Flash and 128 KB RAM utilizing Arm® Cortex®-M4F cores. Ultra-low-power, 1.8 V, 1 deg. C accuracy, digital temperature sensor with I2C bus interface | NXP  Tiny WLCSP6 package Accuracy: 0.5 °C from 0 °C to +85 °C Low quiescent current: 30 μA Active and 1 μA Shut-down Supply range: 1.8 V ± 0.15 V Resolution: 12 bits

doc&project&patch&script explain to support GD qspi nor in lauterbach, flash tool,ivt,fls mcal, fls bootloader and linux/ chinese/english 目录 1    背景和参考资料... 2 1.1  背景说明... 2 1.2  参考资料... 3 1.3  硬件连接... 5 2    Lauterbach脚本驱动开发(可选) 5 2.1  准备参考脚本... 5 2.2  QuadSPI_ReadID.. 6 2.3  配置QSPI NOR为DOPI模式... 7 2.4  使用DOPI模式 READ_8DTRD.. 10 2.5  测试结果... 13 3    Flash tool算法镜像开发... 14 3.1  Flash SDK实现的算法... 15 3.2  开发新的flash源代码... 17 3.3  测试结果... 20 4    开发IVT参数头... 22 4.1  S32G QSPI控制器配置区别... 24 4.2  QSPI的配置区别... 28 4.3  测试结果... 29 5    开发MCAL Fls驱动... 30 5.1  MCAL Fls驱动工程说明... 30 5.2  FlsMem配置页... 34 5.3  MemCfg配置页... 35 5.4  测试结果... 49 6    开发Bootloader工程中Fls驱动... 51 6.1  Bootloader工程说明... 51 6.2  Bootloader与MCAL Fls驱动的不同点... 53 6.3  镜像打包... 54 6.4  测试结果... 56 7    开发Linux驱动(可选) 57 7.1  Linux GD驱动支持情况... 57 7.2  时钟相关的修改... 58 7.3  在DTS中增加GD flash的支持... 60 7.4  修改源代码增加flash信息结构体... 61 7.5  修改源代码中flash的fixup支持DTR模式... 62 7.6  Turning dummy值解决读错位的问题... 64 7.7  测试结果... 65   Content 1    Background and References. 2 1.1  Background. 2 1.2  References. 3 1.3  Hardware Link. 5 2    Lauterbach Script development(Optional) 6 2.1  Preparing the refer script 6 2.2  QuadSPI_ReadID.. 6 2.3  Configure QSPI NOR to DOPI mode. 8 2.4  Use DOPI mode  READ_8DTRD.. 11 2.5  Test report 13 3    Flash tool algorithm image development 15 3.1  Algorithms implemented by Flash SDK. 15 3.2  Develop new flash source code. 17 3.3  Test Report 21 4    Develop IVT Parameter Header 23 4.1  S32G QSPI Controllder configuration difference. 25 4.2  QSPI Configuration Difference. 30 4.3  Test Report 30 5    Develop MCAL Fls driver 31 5.1  MCAL Fls Driver Project Details. 31 5.2  FlsMem Configuration page. 35 5.3  MemCfg Configuration page. 36 5.4  Test Report 51 6    Develop Bootloader Project Fls Drivedr 52 6.1  Bootloader Project Details. 52 6.2  Difference of Bootloader and MCAL Fls Driver 54 6.3  Image Package. 56 6.4  Test Report 58 7    Develop Linux Driver(Optional) 59 7.1  Linux GD Driver Details. 59 7.2  Modification of Clock. 60 7.3  In DTS add GD flash Support 62 7.4  Modify source code and add flash information structure  63 7.5  Modify the fixup of flash in source code to support DTR mode  64 7.6  Turning Dummy Value to Solve the Misplacement Problem   66 7.7  Test Report 67

  Overview Near Field Communication (NFC) is used for real-time precision marketing based on time, local inventory and the individual when embedded in product displays or the products themselves. NFC is also becoming the preferred method for payment either in smartphones or smart payment cards. In this particular deployment , the overall system consists of Backend Servers, Top Up station and Household Meter. The Backend Server roles are to activate the new installed meter, to collect meter usage data and behaviors, to implement new tariff based on user behaviors, and to allocate energy usage in effective way. Top Up Stations are NFC Reader with SAM and they are connected to local Computer, Tablet or Mobile phone. They are located at retailers near by household to ease the user to buy the credits. Besides that, Top Up Station is also help to upload and download settings or parameter from the Backend Server Household Meters are those Contctless Prepaid Meter has been installed at end user Block Diagram Products Category MCU Product URL KM3x: 50–75 MHz Precision Metrology MCUs with Segment LCDs based on Arm® Cortex®-M0+  Product Description The KM3x MCU family enables single-chip one-, two-, and three-phase electricity meters, as well as flow meters and other precision measurement applications.   Category NFC Fronted Product URL CLRC663 plus family: High-performance NFC frontends  Product Description If you need high NFC performance or the lowest power consumption, use this remarkably efficient yet highly flexible frontend family to push your design further.   Category RTC Product URL PCF8563: Real-time clock/calendar  Product Description The PCF8563 is a CMOS Real-Time Clock (RTC) and calendar optimized for low power consumption.   Category Secure Element Product URL A71CH: Plug and Trust - The fast, easy way to deploy secure IoT connections  Product Description A71CH is a ready-to-use secure element for IoT devices providing a root of trust at the IC level and delivers, chip-to-cloud security right out of the box, so you can safely connect to IoT clouds and services, including AWS, IBM Watson IoT™ Platform, and Google Cloud™ IoT Core without writing security code or exposing keys.   Category Power Management Product URL TEA1721BDB1065: TEA1721 Universal Mains White Goods Flyback SMPS Demo Board  Product Description This reference design demonstrates the TEA1721 as a -12 V and -3.3 V AC/DC SMPS converter that can provide 5 W into a load.   Category Smart Card Product URL 1 MIFARE® DESFire® EV3: High-Security IC for Contactless Smart City Services  Product Description 1 The features of the MIFARE DESFire EV3 IC reflect NXP’s continued commitment to secure, connected and convenient contactless Smart City services. Product URL 2 MIFARE Plus® EV2: Secure IC for Contactless Smart City Services  Product Description 2 As the next generation of NXP’s MIFARE Plus product family, the MIFARE Plus EV2 IC is designed to be both a gateway for new Smart City applications and a compelling upgrade, in terms of security and connectivity, for existing deployments.

目录 1 S32G Linux文档说明 .................................................. 3 2 创建S32G RDB2 Linux板级开发包编译环境 .............. 4 2.1 创建yocto编译环境: ................................................. 4 2.2 独立编译 ................................................................. 9 3 FSL Uboot 定制 ........................................................ 14 3.1 FDT支持 ............................................................... 14 3.2 DM(driver model)支持 ........................................... 20 3.3 Uboot目录结构 ...................................................... 31 3.4 Uboot编译 ............................................................. 34 3.5 Uboot初始化流程 .................................................. 35 3.6 使能了ATF后对Uboot初始化流程的影响 ............... 40 4 Uboot 定制 ............................................................... 41 4.1 修改 DDR大小 ....................................................... 41 4.2 修改调试串口与IOMUX说明 .................................. 44 4.3 DM I2C与PMIC初始化 .......................................... 53 4.4 通用GPIO ............................................................. 59 4.5 启动eMMC定制 ..................................................... 69 4.6 Ethernet定制 ......................................................... 78 5 Uboot debug信息 ..................................................... 89 5.1 Print env ............................................................... 89 5.2 dm - Driver model low level access ...................... 92 5.3 fdt .......................................................................... 95 5.4 I2C测试 ................................................................. 95 5.5 芯片寄存器访问 ..................................................... 98 updated to V5