Overview The NXP® Healthcare Analog Front End reference platform is a complete set of portable medical solutions that enable designers with rapid development tools. Provides ready-to-develop hardware and software that facilitates the design of medical assets such as vital signs monitors, glucose meters and digital stethoscopes, among other portable and healthcare professional devices Based on the Kinetis® K53 high-performance, low-cost, low-power MCU Embeds a complete analog measurement engine including Opamps, TRIAMPS, ADCs, DACs and analog comparators among other modules, reducing costs and PCB sizes Features Developed using the Kinetis ®  K53 MCU, featuring an Arm ®  Cortex ® -M4 core Kinetis K53 MCU also provides low-power operation, DSP capabilities, USB and graphic interface support and a complete analog measurement engine Includes six healthcare-specific analog front ends with reusable software and hardware NXP ®  provides a full set of software tools (CodeWarrior ® , USBSTACK, MQX™ RTOS) NXP product longevity program offers up to 15-year availability for selected products Block Diagram Board Video Design Resources

This doc explain how to configure a new LPDDR4 and test it on S32G, contents as follows: 目录 1    硬件资源，文档及工具下载... 2 1.1    硬件资源... 2 1.2    内存配置测试相关的文档... 2 1.3    内存配置与压力测试工具. 3 2    内存设计要求... 3 3    LPDDR4基础... 3 3.1    基本知识... 3 3.2    Inline ECC.. 4 4    硬件连接... 6 5    S32G+LPDDR4内存配置与测试步骤... 8 5.1    配置LPDDR4初始化寄存器设置... 9 5.2    使用内存测试工具初始化PHY及生成DDRC配置Uboot源代码    11 5.3    生成DDRC配置ATF源代码(从BSP32开始) 14 5.4    测试内存... 18 5.5    其它尺寸的LPDDR4配置... 19 6    测试失败的DEBUG.. 24 7    内存参数应用到Uboot中... 25 8    内存参数应用到ATF中... 25 9    附录... 25 9.1    一个重要的DDR TOOL bug Fix. 25 9.2    Uboot DDR测试工具... 26 9.3    Kernel DDR测试工具... 27 9.4    附DDR tool测试项截图... 28   Contents 1    Hardware Materials, Docs and Tools Needed. 2 1.1    Hardware resource. 2 1.2    Related docs of memory configuration and test 2 1.3    Memory configuration and test tools. 3 2    Memory Hardware Design Requirement 3 3    LPDDR4 Basics. 3 3.1    Basic Knowledge. 3 3.2    Inline ECC.. 5 4    Hardware Design. 7 5    S32G+LPDDR4 Memory Configuration and Test Steps. 8 5.1    Configure LPDDR4 DDRC Register Settings. 9 5.2    Use the Memory Test Tool to Initialize the PHY and Generate the DDRC Configuration Uboot Source Code  12 5.3    Generate ddrc configuration ATF source code (starting from bsp32) 15 5.4    Memory Test 19 5.5    Other size LPDDR4 configurations. 20 6    Debug of the Fails of Test 25 7    Modify the DDRC register settings in Uboot 26 8    Modify the DDRC register settings in ATF. 26 9    Appendix. 26 9.1    A importance DDR TOOL bug Fix. 26 9.2    Uboot DDR Test Tools. 27 9.3    Kernel DDR Test Tool 28 9.4    Attached Screenshot of DDR Tool Test Items. 29

This doc expain how to use eMMC from user space, contents as follows: 目录 1 eMMC的分区情况 ...................................................... 2 2 S32G+BSP29上默认的eMMC启动 ............................ 3 2.1 eMMC硬件设计 .................................................. 3 2.2 eMMC的镜像烧写办法与启动 ............................. 6 2.3 增加MMC内核测试工具 .................................... 10 3 eMMC GP功能的测试 .............................................. 10 3.1 eMMC GP功能的说明 ....................................... 10 3.2 eMMC GP功能的测试 ....................................... 11 4 eMMC RPMB功能的测试 ......................................... 13 4.1 eMMC RPMB功能的说明 ................................. 13 4.2 eMMC RPMB功能的测试 ................................. 15

Combining NXP's wireless MCU with NFC controller allows to build a BLE-NFC bridge. It allows demonstrating transmission of NFC data over BLE, acting then as a king of Magic NFC remote. This demonstrator is built assembling the OM5578: Development Kits for PN7150 Plug’n Play NFC Controller (OM5578/PN7150ARD version including Arduino compatible connectors). on top of the FRDM-KW41Z: Freedom Development Kit for Kinetis ® KW41Z/31Z/21Z MCUs (minimum version B1 since previous versions have a pin conflict on the Arduino connector) Alternatively the Rigado R41Z Eval Board can be used as replacement to the FRDM-KW41Z To complete the demonstration, an android phone is used as BLE counterpart. It shall run the modified version of Kinetis BLE Toolbox android application including the NFC demo part. This dedicated version of the Kinetis BLE Toolbox android application is available for download from the files attached to this document. Below is a video of the demo. As shown, it demonstrate capabilities to control the NFC discovery remotely (via BLE) from the phone. Then, if tapping a card on the bridge, the related information including the content is conveyed through BLE to the phone and get displayed by the app. Additionally, the app can configure a message to be shared whenever an NFC reader (e.g. NFC phone) tap the bridge. The K41Z firmware of this demo is built based on the wireless UART example from MCUXpresso Software Development Kit (SDK), and updated with the porting of the NXP-NCI MCUXpresso example. The complete MCUXpresso project is given in source code in the attached files. To replicate the demo, just import it in an MCUXpresso workspace by selecting "Existing Projects into Workspace", then browsing to the BLE-NFC_bridge_MCUXpressoProject.zip file. Select the frdmkw41z_BLE-NFC_bridge from the "Project Explorer" view, and click on the blue bug icon to build, flash and debug the program.

Overview In the industrial world, it is critical to incorporate fail-safe technology where possible in applications such as crane steering machines, robotic lift, and assembly line robots to name a few. By doing so, you ensure you meet Safety Integrity Level (SIL) standards as found in the IEC 61508 standard. Also, you significantly increase human safety and protect products and property. This fail Safe Motor Control solution incorporates the MPC574xP family of MCUs that delivers the highest functional safety standards for industrial applications. The MPC574xP family incorporates a lockstep function that serves as a watchdog function to flag any problems with the MCU including a programmable Fault Collection and Control Unit (FCCU) that monitors the integrity status of the MCU and provides flexible safe state control. Also, this device is a part of the SafeAssure® program, helping manufacturers achieve functional safety standard compliance. Block Diagram Recommended Products Category Products Features Power Switch 12XS2 | 12 V Low RDSON eXtreme Switch | NXP  Watchdog and configurable Fail-safe mode by hardware Authentication time (on-chip calculations) < 50 ms Programmable overcurrent trip level and overtemperature protection, undervoltage shutdown, and fault reporting Output current monitoring Pressure Sensor MPXHZ6130A|Pressure Sensor | NXP  The MPXHZ6130A series sensor integrates on-chip, bipolar op amp circuitry and thin-film resistor networks to provide a high output signal and temperature compensation for automotive, aviation, and industrial applications. Temperature Sensor https://www.nxp.com/products/sensors/silicon-temperature-sensors/silicon-temperature-sensors:KTY8X High accuracy and reliability Long-term stability Positive temperature coefficient; fail-safe behavior MOSFET Pre-driver GD3000 |3-phase Brushless Motor Pre-Driver | NXP  Fully specified from 8.0 to 40 V covers 12 and 24 V automotive systems Extended operating range from 6.0 to 60V covers 12 and 42 V systems Greater than 1.0 A gate drive capability with protection Power Management and Safety Monitoring MC33908 | Safe SBC | NXP  Enhanced safety block associated with fail-safe outputs Designed for ASIL D applications (FMEDA, Safety manual) Secured SPI interface   Evaluation and Development Boards   Link Description MPC5744P Development Kit for 3-phase PMSM | NXP  The NXP MTRCKTSPS5744P motor control development kit is ideal for applications requiring one PMSM motor, such as power steering or electric powertrain. Evaluation daughter board - NXP MPC5744P, 32-bit Microcontroller | NXP  The KITMPC5744DBEVM evaluation board features the MPC5744P, which is the second generation of safety-oriented microcontrollers, for automotive and industrial safety applications

Explore the MC34937, an industrial-grade 3-phase gate pre-driver for BLDC and PMSM motor control. The MC34937 can support 12V, 24V, and 36V motor control applications and easily interfaces to standard MCUs and DSPs. The demo shows the implementation of the MC34937 with Kinetis Microcontrollers E in a 36V battery-operated electric bike (eBike) application. This same system can be modified to be used in other industrial applications such as electric garden tools, industrial fans and pumps, and electric wheelchairs. Features Demo shows capability of Kinetis KE02 connecting to an MC34937 Motor Driver MC34937 able to drive 12V, 24V, 36V, 48V systems Featured NXP Products Kinetis E - KE02Z64 MC34937 3-phase gate pre-driver Block Diagram MC34937 Schematics and Software:

Overview This reference design demonstrates speed control of the 3-Phase Switched Reluctance (SR) motor with Hall position sensor using the NXP® 56F80x or 56F83XX Digital Signal Controllers (DSCs). It helps start development of the SR drive dedicated to the targeted application The DSC runs main control algorithm; when the start command is accepted, the state of the Hall sensors position signals is sensed and the individual motor phases are powered in order to start the motor in the requested direction of rotation without rotor alignment According to the determined switching pattern and the calculated duty cycle, the on-chip PWM module generates the PWM signals for the SR motor power stage Features Speed Control of an SR motor with position Hall sensors Targeted 56F80X, 56F83XX, and 56F81XX Digital Signal Controllers Running on a 3-Phase SR HV Motor Control Development Platform (115/230VAC) Running on a 3-phase SR LV Motor Control Development Platform (12V DC) The control technique: voltage control with a speed closed loop Hall sensors position reference for commutation Start from any motor position without rotor alignment Manual interface FreeMASTER software control interface and monitor Fault protection Block Diagram Board Design Resources

Overview This drive application allows vector control of an AC Induction Motor (ACIM) running in a closed-speed loop without a speed/position sensor at a low cost and serves as an example of AC induction vector control drive design using an NXP ®  56F8013 with Processor Expert ®  software support. ACIM is ideal for appliance and industrial applications This design uses sensorless FOC to control an ACIM using the 56F8013 device, which can accommodate the sensorless FOC algorithm The motor control system is flexible enough to implement complex motion protocols while it drives a variable load. The system illustrates the features of the 56F8013 in motor control Features General: The motor control algorithm employs Stator-Flux-Oriented Control (SFOC) Power stage switches are controlled by Space Vector Pulse Width Modulation (SVPWM) No position information devices or stator flux measurement are used, a sensorless speed method is employed The motor is capable of forward and reverse rotation and has a speed range from 50rpm to 3000rpm The user controls motion profiles, rotation direction, and speed. The RS-232 communication supports further R&D by enabling the easy tuning of control parameters The motor drive system is designed to create minimal acoustic noise Active power factor correction which reduces the negative effects of the load on the power grid in conducted noise and imaginary power Design is low cost General Benefits: Improved End System Performance Energy savings Quieter operation Improved EMI performance System Cost savings Enhanced Reliability Performance: Input voltage: 85 ~265VAC Input frequency: 45 ~65HZ Rating bus voltage: 350V Rating output power: 500W Switch frequency of PFC switch: 100KHZ Switch frequency of inverter: 10KHZ Power factor: >95% Efficiency: >90% Communications: RS232 port for communication with optoisolation Visual Interface: Multi-segment LED indicators Block Diagram Board Design Resources

本文说明S32G在Linux中如何使用内存读写工具来发起一个HSE Server服务请求，以确认HSE是否正常工作。本说明的目的旨在在极端缺少Debug手段的情况下，确认HSE的状态。 目录 1    背景说明与参考资料... 2 1.1  背景说明... 2 1.2  参考资料... 2 2    启动包含HSE的Linux镜像... 3 3    HSE服务代码逻辑与寄存器状态... 3 3.1  HSE Demo示例... 3 3.2  IDEL情况下MU寄存器状态... 6 4    使用Linux memtool命令来访问HSE. 10 4.1  检查HSE状态... 10 4.2  准备hseSrvDescriptor_t数据结构... 10 4.3  申请HSE服务... 11 5    其它建议... 12

IEEE 1588协议简单理解        IEEE 1588 是一个精密时间协议 (PTP)，用于同步计算机网络中的时钟。 在局域网中，它能将时钟精确度控制在亚微秒范围内，使其适于测量和控制系统。 IEEE 1588 标准为时钟分配定义了一个主从式架构，由一个或多个网段及一个或多个时钟组成。 ​       TSN 网络中时间同步协议使用 IEEE 802.1AS 协议，它基于 IEEE 1588 协议进行精简和修改，也称为 gPTP 协议。 ​       IEEE 1588 协议简称精确时钟协议 PTP（Precision Timing Protocol），它的全称是“网络测量和控制系统的精密时钟同步协议标准”（IEEE 1588 Precision Clock Synchronization Protocol）。其工作的基本原理，是通过主从节点之间进行同步数据帧的发送，记录数据帧的发送时间和接收时间信息进行，并且将该时间信息添加到该数据帧中。从节点获取这些时间信息，并计算从节点本地时钟与主时钟的时间偏差和网络节点之间的传输延时，对本地时钟进行纠正，使之与主节点时钟同步。一个 PTP 网络只能存在一个主时钟。 ​ PTP 协议主要分为两大部分来实现时钟同步功能： ​ 1、建立同步体系： ​       协议使用最佳主时钟算法（Best Master Clock Algorithm，BMCA），通过选取主时钟，建立主从拓扑关系，进而在整个 PTP 网络中建立起同步体系。 ​ 2、同步本地时钟： ​       协议使用本地时钟同步算法（Local Clock Synchronization Algorithm，LCS），通过 PTP 数据报文在网络主从节点之间的交换，计算各从节点本地时钟与主时钟间的时间偏差，调整本地时钟，使之与主时钟同步。 IEEE 1588v1 ​       整个 PTP 网络内的时钟可按照其上 PTP 通信端口的数目来划分成普通时钟（Ordinary Clock，OC）与边界时钟（Boundary Clock，BC）：普通时钟只存在一个，而边界时钟则存在多个。一般在确定性不高的网络节点处使用边界时钟，例如交换机或者路由器一般用作边界时钟，如下图所示。在每个端口上，PTP 通信都是独立进行的。 1、边界时钟： ​      边界时钟上只允许存在一个从端口，与上级节点的主端口通信，将其本地时钟与级主端口进行同步。其余端口为主端口，与下游节点的从端口进行通信。边界时钟可以连接不同的网络协议。 ​ 2、同步体系建立流程： ​   （1）初始状态，各个节点端口会在指定的时间内侦听网络中的 Sync 数据帧； 若接收到 Sync 数据帧，节点端口将根据最佳主时钟算法决定端口状态。若没有收到 Sync 数据帧，该节点状态变更为 Pre_Master，并将自己假定为主时钟节点。此时节点端口状态表现为主时钟，但是并不发送 Sync 帧。 ​   （2）端口状态在一定时间内保持 Pre_Master： 若在端口指定时间内接收到 Sync 数据帧，则该端口状态由最佳主时钟算法决定。 若判定端口为主时钟，则将周期性地发送 Sync 帧；若判定为从时钟，则接受 Sync 帧，并计算偏差，纠正本地时钟。 ​ 若在该时间段内端口没有收到 Sync 数据帧，则将状态变更为主时钟，并且开始定时发送 Sync 数据帧。 ​   （3）主时钟和从时钟的状态随着时钟性能与运行状态的变化而变化。下图展示了 BMCA 中状态转移。 3、时间同步建立流程： ​ 如下图PTP同步原理         如图所示，Master为网路中的同步时钟源，可以认为其与UTC或者GPS时无限接近。Slave为网络中需要被同步设备。假设从Master到Slave的路径符合对称路径，那么路径上的延时我们设Delay，然后设备Master和设备Slave之间待同步的时间差值为Offset，即Slave比Master在同一时刻慢Offset。         Slave设备根据算出的Offset即可以进行本地时钟校准。但是1588V1协议依赖于链路的对称性，即Master到Slave与Slave到Master时延一致，这在实际网络状况下很难满足，故需要额外的不对称算法进行链路延时差计算和补偿校准。   IEEE 1588v2 ​IEEE1588V2在IEEE1588V1版本上做了改进和扩展。主要包括： ​ 1.新增点到点路径延时测量的独立消息模式。 端口 A 与端口 B 间的路径延迟时间 Delay 为： ​        在 PTPv1 中，平均路径延迟测量时通过 Sync 帧与 Delay_Req 帧配合使用的，但是在 PTPv2 中却不需要 Sync 帧的参与，仅通过 PDelay_Req 数据帧系列来进行测量。这是一个独立的延迟测量过程，不依赖 Sync 帧和同步体系建立的参与，使得测量精度有所提高，并且可以经过多次测量求得平均值得到更为准确的路径延迟。另一方面，如果网络中的同步体系发生改变，这时不需要重新计算该节点间的路径延迟，直接使用之前已测得的延迟数据，大大增强了协议执行的效率，使得协议更为方便灵活。在PTPv2 中，利用 PDelay_req 数据帧系列已成为主要的测量路径延迟方法。 ​ 2、新增透明时钟模型 ​        在 PTPv1 中，网络中间节点均采用边界时钟模型。与网络中唯一的主时钟，即一个普通时钟连接的边界时钟，其上唯一的从端口接收主节点发送的同步数据帧，与主时钟实现同步，其余的主端口和与之相连的其他边界时钟发送同步数据帧，最后同步到网络边缘的普通时钟，这样便实现了整个网络的时间同步。这种方法虽然可行，但是由于这种方式是逐级同步，所以距离主时钟越远的节点，同步精度越低。 ​        当网络中的一些节点不需要进行时钟同步或者不具备同步功能时，便可采用透明时钟模型。透明时钟不像 BC/OC 模式那样，需要每个节点都与主时钟进行同步，它的端口只对协议数据帧进行转发，并将计算出的数据帧滞留时间添加在校正域中。这种方式将 PTP 数据帧的处理变得更为简单，降低了网络中 PTP 协议的实施难度，同时提高了各从节点的同步精度。 ​ 透明时钟有模型两种：端对端透明时钟，和点对点透明时钟。 ​     （1）端对端（E2E）透明时钟 ​ E2E 透明时钟对网络中普通数据帧不做任何处理，仅进行转达让其正常通过。但是对于 PTP 事件数据帧，则将他们从接收端口到发送端口间的驻留延迟时间累加到数据帧中的修正域，用以弥补 PTP 数据帧在经过其自身所带来的延迟误差。 ​     （2）点对点（P2P）透明时钟 ​ 点对点（P2P）透明时钟只转发特定的 PTP 报文，包括 Sync 帧、Follo_Up 帧和Announce 帧等。并且会采用 Pdelay_Req 数据帧系列计算每个端口与所连接的端口间的路径延迟时间，再与端口间延迟时间合并添加到时间修正域，来补偿数据帧从源端口到点对点透明时钟出端口的时间延迟。 ​ 3、增加单步时钟模型 ​        单步时钟模型解决了 Follow_Up 帧与 Sync 帧匹配问题。PTP 协议基本的同步过程采用双步模式，即主时钟节点发送 Sync 帧，和带有 Sync 帧发送时间的Follow_Up帧。这种方式虽然能提高 Sync 帧时间戳标记的精度，提高同步效果，但是在网络负载较大的情况下，数据帧很有可能发生丢失或者阻塞，造成两种数据帧的匹配出现差错。 ​        在 PTP 数据帧中设置一个标志，来使用单步模式，将 Sync 帧的发送时间与数据帧中的时间标签的差值作为传输延迟，并将其累加到修正域中。这样主时钟便通过单独的 Sync 帧而不需要 Follow_Up 进行时间的同步校准工作。 ​        单步模式可以减少网络流量，提高网络负载较大时同步的可靠性。单步模式需要额外的辅助硬件，来帮助计算时间修正值并将其累加到校正域中，这对网络的实时性有比较高的要求。 BMCA ​        BMCA，即最佳主时钟算法，它选择网络中性能最佳的时钟作为主时钟，并以 此建立网络拓扑，生成同步体系，进而实现时钟同步功能。 ​        最佳主时钟的选取是通过Announce帧在网络中各节点的传输，比较各个节点上的时钟属性（比如是否将时钟指定为主或者从时钟），用于标识精度的时钟等级，以及用于标识时钟源类型的时钟类型（比如铷钟、铯钟等），还有表示时钟偏移、方差等的时钟特性、时钟地址以及时钟端口号等特征来选择最佳主时钟，当其他时钟特征都一样是，协议会将端口号最小的节点时钟作为主时钟。IEEE 1588协议会以主时钟节点作为根节点形成树形拓扑结构，并且为避免生成回路，那些竞争失败的节点端口，协议将他们定义为被动或者禁用状态。

  本文说明S32G  RDB2板Linux板级开发包BSP32 的ATF细节，以帮助客户了解S32G的ATF是如何运行的，以及如何修改到客户的新板上。   从BSP32开始，默认启动需要ATF支持，所以部分定制需要移动到ATF中，Uboot会简单很多。 请注意本文为培训和辅助文档，本文不是官方文档的替代，请一切以官方文档为准。   目录如下： 目录 1    S32G Linux文档说明... 2 2    创建S32G RDB2 Linux板级开发包编译环境... 3 2.1  创建yocto编译环境: 3 2.2  独立编译... 8 3    NXP ATF 原理... 13 3.1  AArch64 Exception Leve: 13 3.2  ATF原理... 14 3.3  ATF目录 结构... 16 3.4  ATF初始化流程... 25 3.5  NXP ATF的SCMI支持... 28 3.6  NXP ATF的PSCI支持... 32 3.7  NXP ATF OPTEE接口（未来增加）... 36 4    ATF 定制... 36 4.1  修改 DDR配置... 36 4.2  修改调试串口与IOMUX定制说明... 39 4.3  启动eMMC定制说明... 48 4.4  I2C与PMIC定制说明... 58

Overview This reference design of a 3-phase Permanent Magnet Synchronous Motor (PMSM) sensorless vector control drive and a Brushless DC (BLDC) Motor drive without position encoder coupled to the motor shaft uses the NXP® 56F8013 with Processor Expert® software support. PMSM/BLDC motor are excellent choices for many appliances and industrial applications that require low cost and high-performance variable speed operation This design will employ sensorless FOC to control a PMSM and a sensorless algorithm to control BLDC The hardware design supports both motor types with the algorithms fully implemented digitally via software running on the 56F8013 DSC Features General: For PMSM the motor control algorithm employs Field-Oriented Control (FOC). The power stage switches are controlled by means of Space Vector Pulse Width Modulation (SVPWM) The feedback hardware elements are limited to the motor stator phase currents and the bus voltage. No position information devices or stator flux measurement are used; sensorless speed methods are employed The Motor is capable of forward and reverse rotation and has a speed range of 500rpm to 6000rpm The user controls motion profiles, rotation direction, and speed. The RS-232 communication supports further R&D by enabling the easy tuning of control parameters The motor drive system is designed to create minimal acoustic noise Active power factor correction which reduces the negative effects of the load on the power grid in conducted noise and imaginary power Design is low cost General Benefits: Improved End System Performance Energy savings Quieter operation Improved EMI performance System Cost savings Enhanced Reliability Performance: Input voltage: 85 ~265VAC Input frequency: 45 ~65HZ Rating bus voltage: 350V Rating output power: 500W Switch frequency of PFC switch: 100KHZ Switch frequency of inverter: 10KHZ Power factor: >95% Efficiency: >90% Communications: RS232 port for communication with optoisolation Visual Interface: Multi-segment LED indicators Block Diagram Board Design Resources

本文说明在S32G3 RDB3板上，Uboot中使能PFE驱动时，需要加载PFE FW，默认Uboot中，PFE FW是放在SD/eMMC的FAT分区，通过文件系统访问来读取。本文说明如何修改为从QSPI NOR中读取。主要的应用场景是：  在烧写镜像时，需要Uboot通过网口来烧写内核镜像及rootfs。而此时SD/eMMC还没有分区，所以无法将PFE网口需要的FW放在FAT分区中。 目录 1    背景与相关资料... 2 1.1  问题背景... 2 1.2  需要的软件，工具与文档... 3 2    将Uboot PFE FW放在QSPI Nor上... 4 2.1  Uboot代码说明与修改... 4 2.2  测试... 6

目录 1 S32G Linux文档说明 .................................................. 3 2 创建S32G RDB2 Linux板级开发包编译环境 .............. 4 2.1 创建yocto编译环境: ................................................. 4 2.2 独立编译 ................................................................. 9 3 FSL Uboot 定制 ........................................................ 14 3.1 FDT支持 ............................................................... 14 3.2 DM(driver model)支持 ........................................... 20 3.3 Uboot目录结构 ...................................................... 31 3.4 Uboot编译 ............................................................. 34 3.5 Uboot初始化流程 .................................................. 35 3.6 使能了ATF后对Uboot初始化流程的影响 ............... 40 4 Uboot 定制 ............................................................... 41 4.1 修改 DDR大小 ....................................................... 41 4.2 修改调试串口与IOMUX说明 .................................. 44 4.3 DM I2C与PMIC初始化 .......................................... 53 4.4 通用GPIO ............................................................. 59 4.5 启动eMMC定制 ..................................................... 69 4.6 Ethernet定制 ......................................................... 78 5 Uboot debug信息 ..................................................... 89 5.1 Print env ............................................................... 89 5.2 dm - Driver model low level access ...................... 92 5.3 fdt .......................................................................... 95 5.4 I2C测试 ................................................................. 95 5.5 芯片寄存器访问 ..................................................... 98 updated to V5

This doc explain how to build a PFE master project on M7 and how to integration. chinese version. 目录 1 需要的软件与工具 ...................................................... 2 2 Master Demo编译说明 ............................................... 2 2.1 安装RTD_MCAL驱动 ............................................. 2 2.2 安装PFE_MCAL驱动 .............................................. 3 2.3 编译PFE master工程 .............................................. 3 3 修改为支持RDB板的RGMII接口 ................................ 4 3.1 硬件连接 ................................................................. 4 3.2 软件修改 ................................................................. 5 4 Master Demo测试 ...................................................... 7 4.1 硬件连接 ................................................................. 7 4.2 PFE_EMAC1(RGMII)测试过程 ............................... 7 5 Master Demo代码说明 ............................................... 8 6 集成中注意点 ........................................................... 11 6.1 PFE_PreInit .......................................................... 11 6.2 S32G3中的GENCTRL1的配置 ............................. 12 6.3 RX CLOCK重新锁定 ............................................ 13 7 Demo Debug建议 .................................................... 14 7.1 PFE相关寄存器说明 ............................................. 14   Contents 1 Required software and tools ...................................... 2 2 Master Demo compiling ............................................. 2 2.1 Install RTD_MCAL driver........................................ 2 2.2 Install PFE_MCAL driver ........................................ 3 2.3 Compile PFE master project .................................. 3 3 Change the demo to support RDB3 board RGMII port4 3.1 Hardware design .................................................... 4 3.2 Software modification ............................................. 5 4 Master DemoTest ...................................................... 7 4.1 Hardware design .................................................... 7 4.2 PFE_EMAC1(RGMII) test steps ............................. 7 5 Master Demo code flow ............................................. 8 6 Notes in integration .................................................. 11 6.1 PFE_PreInit .......................................................... 11 6.2 The GENCTRL1 configruation of S32G3 ............. 12 6.3 RX CLOCK relock ................................................ 13 7 Demo Debug suggestion ......................................... 14 7.1 PFE related registers ........................................... 14

I am using Adafruit LED stripes with 60 LED's per meter. Each LED integrates the W2812B controller. WS2812B uses a serial protocol, and you can control each LED individually. The strip is made of flexible PCB material, and comes with a weatherproof sheathing.   https://www.adafruit.com/products/1138   WS2812B is an intelligent control LED light source that the control circuit and RGB chip are integrated in a package.   The data transfer protocol use single NZR communication mode. After the pixel power-on reset, the DIN port receive data from controller, the first pixel collects initial 24bit data, then send to the internal data latch, the other data is sent to the next cascade pixel through the DO port.   LED's in cascade: My LED panel uses 16 rows x 30 columns = 480 leds.   In a first approach, in order to generate the bit stream, a timer in PWM mode could be used and generate two different duty cycles for sending a "0" logic or "1" logic. Using PWM's + DMA can unload the CPU in the generation of each single bit. FlexIO module in the Kinetis K82 can do that in a very effective mode and generate 8 channels simultaneously.   But my objective is to unload the CPU as much as possible in the bit stream generation task and find an easy method of multiplexing the 8 FlexIO outputs. In this way, we can control more LED rows and get a minimum number of interrupts and CPU intervention.   I will use the FlexIO internal data shifters to send the data bit stream. One shifter for each row. As we only have 8 shifters, I can use external multiplexor to increase the number of rows. Unloading the CPU for the LED refresh process, we can mux several rows in each shifter output. The limit of LED’s will be the refresh time of the full panel.   FlexIO block diagram:     How are the "1" and "0" generated?   Each pixel needs 24 bits of Red-Green-Blue value (RGB)   For each row, I need to send 30 x 24 bits of RGB information. But I have to encode the data in the NZR/PWM protocol. I use a lookup table to transform 24 bpp information in 24 x 3 = 72 bits per pixel.     In this way the  DMA can send 30 x 24 x 3 = 1440 bits (A full row)  in 60 transfers of 24 bits into the shifter. We get only one DMA interrupt for each row:       Multiplexer implementation:       Frame Buffer LED:   typedef union { uint32_t  rgb;     struct{       uint8_t  b;       uint8_t  r;         uint8_t  g;       uint8_t  a;     }bytes; }ledrgb;   Extended LED encoded data:   typedef struct {   uint32_t g;   uint32_t r;   uint32_t b; }ledrgb_ext;     Lookup Table:   void init_conv_matrix(void) { videoconv[0]=0x92492400; videoconv[1]=0x92492600; videoconv[2]=0x92493400; videoconv[3]=0x92493600; videoconv[4]=0x9249A400; videoconv[5]=0x9249A600; videoconv[6]=0x9249B400; videoconv[7]=0x9249B600; videoconv[8]=0x924D2400; videoconv[9]=0x924D2600; videoconv[10]=0x924D3400; ... };   Part 3: Software for LED Panel emulation Or Return to Project page: LED Panel control with FlexIO

Overview NXP ®  offers solutions for the growing unmanned vehicle market in both civil and defense designs, supporting functions such as control, motion, vision, navigation, and communication. Target applications include: Unmanned Aerial Vehicle Unmanned Ground Vehicle Unmanned Underwater Vehicle Construction, demolition, inspection, or mining robot Firefighting or rescue robot Reference Designs NXP Product Link PX4 Robotic Drone FMU https://www.nxp.com/design/designs/px4-robotic-drone-fmu-rddrone-fmuk66:RDDRONE-FMUK66  KV Series Quad Motor Control https://www.nxp.com/design/designs/kv-series-quad-motor-control:KINETIS-DRONE-REFERENCE-DESIGN Block Diagram Recommended Products NXP Product Link MCU Kinetis® V Series: Real-time Motor Control & Power Conversion MCUs based on Arm® Cortex®-M0+/M4/M7 | NXP  LPC54000|Power Efficient 32-bit Microcontrollers (MCUs)|Cortex®-M4 Core | NXP  i.MX RT1060 MCU/Applications Crossover MCU | Arm® Cortex®-M7, 1MB SRAM | NXP  i.MX 6Solo Applications Processors | Single Arm® Cortex®-A9 @ 1GHz | NXP  i.MX 6Dual Applications Processors | Dual Arm® Cortex®-A9 @1.2GHz | NXP  i.MX 6Quad Applications Processors | Quad Arm® Cortex®-A9 | NXP  Wireless Connectivity Bluetooth®Smart/Bluetooth Low Energy | NXP  Interfaces In-Vehicle Network | NXP  I²C, SPI, Serial Interface Devices | NXP  USB Interfaces | NXP  NFC Reader NFC Readers | NXP  Wireless Power Wireless Power | NXP  Motor Driver GD3000 |3-phase Brushless Motor Pre-Driver | NXP  Voltage Regulator Linear Voltage Regulators | NXP  Switch Detector Signal Conditioners | NXP  Sensors Sensors | NXP  Tools and Software NXP Product Link i.MX RT1060 Evaluation Kit i.MX RT1060 Evaluation Kit | NXP  i.MX RT1020 Evaluation Kit i.MX RT1020 Evaluation Kit | NXP  SABRE Board for Smart Devices Based on the i.MX 6Quad Applications Processors i.MX 6Quad SABRE Development Board | NXP  i.MX RT1064 Evaluation Kit i.MX RT1064 Evaluation Kit | NXP  Kinetis® KV3x TWR-KV31F120M|Tower System Board|Kinetis® MCUs | NXP  i.MX RT1015 i.MX RT1015 Evaluation Kit | NXP  3-Phase Motor Control Low-Voltage, 3-Phase Motor Control Tower System Module | NXP  i.MX RT1050 Evaluation Kit i.MX RT1050 Evaluation Kit | NXP  NXP HoverGames drone kit including RDDRONE-FMUK66 and peripherals KIT-HGDRONEK66: NXP drone kit | NXP  Kinetis KV4x TWR-KV46F150M|Tower System Board|Kinetis MCUs | NXP  BSP, Drivers, and Middleware NXP Product Link Android OS for i.MX Applications Processors Android OS for i.MX Applications Processors | NXP  Embedded Linux for i.MX Applications Processors Embedded Linux for i.MX Applications Processors | NXP  MCUXpresso Software Development Kit (SDK) MCUXpresso SDK | Software Development for Kinetis, LPC, and i.MX MCUs | NXP  MCUXpresso Config Tools - Pins, Clocks, Peripherals MCUXpresso Config Tools|Software Development for NXP Microcontrollers (MCUs) | NXP 

Overview This reference design describes the design of a 3-phase BLDC (Brushless DC) motor drive, which supports the NXP® 56F80X and 56F83XX Digital Signal Controllers (DSCs). The speed-closed loop BLDC drive using an encoder sensor is implemented The system is targeted for applications in both industrial and appliance fields (e.g. washing machines, compressors, air conditioning units, pumps or simple industrial drives required high reliability and efficiency) Features Voltage control of BLDC motor using Encoder sensor Targeted for 56F80X, 56F83XX, and 56F81XX Digital Signal Controllers Running on 3-phase Motor Board Control technique incorporates: Voltage BLDC motor control with speed-closed loop Current feedback loop Both directions of rotation Motoring mode Minimal speed 500 RPM Maximal speed 1000 RPM (limited by power supply) Manual interface (Start/Stop switch, Up/Down push button control, LED indication) FreeMASTER software control interface (motor start/stop, speed set-up) FreeMASTER software monitor Block Diagram Board Design Resources

Speed development time when designing your portable medical device with NXP's Healthcare Analog Front End (AFE) reference platform which includes a complete hardware platform, schematics and software.  Based on the Kinetis Microcontroller K53 measurement. Demo Owner: dr.josefernandezv Demo Owner: aleguzman Features Speed development time when designing your portable medical device with NXP's Healthcare Analog Front End (AFE) reference platform which includes a complete hardware platform, schematics and software NXP offers a complete development platform based on the Tower System, which eases the development of medical applications with a fully integrated set of solutions that reduces the design effort The Medical suitcase is composed of six different analog front ends, each one focused on a specific medical application. Applications included are, 1-Lead ECG, pulse oximeter, blood pressure monitor, glucometer, spirometer, and ultrasound digital stethoscope Featured NXP Products K50_100: Kinetis K50 Measurement 100 MHz MCUs Healthcare Analog Front End( AFE) Block Diagram

this doc and project explain how to integrate S32G M stby demo and Linux STR demo to one demo to achieve the fast boot, chinese version: 本文说明如何在S32G2 RDB2板上搭建 一个M7 MCAL Standby Fullboot GPIO resume Demo加A53 Suspend to RAM的Demo，主要的 应用场景是电动汽车的快速启动。 G3与更新版本BSP的支持情况与此类 似，不再另外说明，客户可以自行参考开发。 请注意本文为培训和辅助文档，本文不是 官方文档的替代，请一切以官方文档为准。     目录 1 参考资料说明与声明 .................................................. 2 2 STBY+STR的硬件注意点 .......................................... 3 3 修改M7 MCAL Standby Demo代码 ............................ 5 3.1 Clock相关修改 ........................................................ 5 3.2 MCU相关修改 ......................................................... 5 3.3 UART Clock相关修改 ............................................. 7 3.4 Port相关修改 .......................................................... 7 3.5 I2C相关修改 ........................................................... 7 3.6 实现M核进入STDY状态等待功能 ........................... 8 3.7 Main函数的修改 ..................................................... 8 4 修改Bootloader工程来支持同时Boot M/A核Demo ... 10 4.1 I2C Clock相关修改 ............................................... 10 4.2 Port相关修改 ........................................................ 11 4.3 其它修改 ............................................................... 12 5 修改A53 Linux代码 .................................................. 13 6 Demo 运行测试 ........................................................ 13 6.1 硬件连接 ............................................................... 13 6.2 镜像烧写 ............................................................... 13 6.3 Demo运行 ............................................................ 14 7 工程发布包............................................................... 15 8 未来开发建议 ........................................................... 17 8.1 M/A核同步机制 ..................................................... 17 8.2 功能安全与信息安全 ............................................. 17 9 遗留问题 .................................................................. 17 9.1 IPCF STR支持 ...................................................... 18 9.2 PFE Slave STR支持 ............................................. 18 注意以下说明与声明： 说明： 汽车网关有快速启动要求，而电动车因为驻车时有更大的电池提供待机电源，所以希望是使 用Linux 的suspend to ram 的功能来实现Linux 的快速启动，而在S32G 上则需要考虑将M 核的 Standby 功能 与A 核的STR 功能 结合起来，目前可用的资源包括：  从BSP32 起支持ATF，可以支持Linux 端的STR 功能，文档《S32G_Linux_STR_V1-*.pdf》 (John.Li)说明linux STR 的原理和与M7 Standby Demo 结合时所需要的修改。  NXP 的M7 内部standby demo，可以支持M 核端的standby 功能，支持full boot 和standby ram boot。文档《S32G_Standby_Demo_V4-*.pdf》(John.Li)有详细说明，本文使用MCAL full boot+GPIO resume Demo。  本Demo 与本文主要说明如何将这两个Demo 结合起来，形成一个整体的Demo。  由于需要Boot M 核加A 核，所以也需要Bootloader 工程的支持，文档 《S32G_Bootloader_V1-*.pdf》(John.Li)说明了如何创建一个MCAL sample 加Linux 的 Bootloader 工程。 声明： 请注意：  M7 standby demo 本来为NXP 内部Demo，不保证运行质量。而Linux 本身也是reference software。  Linux STR 本身会引入比较复杂的电源管理切换，也会引起系统级的不稳定性。  本文所说的方法也是实验性质，不保证运行质量。 所以客户应该谨慎决定其产品功能并自行保证其产品质量，本文及本Demo 仅为Demo 性质。   This article explains how to build a demo of M7 MCAL Standby Fullboot GPIO resume Demo plus A53 Suspend to RAM on the S32G2 RDB2 board. The main application scenario is the quick start of electric vehicles. The support situation of G3 and the newer version of BSP is similar to this, no further explanation is given, customers can refer to it for development by themselves.  Please note that this article is a training and auxiliary document. This article is not a substitute for the official document. Please refer to the official document. Contents 1    Reference materials and statement 2 2    STBY+STR hardware checkpoints. 3 3    Modified M7 MCAL Standby Demo codes. 5 3.1  Clock modification. 5 3.2  MCU related modification. 6 3.3  UART Clock related modificaiton. 7 3.4  Port related modification. 8 3.5  I2C related modification. 8 3.6  Enable the waiting function of M core entering STDY. 9 3.7  Main function modification. 9 4    Modify the Bootloader project to support simultaneous M/A core demo  11 4.1  I2C Clock related modification. 11 4.2  Port related modifcaiton. 11 4.3  Others modificaiton. 13 5    Modify A53 Linux codes. 14 6    Demo running and testing. 14 6.1  Hardware link. 14 6.2  Image burning. 14 6.3  Demo running. 15 7    Project release package. 16 8    Suggestion for the future development 17 8.1  M/A core sync mechanism.. 17 8.2  Function safety and Information security. 17 9    Remaining issues. 18 9.1  IPCF STR support 18 9.2  PFE Slave STR support 18   as need refer:   S32G_Linux STR This doc explain S32G Linux STR details and modify to integrate with M stdy demo https://community.nxp.com/t5/NXP-Designs-Knowledge-Base/S32G-Linux-STR/ta-p/1652680 S32G Standby Demo the project build a new Mcal standby demo and explain its details https://community.nxp.com/t5/NXP-Designs-Knowledge-Base/S32G-M-kernel-Standby-demo-and-how-to-porting-to-Mcal/ta-p/1556313 S32G Boot customization doc how to run bootloader to run mcal&linux https://community.nxp.com/t5/NXP-Designs-Knowledge-Base/S32G-Bootloader-Customzition/ta-p/1519838