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EUF-ACC-T1573 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 本次会议将介绍如何区分飞思卡尔电源管理解决方案并将其连接到大多数飞思卡尔 MCU 和 MPU,以实现物联网、汽车和多市场应用中的完整系统支持。凭借针对交通运输、能源管理和楼宇控制领域工业应用的完整 MCU 工具协调策略,我们可以为您的客户提供最快的产品上市时间。演示将包括与 MCU 无关的模拟软件驱动程序的现场演示,以便在您下次拜访客户时更好地定位飞思卡尔模拟系统解决方案。 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 本次会议将介绍如何区分飞思卡尔电源管理解决方案并将其连接到大多数飞思卡尔 MCU 和 MPU,以实现物联网、汽车和多市场应用中的完整系统支持。凭借针对交通运输、能源管理和楼宇控制领域工业应用的完整 MCU 工具协调策略,我们可以为您的客户提供最快的产品上市时间。演示将包括与 MCU 无关的模拟软件驱动程序的现场演示,以便在您下次拜访客户时更好地定位飞思卡尔模拟系统解决方案。
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Getting Started with eIQ Time Series Studio This lab will walk through how to use eIQ Time Series Studio (TSS) to create time series models for embedded microcontrollers.  It covers how to import time series data, shows how the tool can generate multiple machine learning (ML) algorithms, and describes how to deploy those generated models to your development board. eIQ Time Series Studio is now available as a standalone installer.  This lab uses the FRDM-MCXN947 but the same steps will apply to any of the devices supported by eIQ Time Series Studio: MCX FRDM-MCXA156 FRDM-MCXC444 FRDM-MCXE247 FRDM-MCXN236 FRDM-MCXN947 FRDM-MCXW71 i.MX RT i.MXRT700-EVK i.MXRT685-EVK i.MXRT595-EVK MIMXRT1060-EVK MIMXRT1170-EVK MIMXRT1180-EVK i.MX6 MCIMX6ULL-EVK i.MX8 8MPLUSLPD4-PEVK i.MX9 i.MX93EVK RW FRDM-RW612 LPC LPC55S69-EVK Kinetis FRDM-K66F FRDM-KV31F FRDM-K32L3A6 DSC MC56F83000-EVK MC56F80000-EVK The labs are written for either VS Code or MCUXpresso IDE, but the same concepts can be used for other IDEs. TSS can be accessed via an on-prem PC application or by using the web version in your browser. You can also view the video below for a quick overview of the Time Series Studio process.  (function() { var wrapper = document.getElementById('lia-vid-6390665301112w960h540r208'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos) Also check out the ML Universal Datalogger on the App Code Hub for a tool to collect sensor data that can be used with the Time Series Studio, as well as the Time Series Studio examples on App Code Hub. Also see this document for details on how to add TSS libraries to existing projects.  --- Updated June 2026 for TSS 2.0.5 release i.MX RT
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RT600 MCUXpresso JLINK debug QSPI flash RT600 MCUXpresso JLINK debug QSPI flash 1 Introduction     MIMXRT600-EVK is the NXP official board, which onboard flash is the external octal flash, the octal flash is connected to the RT685 flexSPI portB. In practical usage, the customer board may use other flash types, eg QSPI flash, and connect to the FlexSPI A port. Recently, nxp published one RT600 customer flash application note: https://www.nxp.com/docs/en/application-note/AN13386.pdf This document mainly gives the CMSIS DAP related flash algorithm usage, which modifies the option data to generate the new flash algo for the different flash types. Some customer’s own board may use the RT600 QSPI flash+MCUXPresso+JLINK to debug the application code. Recently, one of the customers find on his own customer board, when they use debugger JLINK associated with the MCUXPresso download code to the RT600 QSPI flash, they meet download issues, but when using the CMSIS DAP as a debugger and the related QSPI cfx file, they can download OK. So this document mainly gives the experience of how to use the RT600, MCUXpresso IDE, and JLINK to download and debug the code which is located in the external QSPI flash. 2 JLINK driver prepare and test   MCUXpresso IDE use the JLINK download, it will call the JLINK driver related script and the flash algorithm, but to RT600, the JLINK driver will use the RT600 EVK flexSPI port B octal flash in default, so, if the customer board changes to other flexSPI port and to QSPI flash, they need to provide the related QSPI flash algorithm and script file, otherwise, even they can find the ARM CM33 core, the download will be still failed. If customers want to use the MCUXpresso IDE and the JLINK, they need to make sure the JLINK driver attached tool can do the external flash operation, eg, erase, read, write successfully at first. Now, give the JLINK driver related tool how to add the RT600 QSPI flash driver and script file. 2.1 JLINK driver install   Download the Segger JLINK driver from the following link: https://www.segger.com/downloads/jlink/JLink_Windows_V754b_x86_64.exe This document will use the jlink v7.54b to test, other version is similar. Install the driver, the default driver install path is: C:\Program Files\SEGGER 2.2 Universal flashloader RT-UFL    RT-UFL v1.0 is a universal flashloader, which uses one .FLM file for all i.MXRT chips, and the different external flash, it is mainly used for the Segger JLINK debugger. RT-UFL v1.0 downoad link: https://github.com/JayHeng/RT-UFL/archive/refs/tags/v1.0.zip    Now, to the RT600 QSPI, give the related flash algo file patch.    Copy the following path file: \RT-UFL-1.0\algo\SEGGER\JLink_Vxxx To the JLINK install path: \SEGGER\JLink Then copy the content in file: RT-UFL-master\test\SEGGER\JLink_Vxxx\Devices\NXP\iMXRT6xx\archive2\evkmimxrt685.JLinkScript To replace the content in: C:\Program Files\SEGGER\JLink\Devices\NXP\iMXRT_UFL\iMXRT6xx_CortexM33.JLinkScript Otherwise, the MCUXpresso IDE debug reset button function will not work. So, need to add the JLINKScript code for ResetTarget, which will reset the external flash. pic1 The RT-UFL provide 3 types download flash algo: MIMXRT600_UFL_L0, MIMXRT600_UFL_L1, MIMXRT600_UFL_L2. Pic 2 _L0 used for the QSPI Flash and Octal Flash(page size 256 Bytes, sector size 4KB), _L1/2 used for the hyper flash(Page size 512 Bytes,Sector size 4KB/64KB). The JLINKDevices.xml content also can get the detail information. Different name will call different .FLM, the .FLM is the flash algorithm file, the source code can be found in RT-UFL v1.0, it will use different option0 option1 to configure the different external memory when the memory chip can support SFDP. 2.3 JLINK commander test Please note, the device need to select as MIMXRT600_UFL_L0 when using the QSPI flash. Pic 3                                         pic 4 Pic 5 We can find, the JLINK command can realize the external QSPI flash read, erase function. 2.4 Jflash Test Operation steps: Target->connect->production programming Pic 6 We can find, the Jflash also can realize the RT600 external QSPI flash erase and program. Please note, not all the JLINK can support JFLASH, this document is using Segger JLINK plus. 3 MCUXpresso configuration and test MCUXpresso: v11.4.0 SDK_2_10_0_EVK-MIMXRT685 MCUXPresso IDE import the SDK project, eg. Helloworld or led_output. 3.1 QSPI FCB configuration    FCB is located from the flash offset address 0X08000400, which is used for the FlexSPI Nor boot configuration, the detailed content of the FCB can be found from the RT600 user manual Table 997. FlexSPI flash configuration block. Different external Flash, the configuration is different, if need to use the QSPI flash, the FCB should use the QSPI related configuration and its own LUT table.    Modify SDK project flash_config folder flash_config.c and flash_config.h, LUT contains fast read, status read, write enable, sector erase, block erase, page program, erase the whole chip. If the external QSPI flash command is different, the LUT command should be modified by following the flash datasheet mentioned related command. const flexspi_nor_config_t flexspi_config = { .memConfig = { .tag = FLASH_CONFIG_BLOCK_TAG, .version = FLASH_CONFIG_BLOCK_VERSION, .readSampleClksrc=kFlexSPIReadSampleClk_LoopbackInternally, .csHoldTime = 3, .csSetupTime = 3, .columnAddressWidth = 0, .deviceModeCfgEnable = 0, .deviceModeType = 0, .waitTimeCfgCommands = 0, .deviceModeSeq = {.seqNum = 0, .seqId = 0,}, .deviceModeArg = 0, .configCmdEnable = 0, .configModeType = {0}, .configCmdSeqs = {0}, .configCmdArgs = {0}, .controllerMiscOption = (0), .deviceType = 1, .sflashPadType = kSerialFlash_4Pads, .serialClkFreq = kFlexSpiSerialClk_133MHz, .lutCustomSeqEnable = 0, .sflashA1Size = BOARD_FLASH_SIZE, .sflashA2Size = 0, .sflashB1Size = 0, .sflashB2Size = 0, .csPadSettingOverride = 0, .sclkPadSettingOverride = 0, .dataPadSettingOverride = 0, .dqsPadSettingOverride = 0, .timeoutInMs = 0, .commandInterval = 0, .busyOffset = 0, .busyBitPolarity = 0, .lookupTable = { #if 0 [0] = 0x08180403, [1] = 0x00002404, [4] = 0x24040405, [12] = 0x00000604, [20] = 0x081804D8, [36] = 0x08180402, [37] = 0x00002080, [44] = 0x00000460, #endif // Fast Read [4*0+0] = FLEXSPI_LUT_SEQ(CMD_SDR , FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), [4*0+1] = FLEXSPI_LUT_SEQ(MODE4_SDR, FLEXSPI_4PAD, 0x00, DUMMY_SDR , FLEXSPI_4PAD, 0x09), [4*0+2] = FLEXSPI_LUT_SEQ(READ_SDR , FLEXSPI_4PAD, 0x04, STOP_EXE , FLEXSPI_1PAD, 0x00), //read status [4*1+0] = FLEXSPI_LUT_SEQ(CMD_SDR , FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), //write Enable [4*3+0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP_EXE, FLEXSPI_1PAD, 0), // Sector Erase byte LUTs [4*5+0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18), // Block Erase 64Kbyte LUTs [4*8+0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18), //Page Program - single mode [4*9+0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18), [4*9+1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x0), //Erase whole chip [4*11+0]= FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP_EXE, FLEXSPI_1PAD, 0), }, }, .pageSize = 0x100, .sectorSize = 0x1000, .ipcmdSerialClkFreq = 1, .isUniformBlockSize = 0, .blockSize = 0x10000, }; This code has been tested on the RT685+ QSPI flash MT25QL128ABA1ESE, the code boot is working. 3.2 Debug configuration Configure the JLINK options in the MCUXpresso IDE as the JLINK driver: JLinkGDBServerCL.exe Windows->preferences Pic 7 Press debug, generate .launch file. Pic 8 Run->Debug configurations           Pic 9 Choose the device as MIMXRT600_UFL_L0, if the SWD wire is long and not stable, also can define the speed as the fixed low frequency. 3.3 Download and debug test Before download, need to check the RT685 ISP mode configuration, as this document is using the 4 wire QSPI and connect to the FlexSPI A port, so the ISP boot mode should be FlexSPI boot from Port A: ISP2 PIO1_17 low, ISP1 PIO1_16 high, ISP0 PIO1_15 high Click debug button, we can see the code enter the debug mode, and enter the main function, the code address is located in the flexSPI remap address. Pic 10 Click run, we can find the RT685 pin P0_26 is toggling, and the UART interface also can printf information. The application code is working. 4 External SPI flash operation checking To the customer designed board, normally we will use the JLINK command to check whether it can find the ARM core or not at first, make sure the RT chip can work, then will check the external flash operation or not. 4.1 SDK IAP flash code test We can use the SDK related code to test the external flash operation or not at first, the SDK code path is: SDK_2_10_0_EVK-MIMXRT685\boards\evkmimxrt685\driver_examples\iap\iap_flash Then, check the external flash, and modify the code’s related option0, option1 to match the external flash. About the option 0 and option1 definition, we can find it from the RT600 user manual Table 1004.Option0 definition and Table 1005.Option1 definition Pic 11 Pic 12 To the external QSPI flash which is connected to the FLexSPI portA, we can modify the option to the following code:     option.option0.U = 0xC0000001;//EXAMPLE_NOR_FLASH;     option.option1.U = 0x00000000;//EXAMPLE_NOR_FLASH_OPTION1; Then burn the IAP_flash project to the RT685 internal RAM, debug to run it. Pic 13 We can find, the external QSPI flash initialization, erase, read and write all works, and the memory also can find the correct data. 4.2 MCUBootUtility test   Chip enter the ISP mode, then use the MCUBootUtility tool to connect the RT685 and QSPI flash, to do the application code program and read test. ISP mode:ISP2:high, ISP1: high ISP0 low Configure FlexSPI NOR Device Configuration as QSPI, we can use the template: ISSI_IS25LPxxxA_IS25WPxxxA. Pic 14 Click connect to ROM button, check whether it can recognize the external flash: Pic 15 After connection, we can use the tool attached RT685 image to download: NXP-MCUBootUtility-3.3.1\apps\NXP_MIMXRT685-EVK_Rev.E\led_blinky_0x08001000_fdcb.srec Pic 16 We can find, the connection, erase, program and read are all work, it also indicates the RT685+external QSPI flash is working. Then can go to debug it with IDE and debugger. i.MXRT 600
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S32G LLCE CAN Linux Driver Test Chinese Version. 本文说明S32G LLCE CAN Linux驱动的 快速测试方法。 目录 1 参考资料 .................................................................... 2 1.1 参考资料 ................................................................. 2 1.2 版本匹配说明 .......................................................... 2 2 环境搭建 .................................................................... 3 2.1 使用Yocto编译 ........................................................ 3 2.2 使用Standalone编译 ............................................... 4 3 测试 ........................................................................... 5 3.1 硬件连接 ................................................................. 5 3.2 测试方法 ................................................................. 6 4 LLCE CAN Linux驱动说明 ......................................... 7 4.1 DTS ........................................................................ 7 4.2 源代码 .................................................................... 9 Automotive
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i.MX6UL/ULL/ULZ DRAM Register Programming Aids Important: If you have any questions or would like to report any issues with the DDR tools or supporting documents please create a support ticket in the i.MX community. Please note that any private messages or direct emails are not monitored and will not receive a response.   This is the detailed programming aid for the registers associated with DRAM initialization (DDR3 and LPDDR2) of the MX6UL/ULL/ULZ (consolidated RPA). The last work sheet tab in the tool formats the register settings for use with the ARM DS5/RealView debugger. It can be manually converted by the user to a DCD file format used by uboot or other bootloaders (note the removal of debugger specific commands in this tab). The programming aids were developed for internal NXP validation and development boards. This tool serves as an aid to assist with programming the DDR interface of the MX6UL/ULL/ULZ and is based on the DDR initialization scripts developed by the R&D team and no guarantees are made by this tool. The following are some general notes regarding this tool: Refer to the "How To Use" tab in the tool as a starting point to use this tool. Note that in the "DStream .ds file" tab there are DS5 debugger specific commands that should be commented out or removed when using the DRAM initialization for non-debugger specific applications (like when porting to bootloaders). This tool may be updated on an as-needed basis for bug fixes or future improvements.  There is no schedule for aforementioned maintenance.   i.MX6 All i.MX6UL
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Falcon Mode Enablement - iMX8MP_EVK Hi, I need to enable Falcon Mode on iMX8MP_EVK in the Yocto branch 6.12-walnascar. However, as per the AN14641 document, the meta-imx-fastboot layer is available only in the lf-6.6.36-2.1.0-secure branch. How can I port this layer to my walnascar branch and enable Falcon Mode? Please help here.. Re: Falcon Mode Enablement - iMX8MP_EVK Please use the following command. uuu -b emmc_all - .rootfs.wic For example: $ uuu -b emmc_all imx-boot-imx95evk-sd.bin-flash_all     core-image-minimal-imx95evk.rootfs.wic Re: Falcon Mode Enablement - iMX8MP_EVK Hi Tipingwang, Thanks for your reply. I am trying to enable Falcon mode and have followed the steps provided in AN14641, but I am getting stuck during the flashing process. As per the README, the flashing steps are mentioned as below (for eMMC): unzstd -[secure-boot]- .rootfs.wic.zst uuu -b emmc_all - .rootfs.wic uuu -b emmc My boot memory is eMMC. I attempted to flash the image using the following command: sudo ./uuu -d -v -b emmc_all imx-boot-imx8mpevk-sd.bin-flash_evk imx-image-core-imx8mpevk.rootfs-20260616051114.wic However, during execution, the flashing process fails with the following error: sudo ./uuu -d -v -b emmc_all imx-boot-imx8mpevk-sd.bin-flash_evk imx-image-core-imx8mpevk.rootfs-20260616051114.wic uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.5.243-5-g124d086   Build in config: Pctl Chip Vid Pid BcdVersion Serial_No ================================================== SDPS: MX8QXP 0x1fc9 0x012f [0x0002..0xffff] SDPS: MX8QM 0x1fc9 0x0129 [0x0002..0xffff] SDPS: MX8DXL 0x1fc9 0x0147 SDPS: MX28 0x15a2 0x004f SDPS: MX815 0x1fc9 0x013e SDPS: MX865 0x1fc9 0x0146 SDPS: MX8ULP 0x1fc9 0x014a SDPS: MX8ULP 0x1fc9 0x014b SDPS: MX93 0x1fc9 0x014e SDPS: MX91 0x1fc9 0x0159 SDPS: MX95 0x1fc9 0x015d SDPS: MX95 0x1fc9 0x015c SDPS: MX943 0x1fc9 0x0027 SDPS: MX952 0x1fc9 0x0028 SDP: MX7D 0x15a2 0x0076 SDP: MX6Q 0x15a2 0x0054 SDP: MX6D 0x15a2 0x0061 SDP: MX6SL 0x15a2 0x0063 SDP: MX6SX 0x15a2 0x0071 SDP: MX6UL 0x15a2 0x007d SDP: MX6ULL 0x15a2 0x0080 SDP: MX6SLL 0x1fc9 0x0128 SDP: MX7ULP 0x1fc9 0x0126 SDP: MXRT106X 0x1fc9 0x0135 SDP: MX8MM 0x1fc9 0x0134 SDP: MX8MQ 0x1fc9 0x012b SDPU: SPL 0x0525 0xb4a4 [0x0000..0x04ff] SDPV: SPL1 0x0525 0xb4a4 [0x0500..0x9998] SDPV: SPL1 0x1fc9 0x0151 [0x0500..0x9998] SDPU: SPL 0x0525 0xb4a4 [0x9999..0x9999] SDPU: SPL 0x3016 0x1001 [0x0000..0x04ff] SDPV: SPL1 0x3016 0x1001 [0x0500..0x9998] FBK: 0x066f 0x9afe FBK: 0x066f 0x9bff FBK: 0x1fc9 0x0153 FB: 0x0525 0xa4a5 FB: 0x18d1 0x0d02 FB: 0x3016 0x0001 FB: 0x1fc9 0x0152 FB: 0x0483 0x0afb FB: 0x1d6b 0x0104   Run built-in script:   uuu_version 1.4.149   # @_flash.bin            | bootloader, which can extract from wic image # @_image   [_flash.bin] | wic image burn to emmc.     # This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ SDP: boot -f imx-boot-imx8mpevk-sd.bin-flash_evk -scanlimited 0x800000   # This command will be run when ROM support stream mode # i.MX8QXP, i.MX8QM SDPS: boot -scanterm -f imx-boot-imx8mpevk-sd.bin-flash_evk -scanlimited 0x800000   # These commands will be run when use SPL and will be skipped if no spl # SDPU will be deprecated. please use SDPV instead of SDPU # { SDPU: delay 1000 SDPU: write -f imx-boot-imx8mpevk-sd.bin-flash_evk -offset 0x57c00 SDPU: jump -scanlimited 0x800000 # }   # These commands will be run when use SPL and will be skipped if no spl # if (SPL support SDPV) # { SDPV: delay 1000 SDPV: write -f imx-boot-imx8mpevk-sd.bin-flash_evk -skipspl -scanterm -scanlimited 0x800000 SDPV: jump -scanlimited 0x800000 # }     FB: ucmd setenv fastboot_dev mmc FB: ucmd setenv mmcdev ${emmc_dev} FB: ucmd mmc dev ${emmc_dev} FB: flash -raw2sparse all imx-image-core-imx8mpevk.rootfs-20260616051114.wic FB: flash -scanterm -scanlimited 0x800000 bootloader imx-boot-imx8mpevk-sd.bin-flash_evk FB: ucmd if env exists emmc_ack; then ; else setenv emmc_ack 0; fi; FB: ucmd mmc partconf ${emmc_dev} ${emmc_ack} 1 0 FB: done     Wait for Known USB Device Appear... New USB Device Attached at 1:2-152E1000D9DE520A 1:2-152E1000D9DE520A>Start Cmd:SDPS: boot -scanterm -f imx-boot-imx8mpevk-sd.bin-flash_evk -scanlimited 0x800000 14%1:2-152E1000D9DE520A>Fail HID(W): LIBUSB_ERROR_TIMEOUT (-7)(20.07s) The detailed uuu logs are attached above for reference. Could you please guide me on the correct procedure to flash a Falcon-enabled OS into eMMC, or let me know if I am missing any required steps or configurations? Thanks in advance for your support. Re: Falcon Mode Enablement - iMX8MP_EVK Falcon Mode is not incompatible with Secure Boot BUT On lf-6.12.20-2.0.0-secure, you cannot enable Secure Boot together with Falcon Mode using the provided Yocto flow About 0001-imx8m-reset-ethernet-phy-in-spl.patch For i.MX8MP EVK → strongly recommended Not strictly required if you don't use Ethernet during early boot Re: Falcon Mode Enablement - iMX8MP_EVK Hi Yiping Wang, Thank you for your response. I have a couple of additional questions for clarification. According to the information provided, the branch lf-6.12.20-2.0.0-secure supports Falcon Mode v2, but Secure Boot is marked as not yet supported. Since Secure Boot is a requirement for my i.MX8MP platform, will Falcon Mode work correctly if I use this branch, or is Falcon Mode incompatible when Secure Boot is enabled? For the i.MX8MP EVK, do I need to apply the patch 0001-imx8m-reset-ethernet-phy-in-spl.patch, or is it optional depending on the use case? Re: Falcon Mode Enablement - iMX8MP_EVK You probably do not need to port the layer from lf-6.6.36-2.1.0-secure yourself. The public nxp-imx-support/meta-imx-fastboot - GitHub repository already shows a lf-6.12.20-2.0.0-secure branch. Please refer to README in https://github.com/nxp-imx-support/meta-imx-fastboot Re: Falcon Mode Enablement - iMX8MP_EVK Please help here, And i am using UUU to flash eMMC Re: Falcon Mode Enablement - iMX8MP_EVK As per this image i found in NXP forum it seems that flashing eMMC using the UUU tool may not be supported in this case. Could you please suggest the appropriate method to flash an eMMC device with a Falcon-enabled OS? In your previous reply, you suggested using the following command:   - .rootfs.wic> I tried this approach, but I encountered the same error again: Fail HID(W): LIBUSB_ERROR_TIMEOUT (-7) (20.07s) Could you please guide me on the correct flashing procedure or any alternative tools or steps required for flashing eMMC with Falcon mode enabled? Re: Falcon Mode Enablement - iMX8MP_EVK I verified the following commands on IMX95FRDM, there is no problem, please refer to my log. C:\Users\nxa22585>C:\Users\nxa22585\Downloads\i.mx95\uuu.exe -lsusb uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.5.243-0-g230f1b1 Connected Known USB Devices Path Chip Pro Vid Pid BcdVersion Serial_no ==================================================================== 2:4 MX95 SDPS: 0x1FC9 0x015D 0x0002 61F49AAB2DCB4DDF C:\Users\nxa22585>C:\Users\nxa22585\Downloads\i.mx95\uuu.exe -b emmc_all C:\Users\nxa22585\Downloads\i.mx95\imx-boot-imx95-15x15-lpddr4x-frdm-sd.bin-flash_all C:\Users\nxa22585\Downloads\i.mx95\core-image-minimal-imx8mnevk.rootfs.wic uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.5.243-0-g230f1b1 Success 1 Failure 0 1:2-61F49AAB 8/ 8 [Done ] FB: done 2:4-61F49AAB 3/ 3 [=================100%=================] SDPV: jump -scanlimited 0x800000 C:\Users\nxa22585> Re: Falcon Mode Enablement - iMX8MP_EVK Please help here i have stucked in this part Re: Falcon Mode Enablement - iMX8MP_EVK In previous reply you gave a reference command for IMX95FRDM is that falcon enabled?  Here you can find what i was done in Yocto - IMX8MP 1) meta-imx-fastboot - lf-6.12.20-2.0.0-secure - Github_Link 2) Added this meta to my source - Github_Link 3) And followed all the instruction gave by  AN14641 document. 4)Bitbake commands that i followed:  bitbake -c clean linux-imx && bitbake -c clean imx-boot && bitbake -c clean u-boot-imx && bitbake -c clean imx-atf && bitbake -c clean imx-image-core  bitbake -c compile linux-imx && bitbake -c compile imx-boot && bitbake -c compile u-boot-imx && bitbake -c compile imx-atf && bitbake -c compile imx-image-core bitbake linux-imx && bitbake imx-boot && bitbake u-boot-imx && bitbake imx-atf && bitbake imx-image-core 5)  CASE 1: sudo ./uuu -b emmc_all imx-image-core-imx8mpevk.rootfs-20260617095251.wic uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.5.243-5-g124d086 Success 0 Failure 0 1:2-152E1000 1/ 1 [=================100%=================] SDPS: boot -scanterm -f /home/smurugan8/YOCTO/LWT/image/imx-image-core-imx8mpevk.rootfs-20260617095251.wic -scanlimited 0x800000 CASE 2:  sudo ./uuu -b emmc_all imx-boot-imx8mpevk-sd.bin-flash_evk imx-image-core-imx8mpevk.rootfs-20260617095251.wic uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.5.243-5-g124d086 Success 0 Failure 1 1:2-152E1000 1/ 1 [HID(W): LIBUSB_ERROR_TIMEOUT (-7) ] SDPS: boot -scanterm -f imx-boot-imx8mpevk-sd.bin-flash_evk -scanlimited 0x800000 IMPORTANT : I NEED TO FLASH A FALCON ENABLED OS INTO eMMC  Re: Falcon Mode Enablement - iMX8MP_EVK Please note uuu is only used to program images to emmc, it doesn't check the content of your images. I suspect there is problem with your uuu command itself. Where did you download uuu? Please download the latest UUU from https://github.com/nxp-imx/mfgtools/releases Please download the Windows version UUU to do verification. Re: Falcon Mode Enablement - iMX8MP_EVK Hi yipingwan I also tried using the UUU tool on Windows, but I am seeing the same result—it still does not work for flashing eMMC.  I have attached the UUU -log. However, when I flash the same Falcon-enabled OS to an SD card, it boots and works correctly. This confirms that the image itself and the Falcon configuration are valid. My question is: Why am I unable to flash this Falcon-enabled image to eMMC, even though the same image works from SD? Is there any alternative or recommended method to flash a Falcon-enabled OS to eMMC, other than using UUU? Could you please advise on the supported or reliable procedure for flashing eMMC in this scenario? Re: Falcon Mode Enablement - iMX8MP_EVK Please help here. Re: Falcon Mode Enablement - iMX8MP_EVK Please execute the following command with your Windows version UUU and send the result to me to do more investigation. uuu.exe -b emmc_all imx-boot-imx8mpevk-sd.bin-flash_evk   imx-image-core-imx8mpevk.rootfs-20260617095251.wic Re: Falcon Mode Enablement - iMX8MP_EVK Please try the following command uuu.exe -b emmc_all  C:\Users\vvdn\Sanjiv\Falcon\imx-boot-imx8mpevk-sd.bin-flash_evk C:\Users\vvdn\Sanjiv\Falcon\imx-image-multimedia-imx8mpevk.rootfs-20260624074743.wic Then send the result to me again. Re: Falcon Mode Enablement - iMX8MP_EVK Here you can find the output, PS C:\Users\vvdn\Sanjiv\uuu_source-uuu_1.5.243\uuu-uuu_1.5.243\uuu> .\uuu.exe -b emmc_all C:\Users\vvdn\Sanjiv\Falcon\imx-boot-imx8mpevk-sd.bin-flash_evk C:\Users\vvdn\Sanjiv\Falcon\imx-image-multimedia-imx8mpevk.rootfs-20260624074743.wic uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.5.243-0-g230f1b1 Success 0 Failure 1 1:3-152E1000 1/ 1 [HID(W): LIBUSB_ERROR_TIMEOUT (-7) ] SDPS: boot -scanterm -f C:\Users\vvdn\Sanjiv\Falcon\imx-b... Re: Falcon Mode Enablement - iMX8MP_EVK I above you can find the log of UUU,  Command=> .\uuu.exe -b emmc C:\Users\vvdn\Sanjiv\Falcon\imx-boot-imx8mpevk-sd.bin-flash_evk C:\Users\vvdn\Sanjiv\Falcon\imx-image-multimedia-imx8mpevk.rootfs-20260624074743.wic But it is not working in eMMC , Same Image will work in SD Card Re: Falcon Mode Enablement - iMX8MP_EVK I verified on IMX8MP_EVK target board, there is no problem to program emmc, please refer to my following log. C:\Users\nxa22585>C:\Users\nxa22585\Downloads\i.mx95\uuu.exe -b emmc_all C:\Users\nxa22585\Downloads\i.mx95\imx-boot-imx8mpevk-sd.bin-flash_evk C:\Users\nxa22585\Downloads\i.mx95\core-image-minimal-imx8mnevk.rootfs.wic uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.5.243-0-g230f1b1 Success 1 Failure 0 2:4-0F0B9800 8/ 8 [Done ] FB: done C:\Users\nxa22585> Please extracted my image from the attached file, and only execute the following command. uuu.exe -b emmc imx-boot-imx8mpevk-sd.bin-flash_evk If it still fails, it seems there is problem with EMMC itself on your target board. You could use the following emmc command to check whether you could write something to emmc in u-boot. Usage: mmc read addr blk# cnt mmc write addr blk# cnt mmc erase blk# cnt Re: Falcon Mode Enablement - iMX8MP_EVK Please only try whether you can write a default boot image to emmc with UUU. Re: Falcon Mode Enablement - iMX8MP_EVK Yes, @yipingwang, When I include the meta-imx-fastboot layer in my build, the flashing process gets stuck. However, if I remove the meta-imx-fastboot layer, I am able to flash the image to eMMC successfully. Re: Falcon Mode Enablement - iMX8MP_EVK I have one question @yipingwang it is falcon enabled image Re: Falcon Mode Enablement - iMX8MP_EVK Please help here.. @yipingwang Re: Falcon Mode Enablement - iMX8MP_EVK Please send /home/smurugan8/YOCTO/LWT/image/falcon_mode/imx-boot-imx8mpevk-sd.bin-flash_evk to me. I will do verification on my target board. Re: Falcon Mode Enablement - iMX8MP_EVK Hi @Sanjiv_Mns  The meta-secure-boot Yocto layer is not implemented for the 6.12.20 BSP. Since the meta-imx-fastboot layer depends on the meta-secure-boot, the branch lf-6.12.20-2.0.0-secure does not implement secure boot. The 0001-imx8m-reset-ethernet-phy-in-spl.patch patch is mandatory if you need to use the Ethernet interfaces in Linux. It resets the PHYs, without which the Linux driver cannot initialize the interfaces. Re: Falcon Mode Enablement - iMX8MP_EVK Please find the attachment . Re: Falcon Mode Enablement - iMX8MP_EVK Hi @yipingwang , I have done the commands which you gave in previous reply, here you can find the command logs & Boot logs COMMAND LOGS: sudo ./uuu -b emmc_all /home/smurugan8/YOCTO/LWT/image/default/imx-boot-imx8mpevk-sd.bin-flash_evk /home/smurugan8/YOCTO/LWT/image/default/imx-image-multimedia-imx8mpevk.rootfs-20260622071640.wic uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.5.243-5-g124d086 Success 1 Failure 0 1:1-152E1000 8/ 8 [Done ] FB: done sudo ./uuu -b emmc /home/smurugan8/YOCTO/LWT/image/default/imx-boot-imx8mpevk-sd.bin-flash_evk /home/smurugan8/YOCTO/LWT/image/falcon_mode/imx-boot-imx8mpevk-sd.bin-flash_evk uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.5.243-5-g124d086 Success 1 Failure 0 1:1-152E1000 7/ 7 [Done ] FB: Done BOOT LOGS: U-Boot SPL 2025.04-g44898b9f3cfe-dirty (Sep 03 2025 - 09:56:50 +0000) DDRINFO: start DRAM init DDRINFO: DRAM rate 4000MTS DDRINFO:ddrphy calibration done DDRINFO: ddrmix config done SEC0: RNG instantiated Normal Boot Trying to boot from MMC2 spl_load_image_fat: error reading image kernel-atf-dtb.itb, err - -5 spl_load_image_fat: error reading image u-boot-atf.itb, err - -5 Error: -2 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Re: Falcon Mode Enablement - iMX8MP_EVK Hi @Sanjiv_Mns  Falcon Mode images works on both SD and eMMC. To flash a Falcon image on eMMC/SD you need to: 1. Build the default bootloader. In a clean Yocto environment, run: bitbake imx-boot. Make sure the meta-imx-fastboot layer is not added at this step. This will generate the tmp/deploy/images/imx8mp-lpddr4-evk/imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evk default bootloader. 2. Build the falcon mode bootloader and the falcon mode image. Add the meta-imx-fastboot layer to your BBLAYERS. To compile the falcon mode bootloader, run: bitbake imx-boot This command will generate the tmp/deploy/images/imx8mp-lpddr4-evk/imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evk_dual_bootloader falcon bootloader. This bootloader contains only the SPL, without the U-Boot proper. When the meta-imx-fastboot layer is added, the *_dual_bootloader is generated. See layer.conf.   To compile the falcon mode image, run: bitbake imx-image-multimedia This will generate the tmp/deploy/images/imx8mp-lpddr4-evk/imx-image-multimedia-imx8mp-lpddr4-evk.rootfs.wic.zst image. 3. Use UUU to flash the image on the eMMC. UUU is the only tool available to flash images on the eMMC. uuu -b emmc_all imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evk imx-image-multimedia-imx8mp-lpddr4-evk.rootfs.wic.zst uuu -b emmc imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evk imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evk_dual_bootloader Re: Falcon Mode Enablement - iMX8MP_EVK Please remove bld-xwayland build folder to rebuild images. $ rm -rf bld-xwayland $ MACHINE=imx8mpevk DISTRO=fsl-imx-xwayland source ./imx-setup-release.sh -b bld-xwayland $ bitbake-layers add-layer ../sources/meta-imx-fastboot Please add the following line in bld-xwayland/conf/local.conf FALCON_KERNEL_BOOTARGS:mx8mp-generic-bsp = "console=ttymxc1,115200 root=/dev/mmcblk2p2 rootwait rw quiet" Then rebuild images: $ bitbake imx-boot $ bitbake core-image-minimal uuu.exe -b emmc_all imx-boot-imx8mpevk-sd.bin-flash_evk core-image-minimal-imx8mpevk.rootfs.wic uuu.exe -b emmc imx-boot-imx8mpevk-sd.bin-flash_evk imx-boot-imx8mpevk-sd.bin-flash_evk_falcon Please refer to my verification log: U-Boot SPL 2025.04-g9383f8387dc7-dirty (Jun 04 2025 - 09:48:20 +0000) DDRINFO: start DRAM init DDRINFO: DRAM rate 4000MTS DDRINFO:ddrphy calibration done DDRINFO: ddrmix config done SEC0: RNG instantiated Normal Boot Trying to boot from MMC2 Failed to find node!, err: -11! Failed to find node!, err: -11! NOTICE: Do not release JR0 to NS as it can be used by HAB NOTICE: BL31: v2.12.0(release):lf-6.12.20-2.0.0-dirty NOTICE: BL31: Built : 08:15:07, May 9 2025 [ 0.324123] imx8mp-ldb ldb-display-controller: Failed to create device link (0x180) with 32e90000.lcd-controller [ 0.395104] : mipi_csis_imx8mp_phy_reset, No remote pad found! [ 0.514210] imx8mp-ldb ldb-display-controller: Failed to create device link (0x180) with 1-004c [ 0.576883] imx8mp-ldb ldb-display-controller: Failed to create device link (0x180) with 1-004c [ 0.625848] ov5640 1-003c: ov5640_write_reg: error: reg=3008, val=42 [ 0.632862] ov5640 1-003c: ov5640_write_reg: error: reg=3103, val=11 [ 0.639669] ov5640 1-003c: ov5640_read_reg: error: reg=3108 [ 0.645268] ov5640 1-003c: failed to power on [ 0.661389] imx8mp-ldb ldb-display-controller: Failed to create device link (0x180) with phy-lvds [ 0.694937] [drm:drm_bridge_attach] *ERROR* failed to attach bridge /soc@0/bus@32c00000/mipi_dsi@32e60000 to encoder DSI-41: -19 [ 0.706570] imx_sec_dsim_drv 32e60000.mipi_dsi: Failed to attach bridge: 32e60000.mipi_dsi [ 0.714859] imx_sec_dsim_drv 32e60000.mipi_dsi: failed to bind sec dsim bridge: -19 NXP i.MX Release Distro 6.12-walnascar imx8mpevk ttymxc1 imx8mpevk login: root root@imx8mpevk:~# Re: Falcon Mode Enablement - iMX8MP_EVK Please use the following commands to program images to the target board with UUU. unzstd <image_name>-[secure-boot]-<machine_name>.rootfs.wic.zst uuu -b emmc_all <default_bootloader> <image_name>-<machine_name>.rootfs.wic uuu -b emmc <default_bootloader> <falcon_mode_bootloader>  The first parameter is the default bootloader, falcon mode bootloader is only specified in the second parameter of the second uuu command. Re: Falcon Mode Enablement - iMX8MP_EVK Hi @yipingwang & @elena_popa  Thank you so much for your support
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Exporting YOLO Models for NXP i.MX Platforms In this post, we will review the YOLO model export process for three popular NXP families: i.MX8MP, i.MX93, and i.MX95. These processors are increasingly used in edge AI applications such as smart vision, industrial automation, robotics, and intelligent HMI systems. Although they all support machine learning deployment, the export path, supported runtimes, and hardware acceleration options may differ depending on the device. The purpose of this guide is to provide a clearer starting point for developers who want to take a trained YOLO model and prepare it for execution on these i.MX platforms. Whether your workflow targets CPU, NPU. YOLO Model Export Workflow for i.MX Processors 1) Install Ultralytics Install or upgrade the Ultralytics package from PyPI: pip install -U ultralytics 2) Export the YOLO Model (TFLite INT8) Export your trained YOLO model to TensorFlow Lite (TFLite) format with INT8 quantization: yolo export model= .pt format=tflite int8=True Notes: The model must be exported in TFLite format and quantized to INT8. At this stage: The model can run on CPU for: i.MX8MP i.MX93 i.MX95 On i.MX8MP, this TFLite model can also be deployed to the NPU using the appropriate delegate. 3) i.MX93  Compile for Ethos-U NPU (Vela) For i.MX93, an additional compilation step is required to use the Ethos-U NPU. Run the Vela compiler to convert the TFLite model into an optimized format: vela .tflite --output-dir Notes: This step generates a model optimized for the Ethos-U NPU. The resulting output files are required for deployment using the NPU delegate on the i.MX93 platform. Please ensure that the model complies with the Ethos-U operator constraints, as only supported operations can be accelerated by the NPU. This command can be executed directly on the i.MX93 target, or alternatively by using the eIQ Toolkit (please refer to the eIQ Converter documentation for more details). 4)  i.MX95 Convert Model Using Neutron SDK For i.MX95, the model must be converted using the Neutron Converter, depending on the BSP version installed on your board. .\neutron-converter.exe ` --input " .tflite" ` --target imx95 ` --output " .tflite" ` --optimization-level OOpt Notes: The Neutron toolchain prepares the model for i.MX95 NPU acceleration. Supported formats and flags may vary depending on the Neutron SDK version. Always verify compatibility with your BSP release. You can check the compatibility details of the Neutron SDK in the "docs" folder of your downloaded Neutron SDK package. 5) Benchmark the Model After exporting and converting the model, you can validate performance using benchmarking tools. Typical options include: TFLite benchmark tool (CPU / delegate): benchmark_model --graph= .tflite --num_threads=X 6) Results iMX8MP CPU root@imx8mpevk:~# /usr/bin/tensorflow-lite-2.19.0/examples/benchmark_model --graph=yolov8n_full_integer_quant.tflite --mum_threads=4 INFO: STARTING! WARN: Unconsumed cmdline flags: --mum_threads=4 INFO: Log parameter values verbosely: [0] INFO: Graph: [yolov8n_full_integer_quant.tflite] INFO: Signature to run: [] INFO: Loaded model yolov8n_full_integer_quant.tflite INFO: Created TensorFlow Lite XNNPACK delegate for CPU. INFO: The input model file size (MB): 3.42652 INFO: Initialized session in 86.368ms. INFO: Running benchmark for at least 1 iterations and at least 0.5 seconds but terminate if exceeding 150 seconds. INFO: count=1 curr=1029584 p5=1029584 median=1029584 p95=1029584 INFO: Running benchmark for at least 50 iterations and at least 1 seconds but terminate if exceeding 150 seconds. INFO: count=50 first=986237 curr=985536 min=983921 max=993982 avg=985863 std=1497 p5=984152 median=985947 p95=986715 INFO: Inference timings in us: Init: 86368, First inference: 1029584, Warmup (avg): 1.02958e+06, Inference (avg): 985863 INFO: Note: as the benchmark tool itself affects memory footprint, the following is only APPROXIMATE to the actual memory footprint of the model at runtime. Take the information at your discretion. INFO: Memory footprint delta from the start of the tool (MB): init=11.207 overall=40.918 root@imx8mpevk:~# NPU root@imx8mpevk:~# /usr/bin/tensorflow-lite-2.19.0/examples/benchmark_model --graph=yolov8n_full_integer_quant.tflite --num_threads=4 --external_delegate_path=/usr/lib/libvx_delegate.so INFO: STARTING! INFO: Log parameter values verbosely: [0] INFO: Num threads: [4] INFO: Graph: [yolov8n_full_integer_quant.tflite] INFO: Signature to run: [] INFO: #threads used for CPU inference: [4] INFO: #threads used for CPU inference: [4] INFO: External delegate path: [/usr/lib/libvx_delegate.so] INFO: Loaded model yolov8n_full_integer_quant.tflite INFO: Vx delegate: allowed_cache_mode set to 0. INFO: Vx delegate: device num set to 0. INFO: Vx delegate: allowed_builtin_code set to 0. INFO: Vx delegate: error_during_init set to 0. INFO: Vx delegate: error_during_prepare set to 0. INFO: Vx delegate: error_during_invoke set to 0. INFO: EXTERNAL delegate created. INFO: Explicitly applied EXTERNAL delegate, and the model graph will be completely executed by the delegate. INFO: The input model file size (MB): 3.42652 INFO: Initialized session in 39.515ms. INFO: Running benchmark for at least 1 iterations and at least 0.5 seconds but terminate if exceeding 150 seconds. INFO: count=1 curr=16831746 p5=16831746 median=16831746 p95=16831746 INFO: Running benchmark for at least 50 iterations and at least 1 seconds but terminate if exceeding 150 seconds. INFO: count=50 first=67167 curr=67190 min=67048 max=67366 avg=67187 std=64 p5=67094 median=67184 p95=67295 INFO: Inference timings in us: Init: 39515, First inference: 16831746, Warmup (avg): 1.68317e+07, Inference (avg): 67187 INFO: Note: as the benchmark tool itself affects memory footprint, the following is only APPROXIMATE to the actual memory footprint of the model at runtime. Take the information at your discretion. INFO: Memory footprint delta from the start of the tool (MB): init=9.47266 overall=224.398 root@imx8mpevk:~# iMX93 CPU root@imx93evk:~# /usr/bin/tensorflow-lite-2.19.0/examples/benchmark_model --graph=yolov8n_full_integer_quant.tflite --num_threads=2 INFO: STARTING! INFO: Log parameter values verbosely: [0] INFO: Num threads: [2] INFO: Graph: [yolov8n_full_integer_quant.tflite] INFO: Signature to run: [] INFO: #threads used for CPU inference: [2] INFO: #threads used for CPU inference: [2] INFO: Loaded model yolov8n_full_integer_quant.tflite INFO: Created TensorFlow Lite XNNPACK delegate for CPU. INFO: The input model file size (MB): 3.42652 INFO: Initialized session in 57.963ms. INFO: Running benchmark for at least 1 iterations and at least 0.5 seconds but terminate if exceeding 150 seconds. INFO: count=3 first=247896 curr=198973 min=198973 max=247896 avg=215381 std=22991 p5=198973 median=199275 p95=247896 INFO: Running benchmark for at least 50 iterations and at least 1 seconds but terminate if exceeding 150 seconds. INFO: count=50 first=199533 curr=198880 min=197719 max=205262 avg=199032 std=1005 p5=198344 median=198886 p95=199961 INFO: Inference timings in us: Init: 57963, First inference: 247896, Warmup (avg): 215381, Inference (avg): 199032 INFO: Note: as the benchmark tool itself affects memory footprint, the following is only APPROXIMATE to the actual memory footprint of the model at runtime. Take the information at your discretion. INFO: Memory footprint delta from the start of the tool (MB): init=11.2539 overall=40.9961 root@imx93evk:~# NPU root@imx93evk:~# /usr/bin/tensorflow-lite-2.19.0/examples/benchmark_model --graph=yolov8n_full_integer_quant_vela.tflite --num_threads=2 --external_delegate_path=/usr/lib/libethosu_delegate.so INFO: STARTING! INFO: Log parameter values verbosely: [0] INFO: Num threads: [2] INFO: Graph: [yolov8n_full_integer_quant_vela.tflite] INFO: Signature to run: [] INFO: #threads used for CPU inference: [2] INFO: #threads used for CPU inference: [2] INFO: External delegate path: [/usr/lib/libethosu_delegate.so] INFO: Loaded model yolov8n_full_integer_quant_vela.tflite INFO: Ethosu delegate: device_name set to /dev/ethosu0. INFO: Ethosu delegate: cache_file_path set to . INFO: Ethosu delegate: timeout set to 60000000000. INFO: Ethosu delegate: enable_cycle_counter set to 0. INFO: Ethosu delegate: enable_profiling set to 0. INFO: Ethosu delegate: profiling_buffer_size set to 2048. INFO: Ethosu delegate: pmu_event0 set to 0. INFO: Ethosu delegate: pmu_event1 set to 0. INFO: Ethosu delegate: pmu_event2 set to 0. INFO: Ethosu delegate: pmu_event3 set to 0. INFO: EXTERNAL delegate created. INFO: EthosuDelegate: 8 nodes delegated out of 15 nodes with 8 partitions. INFO: Explicitly applied EXTERNAL delegate, and the model graph will be partially executed by the delegate w/ 8 delegate kernels. INFO: Created TensorFlow Lite XNNPACK delegate for CPU. INFO: The input model file size (MB): 2.9511 INFO: Initialized session in 638.148ms. INFO: Running benchmark for at least 1 iterations and at least 0.5 seconds but terminate if exceeding 150 seconds. INFO: count=7 first=87215 curr=81264 min=81079 max=87215 avg=82056.4 std=2107 p5=81079 median=81187 p95=87215 INFO: Running benchmark for at least 50 iterations and at least 1 seconds but terminate if exceeding 150 seconds. INFO: count=50 first=81497 curr=81232 min=80887 max=81783 avg=81153.1 std=178 p5=80921 median=81148 p95=81497 INFO: Inference timings in us: Init: 638148, First inference: 87215, Warmup (avg): 82056.4, Inference (avg): 81153.1 INFO: Note: as the benchmark tool itself affects memory footprint, the following is only APPROXIMATE to the actual memory footprint of the model at runtime. Take the information at your discretion. INFO: Memory footprint delta from the start of the tool (MB): init=7.36328 overall=8.73828 root@imx93evk:~# iMX95 CPU root@imx95evk:~# /usr/bin/tensorflow-lite-2.19.0/examples/benchmark_model --graph=yolov8n_full_integer_quant.tflite --num_threads=6 INFO: STARTING! INFO: Log parameter values verbosely: [0] INFO: Num threads: [6] INFO: Graph: [yolov8n_full_integer_quant.tflite] INFO: Signature to run: [] INFO: #threads used for CPU inference: [6] INFO: #threads used for CPU inference: [6] INFO: Loaded model yolov8n_full_integer_quant.tflite INFO: Created TensorFlow Lite XNNPACK delegate for CPU. INFO: The input model file size (MB): 3.42652 INFO: Initialized session in 35.268ms. INFO: Running benchmark for at least 1 iterations and at least 0.5 seconds but terminate if exceeding 150 seconds. INFO: count=7 first=115073 curr=74468 min=74170 max=115073 avg=80310.4 std=14192 p5=74170 median=74581 p95=115073 INFO: Running benchmark for at least 50 iterations and at least 1 seconds but terminate if exceeding 150 seconds. INFO: count=50 first=74143 curr=74135 min=73657 max=76392 avg=74346.9 std=447 p5=73829 median=74307 p95=75020 INFO: Inference timings in us: Init: 35268, First inference: 115073, Warmup (avg): 80310.4, Inference (avg): 74346.9 INFO: Note: as the benchmark tool itself affects memory footprint, the following is only APPROXIMATE to the actual memory footprint of the model at runtime. Take the information at your discretion. INFO: Memory footprint delta from the start of the tool (MB): init=11.5195 overall=40.8867 root@imx95evk:~# NPU: root@imx95evk:~# /usr/bin/tensorflow-lite-2.19.0/examples/benchmark_model --graph=yolov8n_full_integer_quant_neutron.tflite --num_threads=6 --external_delegate_path=/usr/lib/libneutron_delegate.so INFO: STARTING! INFO: Log parameter values verbosely: [0] INFO: Num threads: [6] INFO: Graph: [yolov8n_full_integer_quant_neutron.tflite] INFO: Signature to run: [] INFO: #threads used for CPU inference: [6] INFO: #threads used for CPU inference: [6] INFO: External delegate path: [/usr/lib/libneutron_delegate.so] INFO: Loaded model yolov8n_full_integer_quant_neutron.tflite INFO: EXTERNAL delegate created. INFO: NeutronDelegate delegate: 1 nodes delegated out of 33 nodes with 1 partitions. INFO: Neutron delegate version: v1.0.0-7399a58e, zerocp enabled. INFO: Explicitly applied EXTERNAL delegate, and the model graph will be partially executed by the delegate w/ 1 delegate kernels. INFO: Created TensorFlow Lite XNNPACK delegate for CPU. INFO: The input model file size (MB): 3.20989 INFO: Initialized session in 12.756ms. INFO: Running benchmark for at least 1 iterations and at least 0.5 seconds but terminate if exceeding 150 seconds. INFO: count=17 first=31509 curr=27588 min=27555 max=31509 avg=29101.2 std=1166 p5=27555 median=29071 p95=31509 INFO: Running benchmark for at least 50 iterations and at least 1 seconds but terminate if exceeding 150 seconds. INFO: count=50 first=28068 curr=29081 min=26573 max=31340 avg=29104.1 std=1204 p5=27306 median=29141 p95=31171 INFO: Inference timings in us: Init: 12756, First inference: 31509, Warmup (avg): 29101.2, Inference (avg): 29104.1 INFO: Note: as the benchmark tool itself affects memory footprint, the following is only APPROXIMATE to the actual memory footprint of the model at runtime. Take the information at your discretion. INFO: Memory footprint delta from the start of the tool (MB): init=6.98438 overall=12.2344 root@imx95evk:~ Disclaimer: Ultralytics YOLO models have not been officially validated/supported by NXP. Therefore, compatibility with i.MX processors and their corresponding NPUs cannot be guaranteed. Some models or configurations may not work as expected depending on operator support and hardware limitations.
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2S TDM Master: Persistent 1-slot downward shift during continuous DMA streaming 1. Test Configuration I2S configured as TDM Master, DSP mode with short WS 8 slots per frame, 32-bit per slot, frame length = 256 bit Using fsl_i2s_dma driver Dual-buffer ping-pong transfer FreeRTOS task waits on a semaphore from the DMA callback, fills the buffer, then calls I2S_TxTransferSendDMA to re-submit Test data pattern: fixed 0x000Axxxx (upper 16 bits = 0x000A, lower 16 bits contain slot index and sample sequence number) 2. Persistent One-Slot Downward Shift (100% Reproducible) Logic analyzer captures show: Transmitted data is consistently shifted down by exactly one slot Data intended for Slot 0 appears in the physical Slot 1 position Data intended for Slot 1 appears in the physical Slot 2 position By extension, data intended for Slot 7 appears in Slot 0 of the next frame (or is lost) This shift is stable after the stream starts; it does not drift further over time and remains a fixed 1-slot offset 3. Startup Data Misalignment (Intermittent) The logic analyzer occasionally observes: After the WS frame sync pulse, the DATA line remains at low level (all zeros) for a period After a blank interval of 1~3 frames, valid test data suddenly appears Once the blank interval ends, the data still exhibits the 1-slot offset described in item 2 Audio(PDM | I2S | SAI) Re: 2S TDM Master: Persistent 1-slot downward shift during continuous DMA streaming Hello @Xanderwangx , Thank you for your post. Could you please let us know which NXP MCU you are using? Also, are you working with one of our evaluation boards or a custom board? Are you using the SDK example code, or is this based on your own implementation? If it is your own code, would you be able to share it with us for further analysis? BR Celeste Re: 2S TDM Master: Persistent 1-slot downward shift during continuous DMA streaming Hello @Xanderwangx , Thank you for your reply. However, the RT family is not within my support scope. I mainly support MCX and Kinetis family. Also, this is MCX channel, not for RT product. Could you please create a new post under i.MX RT Crossover MCUs - NXP Community? The RT support team will be able to assist you there. BR Celeste Re: 2S TDM Master: Persistent 1-slot downward shift during continuous DMA streaming MCU: MIMXRT685-EVK (i.MX RT685) Board: Custom product board based on RT685. I am using Loop DMA mode with ping-pong buffers. The DMA is configured with I2S_TransferSendLoopDMA() using 2 descriptors. In the DMA callback, I fill the next buffer and the loop continues automatically. void I2S1_TDM_Init(void) { I2S_Type *base = I2S1; /* I2S Configuration */ i2s_config_t cfg; I2S_TxGetDefaultConfig(&cfg); cfg.masterSlave = kI2S_MasterSlaveNormalMaster; cfg.mode = kI2S_ModeDspWsShort; /* TDM = DSP mode */ cfg.divider = 24576000 / (TDM_SAMPLE_RATE * TDM_SLOT_NUM * TDM_SLOT_WIDTH); cfg.dataLength = TDM_SLOT_WIDTH; /* 32-bit */ cfg.frameLength = TDM_FRAME_LENGTH; /* 256-bit */ cfg.oneChannel = false; cfg.position = 0; cfg.wsPol = true; /* DSP A or B */ I2S_TxInit(base, &cfg); /* Enable 8 slots (Primary + 3 Secondary Channels) */ /* Note: Using 4 channels to cover 8 slots with 32-bit data */ I2S_EnableSecondaryChannel(base, kI2S_SecondaryChannel1, false, 32 * 2); I2S_EnableSecondaryChannel(base, kI2S_SecondaryChannel2, false, 32 * 4); I2S_EnableSecondaryChannel(base, kI2S_SecondaryChannel3, false, 32 * 6); /* DMA Loop Transfer Setup */ DMA_Init(DMA0); DMA_EnableChannel(DMA0, I2S_TX_DMA_CH); DMA_SetChannelPriority(DMA0, I2S_TX_DMA_CH, kDMA_ChannelPriority3); DMA_CreateHandle(&dma_handle, DMA0, I2S_TX_DMA_CH); I2S_TxTransferCreateHandleDMA(base, &i2s_handle, &dma_handle, I2S1_Callback, tdm_xfer); I2S_TransferInstallLoopDMADescriptorMemory(&i2s_handle, tdm_desc, 2); if (I2S_TransferSendLoopDMA(base, &i2s_handle, &tdm_xfer[0], 2) != kStatus_Success) { while (1); /* Fails if TDM_FRAMES * 8 > DMA_MAX_TRANSFER_COUNT(1024) */ } } The slot offset is random across power cycles, not fixed.I also tried disable interrupts before and after the DMA transfer to force synchronization, but slot misalignment still occurs. Does I2S_TransferSendLoopDMA() guarantee frame-aligned DMA startup on RT685? If not, how to force alignment to WS boundary? i.MX-RT600 
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在基于 NXP 的 SoM(Layerscape SoC)上调用 DDR 在我公司的几个月内,我们将准备好推出新的SoM(建立在恩智浦 LS1028 SoC 之上)。因此,我想向您--更有经验的开发人员--请教一些知识,您是如何进行 DDR 更新的?使用什么工具?如何进行 DDR 初始化?您要执行哪些步骤?关于 DDR 有哪些常见误区?我应该注意什么? Re: DDR bring-up on NXP based SoM (Layerscape SoC) 关于 DDR 验证,请遵循《QCVS_DDR_用户指南》。 成功完成 QCVS 验证后,点击"Generate processor expert code" 的图标,在 \ \Generated_Code\ddr_init1.c,then将优化的计时参数集成到 ATF ddr_init.c 中。   QCVS DDR 是 codewarrior Developer Suite Level 的一个工具。 您还可以从以下链接下载 codewarrior Developer Suite Level Evaluation Edition。 https://www.nxp.com/design/software/development-software/codewarrior-development-tools/codewarrior-network-applications/codewarrior-development-suites-for-networked-applications:CW-DS-NETAPPS 评估版可免费使用,但有时间限制。   调试工具用于连接 LS1028A 客户板和 codewarrior 开发者套件级别,请在以下链接中找到该工具: https://www.nxp.com/design/design-center/development-boards-and-designs/CW_TAP CodeWarrior TAP 高性能探针基础单元,支持以太网和 USB(单独订购提示)。 cwh-ctp-base-he CWH-CTP-CTX10-YE Layerscape 处理器(Coretex 10 引脚)   DDR 布局应遵循 AN5097 AN5097,DDR4 同步动态随机存取存储器(SDRAM) 内存接口的硬件和布局设计注意事项
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S32K3 在不阻塞的情况下测量 PWM 占空比 (emiOS ICU IPWM) 你好, 仅供参考- 我正在使用 emiOS 的 ICU 通道来测量 IPWM 模式下不同的 PWM 占空比。我目前能够成功地以 " 阻塞 " 方式测量占空比。 我的输入从 100% 占空比(实际上没有 PWM)过渡到我需要测量的给定占空比的 PWM 信号。 我的 .mex配置如下 我的示例代码如下 虽然这种方法可行,但我更倾向于启动一次信号测量,并定期调用Emios_Icu_Ip_GetDutyCycleValues(),而无需调用 Emios_Icu_Ip_StopSignalMeasurement(),以避免在测量完成之前被阻塞。另外,如果在测量完成时有一个中断被触发,对我来说也是可行的。 我最初只尝试调用 emios_ICU_IP_startSignalMeasuremeasum (),然后定期调用 emios_ICU_IP_getdutyCycleValues ()(每 1 秒,而 PWM 频率为 1kHz),但是数据不准确。 据我了解,SAIC 更适合不同的 PWM 信号(我认为这适合我的用例),但我想我也可以使用 IPWM,因为测量读数会延迟。我不介意返回的结果是否会稍微延迟或过时几毫秒,因为我预计占空比不会发生快速变化,而且频率将保持不变。 如果有人能澄清如何使用IPWM实现这一目标,或者我只能通过SAIC实现这一点,那就太好了。 谢谢 Re: S32K3 measuring PWM duty cycle (eMIOS ICU IPWM) without blocking 你好 您遇到的问题是 S32K3 上 eMIOS ICU IPWM 模式的一个已知限制: IPWM 本身是 "基于测量窗口 "的,而不是连续的,因此在不重启/关闭测量的情况下定期读取会导致过期或部分更新的值。 IPWM 不是为不同步的定期轮询而设计的 您必须: 使用中断通知,或 读数前重新开始测量,或 转用 SAIC 实现真正的无阻塞连续测量 顺祝商祺! Peter
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S32K566 IMCR Confilct 错误 MCU: S32K566 MCAL 套餐:RTD 0.8.0 (S32K5_RTD_0_8_0_D2512_ASR_REL_4_9_REL_4_9_REV_0000_20251205) 端口插件:端口_TS_T40D85M8I0R0 工具:EB Tresos / NXP MCAL 生成器 (McalGenerator_Nxp_S32K5-0.8.0) 说明: 我正在尝试使用端口 MCAL 插件在 S32K566 上配置多个 ADC0 模拟输入引脚。当我配置多个 ADC0 输入通道时,代码生成器会报告 IMCR 冲突错误。 配置: PCR 209 → 模式: ADC0_ADC0_CH2_P2_IN (映射到 SIUL2_3 上的 PORT209) PCR 226 → 模式: ADC0_ADC0_CH4_P4_IN (映射到 SIUL2_3 上的 PORT226) 问题 当仅配置一个 ADC 引脚时,代码生成成功,但 IMCR 索引报告为 0。 当添加第二个 ADC 引脚时,会出现 IMCR 冲突错误,因为两个引脚都映射到 SIUL2_3 上的同一个 IMCR 索引 0。 我调查了 port_s32K5_resource.m 文件,发现所有 ADC0 模拟输入通道都是使用 IMCR 映射 0 定义的 需要更改哪些配置才能解决这个问题? 如果这是一个已确认的错误,有没有已知的解决方法? Re: S32K566 IMCR Confilct Error 你好@JaeHeonJeong 由于 S32K5 仍处于 NPI 状态,我建议使用专用的支持渠道——要么直接 FAE 支持,要么在此处输入票证 (https://support.nxp.com/s/?language=en_US),这样它就会分配给区域 FAE 团队。也可能有专门针对贵公司的私人社区空间,但我不确定,因为我没有访问权限。 该社区尚未支持 S32K5。感谢您的理解。 此致, Lukas Re: S32K566 IMCR Confilct Error ADC0 通道可能基于不同的 IO 引脚和不同的 IMCR。而每个 IO 引脚都专用于一个 IMCR 不确定 K556 设置是关于什么的,因为它是一款非常新的设备。您能提供截图吗?
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s32ds for arm V2.2 のインストール中にアクティベーションに失敗しました。 私の注文/ライセンス情報: 注文ID / 行番号: S32DS-IDE-ARM-V2-X_78357511 / 1 フルフィルメントID: 129144101 アクティベーションコード: 60CA-0D4F-9A08-3EEB 製品:S32 Design Studio for ARM v2.2 アップデート2 有効期限:2030年4月21日 問題の説明: インストール中に、アクティベーションが失敗し、「ソフトウェアアクティベーションコードは既にこの端末で使用されています(3 アクティベート済み 2.2)」というエラーメッセージが表示されます。 私はこのライセンスを1台のPCでしか使用しておらず、この問題はシステムを再インストールした後に発生しました。ライセンスは現在ロックされており、アクティベートできません。また、ウェブサイト上でライセンスを手動で返却するオプションもありません。 このライセンスの認証回数をリセットし、ハードウェアとの紐付けを解除してください。そうすれば、現在使用しているPCで正常にライセンス認証を行うことができます。 よろしくお願いします。 回复: s32ds for arm V2.2 Activation failed during installation. 直しました。C:\ProgramData\FLEXnetフォルダを削除し、ソフトウェアを再インストールして、アクティベーションコードを入力する際にオフラインインストールを選択してください。
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SE050E2HQ1/Z01Z3Z 的电容和铁氧体磁珠要求 您好,NXP团队, 我们在定制设计板中使用安全元件 P/N:SE050E2HQ1/Z01Z3Z。 在审查参考设计板 OM-SE050ARD 时,我们几乎没有什么顾虑,如下所示 1.是否严格要求在 VIN (12)、VOUT (15)、VCC (18)引脚上使用阻抗为 330 欧姆、频率为 100 MHz 的 P/N: BLM21PG331SN1D铁氧体磁珠? 2.我们是否还需要在 VSS (19) 引脚上添加铁氧体磁珠? 3.是否需要使用 0.033uF 电容或者我们可以使用 100nF 电容? 谢谢! Re: Capacitor and Ferrite Bead requirement for SE050E2HQ1/Z01Z3Z 你好@kadamm 希望你一切顺利。 铁氧体磁珠主要与双接口操作(由非接触式接口提供)有关,以实现正确的电磁兼容性。 关于电容,您是否正在考虑只使用一个(共享)100nF 电容?如果是这样,我相信应该不会有什么大的不便。 Eduardo。 Re: Capacitor and Ferrite Bead requirement for SE050E2HQ1/Z01Z3Z 你好,爱德华多、 我们的设计没有采用 ISO 14443 或 ISO 7816 接口。因此,我们计划直接连接 VIN、VCC、VOUT 和 GND 引脚,而不使用铁氧体磁珠。此外,我们在引脚上放置一个 0.1 µF 电容以进行解耦。请问这种方法是否合适?   谢谢!
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S32K312MINI-EVB Segger JTAG-SWD接続エラー こんにちは、S32K312MINi EVBを持っています。SWD/JTAG経由でこれをプログラムしようとしています(opesdaが搭載されていることは知っていますが、私のカスタムPCB設計には搭載されません)。 接続しようとすると、次のエラーが表示されます。 不明なSDA AP IDが検出されました: 0xFFFFFFFF 不明なSDA AP IDが検出されました: 0xFFFFFFFF InitTarget() 終了 - 1.09秒かかりました ****** エラー: J-Link スクリプトファイル関数 InitTarget() がエラーコード -1 を返しました   R0と消去を試しましたが、うまくいきませんでした Re: S32K312MINI-EVB Segger Jtag-SWD connection error こんにちは、 ご返信ありがとうございます。 Seggerソフトウェアの最新バージョンを使用していますが、vrefが3.3Vになっているのを確認しています。 ピンもテストしましたが、配線は正しいです。リセットボタンは、複数のテスト段階において押し続けられました。 JTAGも、チップとの接続に失敗したというエラーコードを出力しています。 速度を落とそうともしましたが、効果がないようです。 PC上でS32用のjlinkscriptを探してみましたが、見つかりませんでした。どこにあるのでしょうか? Re: S32K312MINI-EVB Segger Jtag-SWD connection error こんにちは、 エラー: J-Link スクリプトファイル関数 InitTarget() がエラーコード -1 を返しました。 J-LinkはターゲットMCUの初期化手順を正常に実行できず、初期化スクリプト(InitTarget())が失敗しました。 初期化に失敗したため、デバッガーはデバイスと通信できません。 このメッセージは、J-Linkが接続のごく初期段階でDAP(デバッグアクセスポート)にアクセスできない場合に表示されます。 「不明なSDA AP IDが検出されました: 0xFFFFFFFF」 InitTarget() 関数は、SEGGER が使用する J-Link スクリプト ファイル (.JLinkScript) の一部です。 時計を設定する デバッグインターフェースを起動する MEM-AP / AHB-AP の設定 デバイス固有の設定を実行する デバッグに必要なアクセスが失敗した場合、SEGGER はスクリプトを中止し、エラー -1 を返します。 解決策の概要 J-Linkソフトウェアをアップデートする SEGGER社はS32K31xのアルゴリズムにバグがあることを確認した。 J-LinkへのVTref(3.3V)を確認してください。 VTrefが欠落しているため、AP ID = 0xFFFFFFFF → InitTargetが失敗します。 SWD配線を確認する SWD_DIO、SWD_CLK、RESET、およびGNDが正しく接続されていることを確認してください。 リセットして接続し、SWD速度を下げてください。 ファームウェアがピンを早期に再構成してくれると助かります。 SWDモードの代わりにJTAGモードを試してください 同様のNXPデバッグエラーで提案された解決策です。 よろしくお願いします、 ピーター
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MCU1 掩码版本详细信息 您好,NXP团队: 你能否与我们联系 S32K MCU 使用的是哪种类型的 MASK 版本,比如 ROM、Flash 还是 OTP 类型? Re: MCU1 Mask version Details 你好@JANANI_NIVETIDA S32K MCU 使用嵌入式闪存作为程序存储器。它们没有掩膜 ROM 或掩膜 OTP 版本(只有用于内部微调/设置的小 OTP 区域)。 此致, Lukas
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[フィルター: スパム] dexter_travis の投稿本文が「loan」、ボード「1007forum-board」に一致しました。 [フィルター: スパム] dexter_travis の投稿本文が「loan」、ボード「1007forum-board」に一致しました。 投稿件名: Re: i.MX95 EVK と SJA1105Q-EVB の接続 投稿本文: 残念ながら、私はお客様に SJA1105 ボードを貸与しなければなりませんでした。彼らは、DSA 実装がニーズに適しているかどうかを確認するために、93 車載 EVK でこれをテストして使用しています。 現時点では 95 の結果を確認することはできません。 テストと検証をしていただきありがとうございます。ボードが戻ってきたら、あなたの結果を再現してみます。それまではこのチケットを閉じておけます。 本文のテキスト「loan」がフィルター パターン「loan」と一致しました。 ユーザー[id=241378,login=dexter_travis]による投稿は、エンドユーザー側で発生する次のエラーのため拒否されました: メッセージ本文にローンが含まれていますが、このコミュニティでは許可されていません。投稿を送信する前にこのコンテンツを削除してください。
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IMX8MPLUSでxtestが失敗する imx8MPLUS-BB 開発ボードで optee をインストールし、xtest を実行すると、以下のエラーが発生します。 その後、r = ADBG_EXPECT_TEEC_RESULT(c, TEEC_ERROR_SECURITY, res) を r = ADBG_EXPECT_TEEC_RESULT(c, TEEC_ERROR_GENERIC, res) に変更したところ、次の問題が再び発生しました。 とても混乱していて、解決方法がわかりません よろしくお願いします! Re: xtest fails on IMX8MPLUS 古いスレッドなので、おそらくもう答えは気にしないかもしれませんが、他の人も同じ問題を抱えてこの投稿に出会うかもしれません。 私の場合、別のソフトウェア リビジョンに切り替えると問題が解決するようです。optee-os と x-test 6.6.52-2.2.0 ("4.4.0")を使用していたとき、テストはあなたが示したのと同じ方法で失敗しました。optee-os および x-test 6.12.49-2.2.0 ("4.8.0")では、この問題は再現されなくなりました。 最初から構築する場合は、optee と x-test の NXP github リポジトリを使用することを忘れないでください。 - https://github.com/nxp-imx/imx-optee-test - https://github.com/nxp-imx/imx-optee-os Re: xtest fails on IMX8MPLUS どのバージョンの BSP を使用していますか? Re: xtest fails on IMX8MPLUS 実際、これは私の問題を修正したコミットです (6.12 には存在しますが、6.6 には存在しません)。 commit c6c7967f74d4c6267750b3ff42067c004f8cad33 Author: Jens Wiklander Date: Fri Dec 13 10:01:33 2024 +0100 core: pta: secstore: decrease TA buffer install_ta() uses a buffer allocated from the heap while hashing a TA while installing it. The buffer size is 8kB which is a bit large to reliably allocate from the heap, so decrease it to 1kB. Signed-off-by: Jens Wiklander Acked-by: Jerome Forissier Reviewed-by: Etienne Carriere diff --git a/core/pta/secstor_ta_mgmt.c b/core/pta/secstor_ta_mgmt.c index 162de43be..b8dc9283c 100644 --- a/core/pta/secstor_ta_mgmt.c +++ b/core/pta/secstor_ta_mgmt.c @@ -44,7 +44,7 @@ static TEE_Result install_ta(struct shdr *shdr, const uint8_t *nw, struct tee_tadb_ta_write *ta; void *hash_ctx = NULL; size_t offs; - const size_t buf_size = 2 * 4096; + const size_t buf_size = 1024; void *buf; struct tee_tadb_property property; struct shdr_bootstrap_ta bs_ta;
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如何断开调试器? 问题 我需要断开调试器,让应用程序继续运行。 只要拔出 J-Link 的 USB 电缆通常会使我的板崩溃。 有一个 断开按钮,但它是灰色的。 如何才能(优雅地)断开调试器(并让应用程序正常运行)?希望那样我能让 J-Link 掉电? 背景: 在 imxRT1024 上运行的大型 FreeRTOS 应用程序。 调试器工作绝对正常 Windows 10 上的 MCUXpresso IDE v24.9 [版本 25] [2024-09-26] segger J-Link 软件版本 V9.22(刚更新到最新版本) i.MX RT102x Re: How can I disconnect debugger? 你好@davenadler、 感谢您对 NXP MIMXRT 系列的关注! 您的应用程序使用 semihost 吗?还是软件重新配置了任何与 SWD 相关的引脚?也有可能是你的硬件在断开与调试器的连接后出现了供电问题。请帮忙检查一下。或者,也可以尝试使用串行下载模式,直接将映像下载到闪存中,然后检查运行是否正常。 因为如果你的调试器正确地将二进制文件编程到闪存中,那么断开与调试器的连接就不太可能导致崩溃。 致以最诚挚的问候, Gavin
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ls1028aのセキュアデバッグ こんにちは、 ls1028a ベースのカスタム ボードで Secure Debug をテストしたいと思います。今のところ、次の手順を実行しました。 1. fuse_fipと次のinput_fuse_fileを使用してレジスタをヒューズする /* * 著作権 2018 NXP */ --------------------------------------------------- プラットフォーム= LS1028 --------------------------------------------------- POVDD_GPIO = --------------------------------------------------- OTPMK_FLAGS =0010 OTPMK_0 =11111111 OTPMK_1 =22222222 OTPMK_2 =33333333 OTPMK_3 =44444444 OTPMK_4 =aab702d7 OTPMK_5 =f9506757 OTPMK_6 =cfb3b401 OTPMK_7 =b5462445 --------------------------------------------------- SRKH_0 =9f05646d SRKH_1 =eb7e034b SRKH_2 =a5c8da66 SRKH_3 =0215ce65 SRKH_4 =34bec8dd SRKH_5 =500d48bb SRKH_6 =665582c0 SRKH_7 =8b826a4f --------------------------------------------------- OEM_UID_0 =11223344 OEM_UID_1 =55667788 OEM_UID_2 =99001122 OEM_UID_3 =33445566 OEM_UID_4 =77889900 --------------------------------------------------- DCV_0 =68686868 DCV_1 =67676767 DRV_0 =6168745f DRV_1 =5f726e6e --------------------------------------------------- DBG_LVL =001 --------------------------------------------------- WP = ITS = NSEC = ZD = K0 = K1 = K2 = K3 = K4 = K5 = K6 = FR0 = FR1 = --------------------------------------------------- OUTPUT_FUSE_FILENAME =fuse_scr.bin --------------------------------------------------- gen_drv_drbg で作成された DRV λ ./gen_drv_drbgA2 6168745f5f726e6e #-----------------------------------------------------# #------- -------- -------- -------# #------- CST (コード署名ツール) バージョン 2.0 -------# #------- -------- -------- -------# #-----------------------------------------------------# ハミングコード後のDRV[63:0]は次のようになります。 6168745f5f726e6e 名前 | ビット | 値 _______ __|__ __________ __|__ __________ ドライブ 0 | 63 - 32 | 6168745f ドライブ 1 | 31 - 0 | 5f726e6e ブートしてU-Bootシェルから確認することで、それらが正しく融合されていることを確認できます。 ハミングコードエラーなし 0x1e80024 1 01e80024: 00000000 .... dblev が 1 に設定され、dcvr も融合されています => md 0x1e80204 3 01e80204: 00000001 68686868 67676767 ....うぅうぅううう drvr を 1 に設定 => md 0x1e80210 2 01e80210: ffffffff ffffffff ........ しかし、接続できません。コード ウォリアー (バージョン: 11.5.12;) で試してみると、ビルドID: 221209)、ターゲット接続構成で「セキュアデバッグキー:」を設定し、そこにキー「0x6e6e725f5f746861」(逆エンディアン)を指定して検査しようとすると、情報でエラーが発生しました。 [CCS: マルチコア動作中のサブコアエラー] 私はSecure_boot.pptxプレゼンテーション(リンク: https://community.nxp.com/t5/Layerscape-Knowledge-Base/Secure-boot-Fuse-Provisioning-Secure-debug/ta-p/1988564 )に従ってCCSからテストしようとしましたが、次のようになりました。 (ビン)54%すべて削除 (bin) 55 % config cc cwtap:192.168.0.32 (ビン)56%ccを表示 0: コードウォリアーTAP (cwtap:192.168.0.32)CC ソフトウェア バージョン{0.0} (ビン)57% (bin) 57 % ccs::config_chain {ls1028a dap} SAP2: セキュアデバッグ違反 (bin) 58 % ccs::get_config_chain を表示 チェーン位置0: LS1028A チェーンポジション1: DAP チェーン位置2: SAP2 (ビン)59% (bin) 59 % ccs::config_chain {ls1028a dap sap2} LS1028A: std::bad_alloc (bin) 60 % ccs::config_chain {ls1028a dap} SAP2: セキュアデバッグ違反 (bin) 61 % ccs::get_config_chain を表示 チェーン位置0: LS1028A チェーンポジション1: DAP チェーン位置2: SAP2 (bin) 62 % ディスプレイ ccs::read_reg 0 sdcr 1 8 SAP2 エラー - SAP_STATUS を読み取ります SAP2 エラーとは何ですか?それに関していかなる情報も見つけることができません。 何か間違ったことをしているのでしょうか? QorIQ LS1デバイス Re: Secure Debug on ls1028a 他に試せることはありますか?あるいは、チャレンジ/レスポンス手順は ls1028a では実行できないのでしょうか?現時点では、JTAG を閉じたように動作しますが、input_fuse_file で使用される IIUC 構成では、通知なしで条件付きで閉じるように設定する必要があります。また、U-Boot シェルから読み取られたレジスタも同じ情報を伝えます。 Re: Secure Debug on ls1028a @LFGP私はhttps://www.nxp.com/part/LS1027AXE7NQAを使用していますSO、そこには E という文字があります。 Re: Secure Debug on ls1028a @LFGP 私の記憶では、部品番号に E が付いている SoC は、セキュリティがオンになっていることを意味しますか?明日確認しますが、セキュア ブート手順を実行できるため、E が搭載されているはずだとほぼ確信しています。 デバッグレベルに関しては..元の投稿で書きましたが、私は現在レベル001です。 # 001 -> 通知なしで、チャレンジレスポンスを介して条件付きで開きます。 以下は U-Boot シェルからの出力です。 => md 0x1e80204 3 01e80204: 00000001 68686868 67676767 ....うぅうぅううう したがって、0x1e80204 は 00000001 -> DB_LVL は 001 に設定されます。 @LFGP他に何が間違っているのでしょうか?これをさらにデバッグするにはどうすればいいでしょうか? Re: Secure Debug on ls1028a 親愛なる@tomzy_0様、 デバイスの部品番号命名法に文字 E が含まれていることを確認してください。 一方、「デバッグレベル」レジスタが閉じられていないことを確認してください。以下を参照してください。 -------------------------------------------------- # デバッグ レベルをバイナリ形式で指定します。[オプション] # 000 -> 完全にオープン: デバッグ ポータルは無条件に有効になります。 # 001 -> 通知なしで、チャレンジレスポンスを介して条件付きで開きます。 # 01x -> 通知付きでチャレンジレスポンス経由で条件付きで開きます。 # 1xx -> クローズしました。すべてのデバッグ ポータルが無効になっています。 DBG_LVL= ---------------------------------------------------   よろしくお願いいたします LFGP Re: Secure Debug on ls1028a @LFGP素早い返信ありがとうございます。残念ながら、あなたが言及したスレッドで提供されている手順にすでに従いました。私の投稿でリンクしたプレゼンテーションにも同じ手順が書かれていました。このようなコマンドを実行した結果も投稿しました。返される印刷エラー ログで DCV を CCS として読み取ることもできません。 @yipingwangこんにちは。直接言及して申し訳ありませんが、Threadに返信したのはあなただとわかりました。私が間違っていなければ、セキュア ブートのプレゼンテーションの作成も担当されていましたね。 お手伝いいただけますか?プレゼンテーションと私のケースの違いは、私が ls1028a を使用していることです。 チェーンは異なる構成にする必要があります ({ls1028a dap/sap2} と {ls1043a dap sap2})。しかし、これが本当に問題であるかどうかを判断するのは困難です。CCS ドキュメントというものは存在しないと思います。これがなければ、さらにデバッグを行うことさえ困難です。 質問の一つに戻ります。セキュアデバッグが動作するために追加の条件が必要ですか?ITSは設定されていますか?SB_ENだけで十分でしょうか?RCWの他のビットを設定する必要があるでしょうか? Re: Secure Debug on ls1028a 親愛なる@tomzy_0様、 SAP2 の意味は何ですか?回答:セキュア アクセス ポートです。   デバイスが JTAG ポートを開くように設定されている場合、チャレンジ/レスポンス イベントによって認証されるまで SAP2 はロックされたままになります。 チャレンジ/レスポンス イベントを通過する前に列挙またはアクセスを試みると、 「セキュア デバッグ違反」が発生します。そのため、CCS ログ メッセージ「セキュア デバッグ違反」および「SAP2 エラー - SAP_STATUS を読み取り」が表示されます。   次のケースを確認してください。それはあなたのケースに関連しています。 https://community.nxp.com/t5/CodeWarrior-for-QorIQ/JTAG-デバッグチャレンジ応答-in-CodeWarrior-connection-server/mp/1281386   BR LFGP Re: Secure Debug on ls1028a セキュア デバッグが機能するための追加条件はありますか?セキュアブートで起動する必要がありますか?何らかの SECMON 状態にありますか? Re: Secure Debug on ls1028a 親愛なる@tomzy_0様、 SB_EN = 1に設定し、 IT_S =0 SECリファレンス・マニュアルをダウンロードする https://www.nxp.com/webapp/sps/download/preDownload.jsp?render=true 次のアプローチを試すことができます(LS1028aに合わせて調整してください)。 SecMon_HP ステータス レジスタ (位置 0x1e90014) をチェックして、ビット OTPMK_ZERO、OTMPK_SYNDROME、および PE が 0 になっていることを確認してください。そうでない場合は、ユーザーが切断した OTPMK ヒューズに何らかのエラーがあります。 b.OTMPK ヒューズが正しい場合 (手順 1 を参照)、SCRATCHRW2 (0x1ee0204) レジスタにエラーがないか確認します。 紀元前手順 b のエラー コードが 0 の場合は、HPSR のシステム セキュリティ モニターの状態フィールドを確認します。 システムセキュリティモニターの状態 (0x9) ITS ヒューズ = 1 の場合、ISBC コードがボードをリセットしたことを意味します。これには次の理由が考えられます。 ESBC u-boot の署名に使用された公開鍵のハッシュが SRK Hash Fuse の値と一致しません または 画像の署名検証に失敗しました。 SSM_STATE (0xd) または非セキュア状態 (0xb) ESBC ヘッダーのエントリ ポイント フィールドを確認します。 エントリ ポイントが正しい場合は、u-boot イメージが必要なセキュア ブート構成でコンパイルされていることを確認します。 BR LFGP Re: Secure Debug on ls1028a @LFGP こんにちは、返信が遅くなって申し訳ありません。以下はU-Bootシェルからの出力です。 「`」 => md 0x1e90014 1 01e90014: 80002900 .).. 「`」 つまり、SecMonの状態は「チェック」に設定されます。OTPMK_ZEROは0です。OTPMK_SYNDROMまたはPEが何なのか分かりません。 「`」 => md 0x1ee0204 1 01ee0204: 00000000 .... 「`」 SCRATCHRW2 を 0 に設定することで、エラーは発生しません。ちなみに、ハミング符号もゼロなので、すべて問題ないはずです。 「`」 => md 0x1e80024 01e80024: 00000000 .... 「`」 セキュアモニターは別の状態であるべきでしょうか? Re: Secure Debug on ls1028a CodeWarrior GUIからCCSログをDEBUGに設定して接続を確認したところ、以下のことが分かりました。 ccs_get_config_chain serverh = 0 デバイスリスト: (サイズ = 3) ccs_get_config_chain; ccs_error = 0 ccs_get_config_chain serverh = 0 デバイスリスト: (サイズ = 3) device[0]:: core_type=LS1028A(301) device[1]:: core_type=DAP(232) device[2]:: core_type=SAP2(272) ccs_get_config_chain; ccs_error = 0 ccs_read_register coreh = [serverh:0;cc_index:0;chain_pos:0] インデックス = 8192 カウント = 1 サイズ = 8 値: (サイズ = 😎 00000000 00000000 ccs_read_register; ccs_error = 56 エラーメッセージ: SAP2 エラー - SAP_STATUS の読み取り ccs_get_config_chain serverh = 0 デバイスリスト: (サイズ = 3) ccs_get_config_chain; ccs_error = 0 ccs_get_config_chain serverh = 0 デバイスリスト: (サイズ = 3) device[0]:: core_type=LS1028A(301) device[1]:: core_type=DAP(232) device[2]:: core_type=SAP2(272) ccs_get_config_chain; ccs_error = 0 ccs_write_register coreh = [serverh:0;cc_index:0;chain_pos:0] インデックス = 8193 カウント = 1 サイズ = 8 値: (サイズ = 😎 6168745F 5F726E6E ccs_write_register; ccs_error = 56 エラーメッセージ: SAP2 エラー - SAP_STATUS の読み取り チャレンジ値を読み取るとすべて0が返され、SAP2エラーが発生するようです。本来であれば、U-Bootシェルから読み取れるチャレンジ値が返されるはずです。なぜそのようなことが起こるのでしょうか?
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Viable replacement for DSP56F807 Hi team, We have a customer seen the EOL that was sent out on the DSP56F807, specifically we use the DSP56F807VF80E. Since we are faced with having to tackle this and there were no direct replacements listed, I was wondering what the most similar part would be from your point of view? We are thinking if we can find anything that requires little to no redesign work. Thank you for any support you can give on this.
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