MCUXpresso Config Tool for MCUXpresso IDE Clone an Example Project from MCUXpresso IDE The following steps will guide you through the manipulation of the general-purpose outputs. The example sets up a CTimer to generate a PWM signal and change between two LEDs. Find the Quickstart Panel in the lower left-hand corner and click on Import SDK example(s) Click on the FRDM-MCXN947 board to select that you want to import an example that can run on that board, and then click on Next Use the arrow button to expand the  driver_examples  category, then expand the ctimer examples, click on the check box next to  ctimer_match_interrupt_example  to select it. To use the UART for printing (instead of the default semihosting), Select UART as the SDK Debug Console checkbox under the project options. Then, click on Finish Click on the  “frdmmcxn947_ctimer_match_interrupt_example”  project in the Project Explorer View and build, compile, and run the demo as described in the previous section You should see the BLUE and RED LED changing back and forth Terminate the debug session Use MCUXpresso IDE Pins Tools to Modify Example Note: Previously, you had to clone an SDK project like in the previous step. Open the pins tool by selecting “ConfigTools” on the top right hand of the file explorer window and then select “ Open Pins” The pins tool should now display the pin configuration for the ctimer project In the Pins view deselect “Show dedicated pins” and “Show no routed pins” checkboxes to see only the routed pins. Routed pins have a check in a green box next to the pin name. The functions selected for each routed pin are highlighted in green In the current configuration, PIO3_2 and PIO3_3 are routed as the outputs of the CTimer. Let’s add a third Ctimer Match output and enable the Green LED Select “Show no routed pins” to see the other options. To enable the third Ctimer Match Output, browse the column for Ctimer and select and output. In this example, we will select, Ctimer4 Match 2 on PIO3_6. Select the item in the Ctimer column to enable Now, let’s route the Green LED. In the search box type “green” so that the routed pin for this LED is shown. Finally, click the box under the GPIO column. The box will highlight in green, and a check will appear next to the pin Next configure the GPIO pin as an output in the “Routing Details” window Now it’s time to implement these changes into the project by exporting the new updated pin_mux.c and pin_mux.h files that are generated by the Pins tool. Click on Update Project in the menu bar The screen that pops up will show the files that are changing and you can click on “diff” to see the difference between the current file and the new file generated by the Pins tool. Click on “OK” to overwrite the new files into your project Let’s add some additional code to the example. Open  simple_match_interrupt.c  file and add the following macros for the third ctimer output. Add the Green LED functions as well. Some additional code to be implemented will be the third ctimer’s callback, this can be copied from  ctimer_match1_callback  and modify the content to match2. To be able to visually identify the new ctimer, we will remove one of the previous ctimers as shown The main function will need to include the initialization of both the Green LED and the Ctimer Build and download the project as done in the previous section Run the application. You should now see the Green and Blue LED blinking back and forth Terminate the debug session

S32K344 FlexCAN 示例 CAN FD 正常模式：CAN0_Tx 和 Rx 上无信号 大家好 我正在使用 S32 Design Studio 3.6.5 和 FlexCAN IP 示例处理 S32K344 MCU。 我能够在内部环回模式下成功运行 FlexCAN 示例（并验证 Rx 缓冲区上的数据），但当我将其配置为用户/正常模式时，在物理 CAN 引脚（CAN0 TX/RX）上看不到任何活动。此外，生成的代码中还存在语法错误。 问题 生成代码后： 文件 generate/src/Siul2_Ip_Port_PBcfg.c 包含语法错误 即使我手动修复了语法错误以允许项目构建，但仍然没有使用逻辑分析器在CAN0 TX/RX引脚上观察到任何CAN活动。 以下是我的设置详情以及我迄今为止所做的尝试。 外设视图中的 FlexCAN 配置 FlexCAN 实例：CAN0 模式：启用 BRS 的 CAN FD 标称比特率500 kbps 数据比特率： 2 Mbps 时钟源： 24MHz 轮询模式（无中断） 尝试引脚配置 我尝试对 CAN0 引脚进行如下明确配置： PTA27 PTA28 PTD13 PTD14 采取的措施 通过 管理 SDK 元器件 添加了 Pins 和 Ports 元器件 为外围元器件添加了 Siul2_Port 使用 MSCR（FlexCAN 的 ALT 功能）配置上述引脚 再生代码 如果能就正确的 CAN 实例、引脚复用或已知的工具问题提供指导，我们将不胜感激。 Re: S32K344 FlexCAN example CAN FD normal mode: no signals on CAN0_Tx and Rx 更新：通过在外围设备 > 元器件中添加端口，并将引脚添加为 MSCR 索引，我得以生成正确的代码。 但在 PTA27 引脚上无法获得 CAN0 Tx 信号的问题依然存在。我用 Dio GPIO 示例切换了 PTA27，效果很好，但在 CAN FD 上却没有显示任何信号。 PFA 更新项目 zip。 Re: S32K344 FlexCAN example CAN FD normal mode: no signals on CAN0_Tx and Rx 嗨@pariks_hit 请参阅附件中的演示，RTD 为 3.0.0和 S32K3X4EVB。 Re: S32K344 FlexCAN example CAN FD normal mode: no signals on CAN0_Tx and Rx HI 谢谢你的压缩包，我使用了中断，并像你的主文件那样初始化了 STB 和 EN 引脚，现在我可以看到 Tx 引脚上有东西了。不过，我发现它的 CAN ERROR 信号多于 Saleae 中的实际 CAN 信号（截图附后）。我尝试使用传统 CAN 而不是 CAN FD（在这种情况下，我只能看到 CAN ERROR 信号，而看不到其他信号）。在 CAN FD 中，改变有效载荷大小也无济于事。我还尝试像您的项目那样配置引脚 PTA6 和 PTA7，而不是 PTA27 和 PTA28，但两者的 CAN0_Tx 波形相同，因此我认为这不是引脚问题。我还附上了我的项目压缩包，以备不时之需。 请帮帮我。 Re: S32K344 FlexCAN example CAN FD normal mode: no signals on CAN0_Tx and Rx 您好， 感谢您的确认，看来问题出在我在 Saleae 逻辑分析仪上设置的比特率上，我将其设置为 500k，现在我可以看到 CAN 帧了。

S32K314 HSE_FW_0.2.55.0 HSE_FW_0.2.55.0 リリース ノートでは、0.2.55.0 バージョンで次の問題が修正されました: SHE KEY をキー カタログ内の正しいグループに揃える。 私はSHEキーを使用しているので、この問題の影響が何であるかを知りたいです。また、ECUのhseを0.2.40.0から0.2.55.0にアップデートしたい場合、この問題はSHEキーの使用に影響しますか?[ECUにHSE(0.2.40.0)がインストールされ、init catelogがあり、SHEキーが書き込まれ、HSEサービス業者によってのみHSEバージョンが更新されます]。 S32K3 Re: S32K314 HSE_FW_0.2.55.0 こんにちは、ジアユさん SHE キー グループのキー サイズ数が 1 を超える場合、HSE FW 0.2.55.0 フル メモリ更新後に RAM キー カタログ フォーマット サービスが失敗しました。HIS-SHE 仕様には RAM キーが 1 つしかないため、K1 CSEc にも RAM キーが 1 つあります。 クリスマス休暇期間中は、サポートの応答時間は通常より長くなる場合がありますのでご了承ください。場合によっては、ご要望への対応が新年以降になることもあります。ご理解のほどよろしくお願いいたします。 よろしくお願いします、 ロビン --------------------------------------------------------------------------------- 注記： - この投稿があなたの質問への回答である場合は、「解決策として承認」ボタンをクリックしてください。ありがとう！ - Threadは最後の投稿から7週間フォローされます。それ以降の返信は無視されます。 後ほど関連する質問がある場合は、新しいThreadを開いて、閉じたThreadを参照してください。 ---------------------------------------------------------------------------------

Drivers configuration for the S32K3XX Hello, I would like to ask, S32K3XX series chip new construction projects, in the use of drivers, each driver (1 corresponding to the position of each driver type) corresponding to the configuration interface in each configuration (3 shown in the position), there is no documentation or tutorials to explain? In the actual engineering application, I can rely on what information to configure, I set up each time is to look at the name of the setup item to guess its function, and decided to be configured into what, I feel the lack of official basis, so I feel that each of my settings is very no certainty and basis. Re: S32K3XX的drivers配置 Hi@Aaron_LL The following sections of AN13435 have some descriptions of the components And you can find a lot of training tutorials for configuring these peripherals in the official website. https://www.nxp.com/products/S32K3

Seeking a compatible pressure sensor Hallo everyone I'm looking for a compatible pressure sensor to replace the original 125pc05d1. 125pc05d1 is the original pressure sensor.It is a differential pressure type. I have attached the original pressure sensor's outline drawing and technical specifications. The sensitivity of a 125pc05d1 is approximately equal to Δmv/Δp ≈ 70mv/5psi ≈ 14,Because the subsequent amplifier circuit is complex, I don't know how to adjust it. It would be ideal if there were a newer model of pressure sensor with the same sensitivity that would be compatible. For more detailed testing, please see the link below. https://www.eevblog.com/forum/repair/replacing-the-pressure-sensor-requires-assistance/ Thank you for your help. Re: Seeking a compatible pressure sensor Hello, Please consider using the MPX10DP, as it is the closest match to the original 125pc05d1 in both form and functionality. If you need a broader pressure range or more output voltage for higher resolution, consider the MPX5010DP, albeit with additional signal conditioning. BRs, Tomas Re: Seeking a compatible pressure sensor Thanks

S32K148 引导加载程序跳转应用程序，但应用程序在闪存擦除 + 复制后不运行 我正在 S32K148 上开发一个引导加载程序和应用程序设置。 引导加载程序位于闪存起始位置 (0x00000000) 应用程序位于 0x00022000 应用程序有自己的矢量表和链接脚本 当以独立组网 (SA) 方式运行时，应用程序可以完美运行 当引导程序执行闪存擦除和应用程序复制时，跳转到应用程序不起作用。 然而 如果我跳过擦除和复制，跳转就会正常工作 在这两种情况下都输入了 jump_too_application() 启用擦除 + 复制时，跳转后看不到应用打印 堆栈指针和RESET处理程序值看起来有效 应用程序矢量表正确 应用程序在没有引导程序的情况下也能正常运行 我没有在应用程序代码中明确启用看门狗 闪存擦除 + 复制后，在跳转到 S32K148 上的应用程序之前还需要哪些步骤？ 谁能帮帮我？ 我将链接文件脚本和跳转程序代码附在下面。 谢谢！ 引导程序链接器文件 内存 { int_flash_interrupts：ORIGIN = 0x00000000，长度 = 0x00000400 /* 1K */ /* 不要更改此部分 */ int_flash_config：ORIGIN = 0x00000400，长度 = 0x00000010 /* 16 字节 */ /* 不要更改此部分 */ int_flas h：ORIGIN = 0x00000410，长度 = 0x00001101 bf0 /* 总计 128KB-0x410 = 引导加载程序代码为 0x1FBF0 字节 */ int_sram_results：ORIGIN = 0x1FF0000，长度 = 0x00000100 /* 256 字节 */ int_sram：ORIGIN = 0x1FF0100，长度 = 0x0003df00 /* ~248K */ int_sram_stack_stack_c0: ORIGIN = 0x2001E000，长度 = 0x 00001000 /* 4K */ r am_rsvd2：ORIGIN = 0x2001F000，长度 = 0 /* SRAM 结束 */} 应用程序链接文件 内存 { int_flash_intrupts：ORIGIN = 0x00022000，长度 = 0x00000400 /* 1K-0x00022000 处的应用程序中断向量 */ int_flash_config：ORIGIN = 0x00022400，长度 = 0x00022400，长度 = 0x00000010 /* 16 字节-应用程序 闪存配置 */ int_flash：ORIGIN = 0x00022410，长度 = 0x00063bf0 /* 400KB 应用程序区域（0x64000-0x410 = 0x63bf0 字节）*/ int_sram_results：ORIGIN = 0x1FF0000，长度 = 0x00000100 /* 256 字节 */ int_sram：ORIGIN = 0x1FF0100，长度 = 0x0003df00 /* ~248K */ int_sram_stack_c_c0: ORIGIN = 0x2001E000，长度 = 0x00001000 /* 4K */ r am_rsvd2：ORIGIN = 0x2001F000，长度 = 0 /* SRAM 结束 */} main.c EraseApplication(); CopyApplication(DOWNLOADED_APP_START_ADDRESS,APPLICATION_START_ADDRESS,APPLICATION_SIZE)； jump_to_application()； 跳转到应用程序()函数 void jump_too_application(void) { uint32 app_msp; application_entry_t app_reset_handler； /* 跳转前打印信息 */ // printf("跳转到 application\r\n")； /* // volatile uint32 delay = 100000U; // while(delay--)； /* 禁用所有中断 */ __asm volatile ("cpsid i")； /* 将向量表偏移量设置为应用程序的向量表 */ S32_SCB->VTOR = APPLICATION_START_ADDRESS； /* 从向量表的第一个字加载应用程序的 MSP */ app_msp = *((volatile uint32*)APPLICATION_START_ADDRESS)； /* 从向量表的第二个字加载应用程序的 Reset_Handler 地址 */ app_reset_handler = (application_entry_t)(*((volatile uint32*)(APPLICATION_START_ADDRESS + 4U))； /* 设置指向应用程序 MSP 的堆栈指针 */ __asm volatile ("msr msp,%0": :"r" (app_msp))； // /* Memory barrier */ //__asm volatile ("dsb"); // __asm volatile ("isb")； /* 跳转到应用程序的 Reset_Handler */ app_reset_handler()； /* 不应到达此处 */ while(1) { /* 无限循环 */ } } Re: S32K148 Bootloader jump application, but application does not run after flash erase + copy 请注意，在圣诞假期期间，我们的支持响应时间可能会比平时长。在某些情况下，您的请求可能会在新年后得到处理。感谢您的理解。 Re: S32K148 Bootloader jump application, but application does not run after flash erase + copy 嗨，@kavyakoney、 可能存在闪存访问碰撞，因为引导加载程序和应用程序目前都放在 S32K148 的闪存块 0 中。 S32K148 设备包含三个 512 KB 闪存块（方块 0、块 1、块 2）。闪存编程操作（擦除/编程）只能在 CPU 不执行代码的块上进行。 如果引导加载程序从 0 块运行，并试图擦除或编程也在 0 块内的内存，内核可能会执行无效数据，从而无法正确跳转到应用程序。 为避免出现这种情况，应将应用程序放入闪存块 1 或闪存块 2，而将引导加载程序完全放在闪存块 0 中。 谢谢！ BR，丹尼尔

i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) We designed a custom board based with MIMX8ML8XXXKZ SoC MT53E768M64D4DE-046 WT:C LPDDR4 BD71847 PMIC All SoC and DRAM power lanes seem to be powered properly Based on previous experience with i.MX8MM we attempted to generate timings for the DRAM using the DDR Mtool, but the result we got  Spoiler (Highlight to read) Download is complete Waiting for the target board boot... ===================hardware_init===================== hardware_init exit ************************************************************************* ************************************************************************* ************************************************************************* MX8 DDR Stress Test V3.30 Built on Nov 24 2021 13:52:12 ************************************************************************* Waiting for board configuration from PC-end... --Set up the MMU and enable I and D cache-- - This is the Cortex-A53 core - Check if I cache is enabled - Enabling I cache since it was disabled - Push base address of TTB to TTBR0_EL3 - Config TCR_EL3 - Config MAIR_EL3 - Enable MMU - Data Cache has been enabled - Check system memory register, only for debug - VMCR Check: - ttbr0_el3: 0x97d000 - tcr_el3: 0x2051c - mair_el3: 0x774400 - sctlr_el3: 0xc01815 - id_aa64mmfr0_el1: 0x1122 - MMU and cache setup complete ************************************************************************* ARM clock(CA53) rate: 1800MHz DDR Clock: 2000MHz ============================================ DDR configuration DDR type is LPDDR4 Data width: 32, bank num: 8 Row size: 17, col size: 10 One chip select is used Number of DDR controllers used on the SoC: 1 Density per chip select: 3072MB Density per controller is: 3072MB Total density detected on the board is: 3072MB ============================================ MX8M-plus: Cortex-A53 is found ************************************************************************* ============ Step 1: DDRPHY Training... ============ ---DDR 1D-Training @2000Mhz... PMU: Error: CA Training Failed. PMU: ***** Assertion Error - terminating ***** [Result] FAILED Download is completeWaiting for the target board boot...===================hardware_init=====================hardware_init exit***************************************************************************************************************************************************************************************************************************MX8 DDR Stress Test V3.30Built on Nov 24 2021 13:52:12*************************************************************************Waiting for board configuration from PC-end...--Set up the MMU and enable I and D cache--- This is the Cortex-A53 core- Check if I cache is enabled- Enabling I cache since it was disabled- Push base address of TTB to TTBR0_EL3- Config TCR_EL3- Config MAIR_EL3- Enable MMU- Data Cache has been enabled- Check system memory register, only for debug- VMCR Check:- ttbr0_el3: 0x97d000- tcr_el3: 0x2051c- mair_el3: 0x774400- sctlr_el3: 0xc01815- id_aa64mmfr0_el1: 0x1122- MMU and cache setup complete*************************************************************************ARM clock(CA53) rate: 1800MHzDDR Clock: 2000MHz============================================DDR configurationDDR type is LPDDR4Data width: 32, bank num: 8Row size: 17, col size: 10One chip select is usedNumber of DDR controllers used on the SoC: 1Density per chip select: 3072MBDensity per controller is: 3072MBTotal density detected on the board is: 3072MB============================================MX8M-plus: Cortex-A53 is found*************************************************************************============ Step 1: DDRPHY Training... ============---DDR 1D-Training @2000Mhz...PMU: Error: CA Training Failed.PMU: ***** Assertion Error - terminating *****[Result] FAILED A similar situation was with the Config tool. We tried to use the .ds script both generated by Config tool, as well as the RPA, neither worked Based on the discussion on the forum we attempted to disable the CA training. And calibration for single frequency setpoint started working Spoiler (Highlight to read) Download is complete Waiting for the target board boot... ===================hardware_init===================== hardware_init exit ************************************************************************* ************************************************************************* ************************************************************************* MX8 DDR Stress Test V3.30 Built on Nov 24 2021 13:52:12 ************************************************************************* Waiting for board configuration from PC-end... --Set up the MMU and enable I and D cache-- - This is the Cortex-A53 core - Check if I cache is enabled - Enabling I cache since it was disabled - Push base address of TTB to TTBR0_EL3 - Config TCR_EL3 - Config MAIR_EL3 - Enable MMU - Data Cache has been enabled - Check system memory register, only for debug - VMCR Check: - ttbr0_el3: 0x97d000 - tcr_el3: 0x2051c - mair_el3: 0x774400 - sctlr_el3: 0xc01815 - id_aa64mmfr0_el1: 0x1122 - MMU and cache setup complete ************************************************************************* ARM clock(CA53) rate: 1800MHz DDR Clock: 2000MHz ============================================ DDR configuration DDR type is LPDDR4 Data width: 32, bank num: 8 Row size: 17, col size: 10 Two chip selects are used Number of DDR controllers used on the SoC: 1 Density per chip select: 3072MB Density per controller is: 6144MB Total density detected on the board is: 6144MB ============================================ MX8M-plus: Cortex-A53 is found ************************************************************************* ============ Step 1: DDRPHY Training... ============ ---DDR 1D-Training @2000Mhz... [Process] End of initialization [Process] End of read enable training [Process] End of fine write leveling [Process] End of read DQ deskew training [Process] End of MPR read delay center optimization [Process] End of Write Leveling coarse delay [Process] End of write delay center optimization [Process] End of read delay center optimization [Process] End of max read latency training [Result] PASS ---DDR 2D-Training @2000Mhz... [Process] End of initialization [Process] End of 2D write delay/voltage center optimization [Process] End of 2D write delay/voltage center optimization [Process] End of 2D read delay/voltage center optimization [Process] End of 2D read delay/voltage center optimization [Result] PASS ============ Step 2: DDR memory accessing... ============ Verifying DDR frequency [email protected] [Result] OK ============ Step 3: DDR parameters processing... ============ [Result] Done Success: DDR Calibration completed!!! Download is completeWaiting for the target board boot...===================hardware_init=====================hardware_init exit***************************************************************************************************************************************************************************************************************************MX8 DDR Stress Test V3.30Built on Nov 24 2021 13:52:12*************************************************************************Waiting for board configuration from PC-end...--Set up the MMU and enable I and D cache--- This is the Cortex-A53 core- Check if I cache is enabled- Enabling I cache since it was disabled- Push base address of TTB to TTBR0_EL3- Config TCR_EL3- Config MAIR_EL3- Enable MMU- Data Cache has been enabled- Check system memory register, only for debug- VMCR Check:- ttbr0_el3: 0x97d000- tcr_el3: 0x2051c- mair_el3: 0x774400- sctlr_el3: 0xc01815- id_aa64mmfr0_el1: 0x1122- MMU and cache setup complete*************************************************************************ARM clock(CA53) rate: 1800MHzDDR Clock: 2000MHz============================================DDR configurationDDR type is LPDDR4Data width: 32, bank num: 8Row size: 17, col size: 10Two chip selects are usedNumber of DDR controllers used on the SoC: 1Density per chip select: 3072MBDensity per controller is: 6144MBTotal density detected on the board is: 6144MB============================================MX8M-plus: Cortex-A53 is found*************************************************************************============ Step 1: DDRPHY Training... ============---DDR 1D-Training @2000Mhz...[Process] End of initialization[Process] End of read enable training[Process] End of fine write leveling[Process] End of read DQ deskew training[Process] End of MPR read delay center optimization[Process] End of Write Leveling coarse delay[Process] End of write delay center optimization[Process] End of read delay center optimization[Process] End of max read latency training[Result] PASS---DDR 2D-Training @2000Mhz...[Process] End of initialization[Process] End of 2D write delay/voltage center optimization[Process] End of 2D write delay/voltage center optimization[Process] End of 2D read delay/voltage center optimization[Process] End of 2D read delay/voltage center optimization[Result] PASS============ Step 2: DDR memory accessing... ============Verifying DDR frequency [email protected][Result] OK============ Step 3: DDR parameters processing... ============[Result] DoneSuccess: DDR Calibration completed!!! If multiple frequency setpoints are set, the optimization keeps failing at the second setpoint And the stress test started passing correctly both in the Mtool and in the Config tool. However, the Diag read margin, diag write margin and CA eye tests keep failing One thing to note is that comparing to the IMX8MP-EVK we connected the CA and CB to their respective pins on the CPU (in the EVK they were reversed) Here are the respective lanes lengths and the delay deltas Spoiler (Highlight to read) 1. CAx_B, CKE_A, CK_CS_A - 20mm, <1ps 2. CAx_B, CKE_B, CK_CS_B - 19mm, <1ps 3. DQ07_A - 15mm, <1ps 4. DQ07_B - 14.5mm, <1ps 5. DQ815_A -10mm, <1ps 6. DQ815_B -10mm, <1ps 7. CKA - 21mm, DQS0 - 15mm (-22ps to CKA), DQS1 - 13mm (-55ps to CKA) 8. CKB - 21mm, DQS2 - 14mm (-24ps to CKA), DQS3 - 13mm (-54ps to CKA) 1. CAx_B, CKE_A, CK_CS_A - 20mm, <1ps2. CAx_B, CKE_B, CK_CS_B - 19mm, <1ps3. DQ07_A - 15mm, <1ps4. DQ07_B - 14.5mm, <1ps5. DQ815_A -10mm, <1ps6. DQ815_B -10mm, <1ps7. CKA - 21mm, DQS0 - 15mm (-22ps to CKA), DQS1 - 13mm (-55ps to CKA)8. CKB - 21mm, DQS2 - 14mm (-24ps to CKA), DQS3 - 13mm (-54ps to CKA) Can the CA/CB swap be the reason of the problem? 回复： i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) @AlexandrP , @sfatyushkin ,@JorgeCas ,Hi, We designed a custom board based with MIMX8ML4xxxKZ, However, when testing the DDR, even the initial phy init failed, and the error message was as follows: ```txt test-prefix : "C:/nxp/i.MX_CFG_25.12/bin/python3/python" "C:/nxp/i.MX_CFG_25.12/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_25.12/processors/MIMX8ML4xxxKZ/ksdk2_0/mem_validation/ddrc" -a "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/test_app_phy_test_0_0_.log" -p "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/phy_training_phy_test_0_0_.log" -l INFO "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/test.json" "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/ddrc_config_in.json" INFO memtool.utils.helper *****C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/connect.json INFO memtool.utils.helper *****C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/test.json INFO memtool.utils.helper *****C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/phy.json INFO memtool.utils.helper *****C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/ddrc_registers.json INFO memtool.utils.helper *****C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/ddrc_config.json INFO memtool.utils.helper *****C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/ddrc_config_in.json INFO memtool.processor.imx8m.imx8_processor Xls mapping load time 0.011705 INFO memtool.processor.base_processor Config time 0.008170 INFO memtool.processor.base_processor DS file time 0.256190 INFO memtool.phyinit.phy_init Run phyinit for 2020.06\lpddr4 INFO memtool.comm.serial_channel Using serial: COM23 WARNING memtool.comm.serial_channel Timeout waiting for response "[TARGET IS ALIVE]" ERROR memtool.common.base_test Application is not waiting for input state. WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" ERROR memtool.comm.serial_channel Read symbol failed after 3 tries WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" ERROR memtool.comm.serial_channel Read symbol failed after 3 tries WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" ERROR memtool.comm.serial_channel Read symbol failed after 3 tries WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" ERROR memtool.comm.serial_channel Read symbol failed after 3 tries WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" ERROR memtool.comm.serial_channel Read symbol failed after 3 tries {'app_state': -1, 'num_records': -1, 'records': [], 'debug': -1, 'err_capt_regs': -1, 'debug_regs': -1} ****DONE**** ``` Since this is my first time using IMX8, could you give me some advice? Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hello, According to constraint manager, the routing is under the recommended values: Best regards. Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) 127 + 50 ps < 191ps Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hello, 1) A clock frequency reduction, but it is not a warranty that will work.  2) It is under the recommendation, ±50 ps. Best regards. Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Jorge, thanks a lot! This helped us to understand the problem. When laying out the LpDDR lines, we used the same rules as before when laying out iMX8MM, without paying attention to the tightening of the requirements for the CAx lines (within 2 ps in groups), and did not take into account the Pkg delay. So, two questions. 1. Is it possible to configure the CA_x_y lines and run the board with a spread of CA lines times of about 20 ps (possibly at a slow speed), or it is impossible to do without redesigning the board? 2. In the i.MX 8M Plus Hardware Developer’s Guide, all timings seems like in EVK. But the delay on the CK_A lines is indicated to be about 107 ps (145 ps taking into account the Pkg delay). On the EVK board (directly in the project that you provided), I see a delay on the CKa lines of about 89 ps (127 ps taking into account the Pkg delay, and this is outside the 50 ps tolerance for the CA_A_0...4 lines). What is correct? Best regards, Serge Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hello, The issue you are mentioning could be caused by marginal signal integrity or timing violations. Please take a look in attached file for .alg file. Best regards. Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Based on your response we decided to tackle the ODT parameters once again. We redid the Read/Write ODT and driver matrix in Optimization tab and noticed that some random ODT combinations drop 'Target a connection or exception in the script'. Saying random, I mean that from run to run they are different and don't occur every time. Otherwise, the rest of the combinations succeed, even up to 240 Ohm We also evaluated the "Diag Read/Write Margin tests results more closely. Before, only the fact that test showed "checkmark 100%" was viewed , and noticed that whenever test "passes" it demonstrates not all of the DQ lanes, and the number is different every time. See attached pictures (for some reason the forum doesn't let me attach pictures neither in text, nor as attachments, so adding link to drive folder https://drive.google.com/drive/folders/1U4-G1_Em-73UR1zrtUFAsVCRBpAlchGN?usp=sharing) Trying to investigate this, we observed the 1V1 power lane with the oscilloscope, didn't notice anything extra suspicious, but during that the "Diag Margin" test started to show the Eye diagrams for all of the DQ lanes in more or less okay shape, so we added 9.5pF capacitor (see the attachment with "cond" for reference), and the Margin Test results in all DQ lanes diagrams every time it shows anything CA Bus Signals Margin test as well shows "Checkmark 100%", but in the "Charts" tab it states "Collecting diagnostic data..." and in logs it shows error "CA data is missing!" See full log in spoiler Spoiler (Highlight to read) #################### Result for: ca_bus ###### Run 1 ############################################### Microsoft Windows [Version 10.0.19045.2965] (c) Microsoft Corporation. All rights reserved. C:\nxp\i.MX_CFG_25.03\bin>prompt test-prefix : test-prefix : "C:/nxp/i.MX_CFG_25.03/bin/python3/python" "C:/nxp/i.MX_CFG_25.03/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_25.03/processors/MIMX8ML8xxxKZ/ksdk2_0/mem_validation/ddrc" -p "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy_training_ca_bus_lpddr4_0_0_.log" -i "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/figure_ca_bus_lpddr4_0_0_.png" -l DEBUG "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json" INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.processor.base_processor freq_0 set to 667 INFO memtool.phyinit.phy_init Run phyinit for 2020.06\lpddr4 DEBUG memtool.phyinit.phy_init Shared library C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\phyinit\sharedlib\phyinit_2020.06_lpddr4.dll DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.json DEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt DEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt DEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt DEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt DEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWER DEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210) DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.c DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.json DEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445) DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465) DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.bin DEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txt DEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850) DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869) DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885) DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.bin DEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txt DEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716) DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782) DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txt DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.json DEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389) DEBUG memtool.phyinit.out_parser Parse retention register list INFO memtool.comm.serial_channel Using serial: COM3 DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.comm.serial_channel Channel is not alive DEBUG spsdk.utils.interfaces.device.usb_device Closing the Interface: SE Blank 865 (0x1FC9, 0x0146)path=b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}' sn='' DEBUG memtool.comm.serial_channel ==================hardware_init======================= DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup... DEBUG memtool.comm.serial_channel [INFO]: ARM core clock rate is 1800MHz... DEBUG memtool.comm.serial_channel [INFO]: DDR Dram frequency is 666MHz... DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup ended... DEBUG memtool.comm.serial_channel ==================hardware_init exit================== DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read app state WAIT_FOR_INPUT INFO memtool.common.base_test Write app log level DEBUG memtool.comm.serial_channel Executing: Mw92F510,1:0000000a INFO memtool.common.base_test Write app state CONFIG_RECEIVED DEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:55aa55aa DEBUG test_app [DEBUG]: Initialize mailbox... DEBUG test_app [DEBUG]: Apply Init PHY Config... DEBUG test_app [DEBUG]: Execute PHY operation... DEBUG test_app [DEBUG]: Run PHY full init... DEBUG test_app [DEBUG]: Write 1D imem image, offset 0x00050000 size 0x00004000... DEBUG test_app [DEBUG]: End of load 1D imem image... DEBUG test_app [DEBUG]: Set DFI Clock for pstate 0... DEBUG test_app [DEBUG]: Write 1D dmem image, offset 0x00054000 size 0x0000033e... DEBUG test_app [DEBUG]: End of load 1D dmem image... DEBUG test_app [INFO]: Execute Training Firmware for 1D pstate0@667MHz... DEBUG test_app [INFO]: Training Firmware completed for 1D pstate0@667MHz with status 0; Execution ended in 0s.310ms.912us... DEBUG test_app [DEBUG]: PHY operation ended with status 0... DEBUG memtool.comm.serial_channel Executing: mw92F918,1 DEBUG memtool.comm.serial_channel Result: 0x00000000 DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read app state WAIT_FOR_INPUT INFO memtool.common.base_test Read phy status DEBUG memtool.comm.serial_channel Executing: mw92F91C,1 DEBUG memtool.comm.serial_channel Result: 0x00000059 INFO root Number of logged items 0x59 DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4\lpddr4_pmu_train.strings DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4_2d\lpddr4_2d_pmu_train.strings DEBUG memtool.comm.serial_channel Executing: mb961000,400 DEBUG memtool.comm.serial_channel Executing: mb961400,400 DEBUG memtool.comm.serial_channel Executing: mb961800,400 DEBUG memtool.comm.serial_channel Executing: mb961C00,400 DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read app state WAIT_FOR_INPUT INFO memtool.common.base_test Write input param test = 200 DEBUG memtool.comm.serial_channel Executing: Mw92EA10,1:000000c8 INFO memtool.common.base_test Write app state INPUT_RECEIVED DEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:77665544 DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read symbol app_state = 0x5588dcfe DEBUG memtool.comm.serial_channel Executing: mw92EABC,1 DEBUG memtool.comm.serial_channel Result: 0x00000001 INFO memtool.common.base_test Read symbol num_records = 0x1 INFO memtool.common.base_test App state WAIT_FOR_INPUT DEBUG memtool.comm.serial_channel Executing: mw92EF40,8 DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read symbol debug = [0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.comm.serial_channel Executing: mw92EF60,A DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read symbol err_capt_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.comm.serial_channel Executing: mw92EF88,20 DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read symbol debug_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.comm.serial_channel Executing: mw92EAC0,1 DEBUG memtool.comm.serial_channel Result: 0x00000001 INFO memtool.common.base_test Read symbol state = 1 DEBUG memtool.comm.serial_channel Executing: mw92EAC4,1 DEBUG memtool.comm.serial_channel Result: 0x000000C8 INFO memtool.common.base_test Read symbol test_id = 200 INFO memtool.common.base_test Record 0 state TestStatus.PASS DEBUG memtool.comm.serial_channel Executing: mw92EAC8,10 DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read test data [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Test 200 finished with state 1 DEBUG memtool.common.base_test App state: WAIT_FOR_INPUT DEBUG memtool.common.base_test Err_caption_registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.common.base_test Debug: [0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.common.base_test Debug registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.common.base_test Results: [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}] DEBUG memtool.common.base_test Number of records: 1 ERROR memtool.memtests.phy_diags_tests CA data is missing! {'app_state': 1435032830, 'num_records': 1, 'records': [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}], 'debug': '[0, 0, 0, 0, 0, 0, 0, 0]', 'err_capt_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0]', 'debug_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'} ****DONE**** #################### Result for: ca_bus ###### Run 1 ###############################################Microsoft Windows [Version 10.0.19045.2965](c) Microsoft Corporation. All rights reserved.C:\nxp\i.MX_CFG_25.03\bin>prompt test-prefix :test-prefix : "C:/nxp/i.MX_CFG_25.03/bin/python3/python" "C:/nxp/i.MX_CFG_25.03/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_25.03/processors/MIMX8ML8xxxKZ/ksdk2_0/mem_validation/ddrc" -p "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy_training_ca_bus_lpddr4_0_0_.log" -i "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/figure_ca_bus_lpddr4_0_0_.png" -l DEBUG "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json"INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.jsonDEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.processor.base_processor freq_0 set to 667INFO memtool.phyinit.phy_init Run phyinit for 2020.06\lpddr4DEBUG memtool.phyinit.phy_init Shared library C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\phyinit\sharedlib\phyinit_2020.06_lpddr4.dllDEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.jsonDEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txtDEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txtDEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txtDEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txtDEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWERDEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210)DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.cDEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.jsonDEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445)DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465)DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.binDEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txtDEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850)DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869)DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885)DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.binDEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txtDEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716)DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782)DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txtDEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.jsonDEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389)DEBUG memtool.phyinit.out_parser Parse retention register listINFO memtool.comm.serial_channel Using serial: COM3DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.comm.serial_channel Channel is not aliveDEBUG spsdk.utils.interfaces.device.usb_device Closing the Interface: SE Blank 865 (0x1FC9, 0x0146)path=b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}' sn=''DEBUG memtool.comm.serial_channel ==================hardware_init=======================DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel [DEBUG]: Clock setup...DEBUG memtool.comm.serial_channel [INFO]: ARM core clock rate is 1800MHz...DEBUG memtool.comm.serial_channel [INFO]: DDR Dram frequency is 666MHz...DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup ended...DEBUG memtool.comm.serial_channel ==================hardware_init exit==================DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveDEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read app state WAIT_FOR_INPUTINFO memtool.common.base_test Write app log levelDEBUG memtool.comm.serial_channel Executing: Mw92F510,1:0000000aINFO memtool.common.base_test Write app state CONFIG_RECEIVEDDEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:55aa55aaDEBUG test_app [DEBUG]: Initialize mailbox...DEBUG test_app [DEBUG]: Apply Init PHY Config...DEBUG test_app [DEBUG]: Execute PHY operation...DEBUG test_app [DEBUG]: Run PHY full init...DEBUG test_app [DEBUG]: Write 1D imem image, offset 0x00050000 size 0x00004000...DEBUG test_app [DEBUG]: End of load 1D imem image...DEBUG test_app [DEBUG]: Set DFI Clock for pstate 0...DEBUG test_app [DEBUG]: Write 1D dmem image, offset 0x00054000 size 0x0000033e...DEBUG test_app [DEBUG]: End of load 1D dmem image...DEBUG test_app [INFO]: Execute Training Firmware for 1D [email protected] test_app [INFO]: Training Firmware completed for 1D pstate0@667MHz with status 0; Execution ended in 0s.310ms.912us...DEBUG test_app [DEBUG]: PHY operation ended with status 0...DEBUG memtool.comm.serial_channel Executing: mw92F918,1DEBUG memtool.comm.serial_channel Result: 0x00000000DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveDEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read app state WAIT_FOR_INPUTINFO memtool.common.base_test Read phy statusDEBUG memtool.comm.serial_channel Executing: mw92F91C,1DEBUG memtool.comm.serial_channel Result: 0x00000059INFO root Number of logged items 0x59DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4\lpddr4_pmu_train.stringsDEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4_2d\lpddr4_2d_pmu_train.stringsDEBUG memtool.comm.serial_channel Executing: mb961000,400DEBUG memtool.comm.serial_channel Executing: mb961400,400DEBUG memtool.comm.serial_channel Executing: mb961800,400DEBUG memtool.comm.serial_channel Executing: mb961C00,400DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveDEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read app state WAIT_FOR_INPUTINFO memtool.common.base_test Write input param test = 200DEBUG memtool.comm.serial_channel Executing: Mw92EA10,1:000000c8INFO memtool.common.base_test Write app state INPUT_RECEIVEDDEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:77665544DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read symbol app_state = 0x5588dcfeDEBUG memtool.comm.serial_channel Executing: mw92EABC,1DEBUG memtool.comm.serial_channel Result: 0x00000001INFO memtool.common.base_test Read symbol num_records = 0x1INFO memtool.common.base_test App state WAIT_FOR_INPUTDEBUG memtool.comm.serial_channel Executing: mw92EF40,8DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read symbol debug = [0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.comm.serial_channel Executing: mw92EF60,ADEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read symbol err_capt_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.comm.serial_channel Executing: mw92EF88,20DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read symbol debug_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.comm.serial_channel Executing: mw92EAC0,1DEBUG memtool.comm.serial_channel Result: 0x00000001INFO memtool.common.base_test Read symbol state = 1DEBUG memtool.comm.serial_channel Executing: mw92EAC4,1DEBUG memtool.comm.serial_channel Result: 0x000000C8INFO memtool.common.base_test Read symbol test_id = 200INFO memtool.common.base_test Record 0 state TestStatus.PASSDEBUG memtool.comm.serial_channel Executing: mw92EAC8,10DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read test data [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Test 200 finished with state 1DEBUG memtool.common.base_test App state: WAIT_FOR_INPUTDEBUG memtool.common.base_test Err_caption_registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.common.base_test Debug: [0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.common.base_test Debug registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.common.base_test Results: [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}]DEBUG memtool.common.base_test Number of records: 1ERROR memtool.memtests.phy_diags_tests CA data is missing!{'app_state': 1435032830, 'num_records': 1, 'records': [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}], 'debug': '[0, 0, 0, 0, 0, 0, 0, 0]', 'err_capt_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0]', 'debug_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}****DONE**** "CA Eye" always runs into timeout, I tried different values for "ATXImpedance" and with value of 20Ohm it's able to run longer for about one cycle, but in the end it still times out. See the full log in the spoiler Spoiler (Highlight to read) #################### Result for: ca_eye ###### Run 1 ###############################################Microsoft Windows [Version 10.0.19045.2965] (c) Microsoft Corporation. All rights reserved. C:\nxp\i.MX_CFG_25.03\bin>prompt test-prefix : test-prefix : "C:/nxp/i.MX_CFG_25.03/bin/python3/python" "C:/nxp/i.MX_CFG_25.03/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_25.03/processors/MIMX8ML8xxxKZ/ksdk2_0/mem_validation/ddrc" -p "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy_training_ca_eye_lpddr4_0_0_.log" -i "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/figure_ca_eye_lpddr4_0_0_.png" -l DEBUG "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json" INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.processor.base_processor freq_0 set to 667 INFO memtool.phyinit.phy_init Run phyinit for 2020.06\lpddr4 DEBUG memtool.phyinit.phy_init Shared library C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\phyinit\sharedlib\phyinit_2020.06_lpddr4.dll DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.json DEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt DEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt DEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt DEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt DEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWER DEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210) DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.c DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.json DEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445) DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465) DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.bin DEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txt DEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850) DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869) DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885) DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.bin DEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txt DEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716) DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782) DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txt DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.json DEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389) DEBUG memtool.phyinit.out_parser Parse retention register list INFO memtool.comm.serial_channel Using serial: COM3 DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive INFO memtool.comm.serial_channel Send reset to target DEBUG memtool.comm.serial_channel Executing: R DEBUG spsdk.utils.interfaces.device.usb_device Closing the Interface: SE Blank 865 (0x1FC9, 0x0146)path=b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}' sn='' DEBUG memtool.comm.serial_channel ==================hardware_init======================= DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup... DEBUG memtool.comm.serial_channel [INFO]: ARM core clock rate is 1800MHz... DEBUG memtool.comm.serial_channel [INFO]: DDR Dram frequency is 666MHz... DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup ended... DEBUG memtool.comm.serial_channel ==================hardware_init exit================== DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read app state WAIT_FOR_INPUT INFO memtool.common.base_test Write app log level DEBUG memtool.comm.serial_channel Executing: Mw92F510,1:0000000a INFO memtool.common.base_test Write app state CONFIG_RECEIVED DEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:55aa55aa DEBUG test_app [DEBUG]: Initialize mailbox... DEBUG test_app [DEBUG]: Apply Init PHY Config... DEBUG test_app [DEBUG]: Execute PHY operation... DEBUG test_app [DEBUG]: Run PHY full init... DEBUG test_app [DEBUG]: Write 1D imem image, offset 0x00050000 size 0x00004000... DEBUG test_app [DEBUG]: End of load 1D imem image... DEBUG test_app [DEBUG]: Set DFI Clock for pstate 0... DEBUG test_app [DEBUG]: Write 1D dmem image, offset 0x00054000 size 0x0000033e... DEBUG test_app [DEBUG]: End of load 1D dmem image... DEBUG test_app [INFO]: Execute Training Firmware for 1D pstate0@667MHz... DEBUG test_app [INFO]: Training Firmware completed for 1D pstate0@667MHz with status 0; Execution ended in 0s.310ms.898us... DEBUG test_app [DEBUG]: PHY operation ended with status 0... DEBUG memtool.comm.serial_channel Executing: mw92F918,1 DEBUG memtool.comm.serial_channel Result: 0x00000000 DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read app state WAIT_FOR_INPUT INFO memtool.common.base_test Read phy status DEBUG memtool.comm.serial_channel Executing: mw92F91C,1 DEBUG memtool.comm.serial_channel Result: 0x00000059 INFO root Number of logged items 0x59 DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4\lpddr4_pmu_train.strings DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4_2d\lpddr4_2d_pmu_train.strings DEBUG memtool.comm.serial_channel Executing: mb961000,400 DEBUG memtool.comm.serial_channel Executing: mb961400,400 DEBUG memtool.comm.serial_channel Executing: mb961800,400 DEBUG memtool.comm.serial_channel Executing: mb961C00,400 DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read app state WAIT_FOR_INPUT INFO memtool.common.base_test Write input param test = 200 DEBUG memtool.comm.serial_channel Executing: Mw92EA10,1:000000c8 INFO memtool.common.base_test Write app state INPUT_RECEIVED DEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:77665544 DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read symbol app_state = 0x5588dcfe DEBUG memtool.comm.serial_channel Executing: mw92EABC,1 DEBUG memtool.comm.serial_channel Result: 0x00000001 INFO memtool.common.base_test Read symbol num_records = 0x1 INFO memtool.common.base_test App state WAIT_FOR_INPUT DEBUG memtool.comm.serial_channel Executing: mw92EF40,8 DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read symbol debug = [0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.comm.serial_channel Executing: mw92EF60,A DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read symbol err_capt_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.comm.serial_channel Executing: mw92EF88,20 DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read symbol debug_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.comm.serial_channel Executing: mw92EAC0,1 DEBUG memtool.comm.serial_channel Result: 0x00000001 INFO memtool.common.base_test Read symbol state = 1 DEBUG memtool.comm.serial_channel Executing: mw92EAC4,1 DEBUG memtool.comm.serial_channel Result: 0x000000C8 INFO memtool.common.base_test Read symbol test_id = 200 INFO memtool.common.base_test Record 0 state TestStatus.PASS DEBUG memtool.comm.serial_channel Executing: mw92EAC8,10 DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read test data [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Test 200 finished with state 1 DEBUG memtool.common.base_test App state: WAIT_FOR_INPUT DEBUG memtool.common.base_test Err_caption_registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.common.base_test Debug: [0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.common.base_test Debug registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.common.base_test Results: [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}] DEBUG memtool.common.base_test Number of records: 1 DEBUG memtool.processor.base_processor freq_0 set to 667 DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.json DEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt DEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt DEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt DEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt DEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWER DEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210) DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.c DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.json DEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445) DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465) DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.bin DEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txt DEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850) DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869) DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885) DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.bin DEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txt DEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716) DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782) DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txt DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.json DEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389) DEBUG memtool.phyinit.out_parser Parse retention register list DEBUG memtool.common.factories new instance -> {inst} {'app_state': 1435032830, 'num_records': 1, 'records': [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}], 'debug': '[0, 0, 0, 0, 0, 0, 0, 0]', 'err_capt_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0]', 'debug_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'} DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive INFO memtool.comm.serial_channel Send reset to target DEBUG memtool.comm.serial_channel Executing: R ERROR libusbsio.hidapi.dev HID device 'b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}'' opening failed. ERROR memtool.common.base_test Application load ended with exception: Download incomplete due to configuration error! DEBUG memtool.comm.serial_channel Executing: mw92F918,1 #################### Result for: ca_eye ###### Run 1 ###############################################Microsoft Windows [Version 10.0.19045.2965](c) Microsoft Corporation. All rights reserved.C:\nxp\i.MX_CFG_25.03\bin>prompt test-prefix :test-prefix : "C:/nxp/i.MX_CFG_25.03/bin/python3/python" "C:/nxp/i.MX_CFG_25.03/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_25.03/processors/MIMX8ML8xxxKZ/ksdk2_0/mem_validation/ddrc" -p "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy_training_ca_eye_lpddr4_0_0_.log" -i "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/figure_ca_eye_lpddr4_0_0_.png" -l DEBUG "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json"INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.jsonDEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.processor.base_processor freq_0 set to 667INFO memtool.phyinit.phy_init Run phyinit for 2020.06\lpddr4DEBUG memtool.phyinit.phy_init Shared library C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\phyinit\sharedlib\phyinit_2020.06_lpddr4.dllDEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.jsonDEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txtDEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txtDEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txtDEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txtDEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWERDEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210)DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.cDEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.jsonDEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445)DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465)DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.binDEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txtDEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850)DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869)DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885)DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.binDEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txtDEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716)DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782)DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txtDEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.jsonDEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389)DEBUG memtool.phyinit.out_parser Parse retention register listINFO memtool.comm.serial_channel Using serial: COM3DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveINFO memtool.comm.serial_channel Send reset to targetDEBUG memtool.comm.serial_channel Executing: RDEBUG spsdk.utils.interfaces.device.usb_device Closing the Interface: SE Blank 865 (0x1FC9, 0x0146)path=b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}' sn=''DEBUG memtool.comm.serial_channel ==================hardware_init=======================DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel [DEBUG]: Clock setup...DEBUG memtool.comm.serial_channel [INFO]: ARM core clock rate is 1800MHz...DEBUG memtool.comm.serial_channel [INFO]: DDR Dram frequency is 666MHz...DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup ended...DEBUG memtool.comm.serial_channel ==================hardware_init exit==================DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveDEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read app state WAIT_FOR_INPUTINFO memtool.common.base_test Write app log levelDEBUG memtool.comm.serial_channel Executing: Mw92F510,1:0000000aINFO memtool.common.base_test Write app state CONFIG_RECEIVEDDEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:55aa55aaDEBUG test_app [DEBUG]: Initialize mailbox...DEBUG test_app [DEBUG]: Apply Init PHY Config...DEBUG test_app [DEBUG]: Execute PHY operation...DEBUG test_app [DEBUG]: Run PHY full init...DEBUG test_app [DEBUG]: Write 1D imem image, offset 0x00050000 size 0x00004000...DEBUG test_app [DEBUG]: End of load 1D imem image...DEBUG test_app [DEBUG]: Set DFI Clock for pstate 0...DEBUG test_app [DEBUG]: Write 1D dmem image, offset 0x00054000 size 0x0000033e...DEBUG test_app [DEBUG]: End of load 1D dmem image...DEBUG test_app [INFO]: Execute Training Firmware for 1D [email protected] test_app [INFO]: Training Firmware completed for 1D pstate0@667MHz with status 0; Execution ended in 0s.310ms.898us...DEBUG test_app [DEBUG]: PHY operation ended with status 0...DEBUG memtool.comm.serial_channel Executing: mw92F918,1DEBUG memtool.comm.serial_channel Result: 0x00000000DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveDEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read app state WAIT_FOR_INPUTINFO memtool.common.base_test Read phy statusDEBUG memtool.comm.serial_channel Executing: mw92F91C,1DEBUG memtool.comm.serial_channel Result: 0x00000059INFO root Number of logged items 0x59DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4\lpddr4_pmu_train.stringsDEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4_2d\lpddr4_2d_pmu_train.stringsDEBUG memtool.comm.serial_channel Executing: mb961000,400DEBUG memtool.comm.serial_channel Executing: mb961400,400DEBUG memtool.comm.serial_channel Executing: mb961800,400DEBUG memtool.comm.serial_channel Executing: mb961C00,400DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveDEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read app state WAIT_FOR_INPUTINFO memtool.common.base_test Write input param test = 200DEBUG memtool.comm.serial_channel Executing: Mw92EA10,1:000000c8INFO memtool.common.base_test Write app state INPUT_RECEIVEDDEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:77665544DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read symbol app_state = 0x5588dcfeDEBUG memtool.comm.serial_channel Executing: mw92EABC,1DEBUG memtool.comm.serial_channel Result: 0x00000001INFO memtool.common.base_test Read symbol num_records = 0x1INFO memtool.common.base_test App state WAIT_FOR_INPUTDEBUG memtool.comm.serial_channel Executing: mw92EF40,8DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read symbol debug = [0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.comm.serial_channel Executing: mw92EF60,ADEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read symbol err_capt_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.comm.serial_channel Executing: mw92EF88,20DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read symbol debug_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.comm.serial_channel Executing: mw92EAC0,1DEBUG memtool.comm.serial_channel Result: 0x00000001INFO memtool.common.base_test Read symbol state = 1DEBUG memtool.comm.serial_channel Executing: mw92EAC4,1DEBUG memtool.comm.serial_channel Result: 0x000000C8INFO memtool.common.base_test Read symbol test_id = 200INFO memtool.common.base_test Record 0 state TestStatus.PASSDEBUG memtool.comm.serial_channel Executing: mw92EAC8,10DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read test data [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Test 200 finished with state 1DEBUG memtool.common.base_test App state: WAIT_FOR_INPUTDEBUG memtool.common.base_test Err_caption_registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.common.base_test Debug: [0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.common.base_test Debug registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.common.base_test Results: [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}]DEBUG memtool.common.base_test Number of records: 1DEBUG memtool.processor.base_processor freq_0 set to 667DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.jsonDEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txtDEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txtDEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txtDEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txtDEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWERDEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210)DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.cDEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.jsonDEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445)DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465)DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.binDEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txtDEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850)DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869)DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885)DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.binDEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txtDEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716)DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782)DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txtDEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.jsonDEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389)DEBUG memtool.phyinit.out_parser Parse retention register listDEBUG memtool.common.factories new instance -> {inst}{'app_state': 1435032830, 'num_records': 1, 'records': [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}], 'debug': '[0, 0, 0, 0, 0, 0, 0, 0]', 'err_capt_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0]', 'debug_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveINFO memtool.comm.serial_channel Send reset to targetDEBUG memtool.comm.serial_channel Executing: RERROR libusbsio.hidapi.dev HID device 'b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}'' opening failed.ERROR memtool.common.base_test Application load ended with exception: Download incomplete due to configuration error!DEBUG memtool.comm.serial_channel Executing: mw92F918,1 Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hi Jorge, 1. Could you please provide the data on the chain lengths and propagation delays of LpDDR signals in EVK? 2. Our CAD does not allow importing the EVK pcb file in the format it is posted on your site. Can you provide it in ASCII format? Best regards, Serge Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hello, Your DDR connection is ok. There is no functional problem in swap CA/CB since dual channel device channels are independent in LPDDR4, just keep in mind that bit swapping within each slice/byte lane is OK. Byte swapping is NOT allowed. If you still having signal integrity tests failed, please look for layout issues and try lower operating frequencies. You could try to change the tunning with different settings and check if helps with your design: ODTImpedance Desired ODT impedance in Ohm. Valid values for DDR4=240,120,80,60,40. Valid values for DDR3L=high-impedance,120,60,40. Valid values for LPDDR4=240,120,80,60,40 TxImpedance Write Driver Impedance for DQ/DQS in ohm (Valid values for all DDR type= 240, 120, 80, 60, 48, 40, 34) ATxImpedance Write Driver Impedance for Address/Command (AC) bus in ohm (Valid values for all DDR type = 120, 60, 40, 30, 24, 20) Best regards. Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hello @JorgeCas ! I am Alexander's colleague. Attached is the CPU and LPDDR connection diagram. Best regards, Serge Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hello, Could you please share the connections of memory to i.MX device? Best regards. Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Dear JorgeCas! Happy New Year! We made a new board and ran the memory at 1600 MHz. It doesn't run at higher speeds—we'll investigate this problem.. I compared the net lengths in the KIT in your picture with our calculations in EDA. 1. In the KIT, when calculating net lengths and delays, you didn't take the via lengths into account. 2. In the KIT, when calculating the CK_x_x signal path lengths, the additional sections to the resistors (R9, R10) were incorrectly added to calculated. Please comment on the KIT chain lengths highlighted in red. Best regards, Serge

PCS DSPI 始终处于活动状态 hi 早上好 我对 DSPI 的行为非常赞赏。使用 KV58 塔......SDK 中的示例运行正常。我可以选择 CS0 的极性。 我的应用程序使用的驱动程序 SPI 只是复制粘贴。而 CS0 始终处于激活状态。 我看了一遍又一遍......我找不到原因。 如果有人愿意花一点时间，我可以发送文件或整个项目。 我感谢每一份支持 皮耶罗 Re: PCS DSPI always active hi 你好，我是 ，我有一个了不起的修复和问题。 这是 DSPI 初始化的代码 static bool MCP23S17_DspiInit(void) { dspi_master_config_t masterConfig; uint32_t srcClock_Hz； CLOCK_EnableClock( kCLOCK_Spi0 ); DSPI_Deinit( MCP23S17_DSPI_BASE ); DSPI_MasterGetDefaultConfig(&masterConfig); masterConfig.whichCtar = MCP23S17_DSPI_CTAR; masterConfig.ctarConfig.baudRate = MCP23S17_SPI_BAUDRATE; masterConfig.ctarConfig.bitsPerFrame= MCP23S17_SPI_BITS_PER_FRAME; masterConfig.ctarConfig.cpol = MCP23S17_SPI_CPOL; masterConfig.ctarConfig.cpha = MCP23S17_SPI_CPHA; masterConfig.ctarConfig.direction = MCP23S17_SPI_SHIFT_DIR; masterConfig.ctarConfig.pcsToSckDelayInNanoSec= MCP23S17_DELAY_NS; masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec= MCP23S17_DELAY_NS; masterConfig.ctarConfig.betweenTransferDelayInNanoSec= MCP23S17_DELAY_NS; /* 启动时的默认 PCS；实际 PCS 由稍后通过 configFlags 选择 */ masterConfig.whichPcs = MCP23S17_DSPI_PCS0; masterConfig.pcsActiveHighOrLow= kDSPI_PcsActiveLow; masterConfig.enableContinuousSCK= false; masterConfig.enableRxFifoOverWrite= false; masterConfig.enableModifiedTimingFormat= false; masterConfig.samplePoint = kDSPI_SckToSin0Clock； srcClock_Hz = MCP23S17_DSPI_CLK_FREQ； if (srcClock_Hz == 0U) { return false; } DSPI_MasterInit(MCP23S17_DSPI_BASE,&masterConfig, srcClock_Hz)； SPI0->MCR |= (0x003F0000); return true; } 这里的惊喜是 SPI0->MCR |= (0x003F0000); 这一行需要存在 ..在初始化之后，尽管明确设置为低电平激活 CS，但 CS 始终为高电平激活。但 SDK 中的程序是一样的。因此， ，给我解释一下到底哪里出了问题。 谢谢 Pietro Re: PCS DSPI always active hi 你好@pietrodicastri 请参考 SPIx_MCR 寄存器中的 PCSIS 字段。当某位设置为 0 时，PCSx 的非活动状态为低电平，高电平表示活动状态。还需注意的是，该位的作用仅在模块启用时才会发生。确保在启用 SPI 接口前正确配置该位。 BR 爱丽丝

有关 FS32K144HAT0MMHT 功能安全外设驱动器 (SPD) 的询问——可用性和免费来源 队员们好 我们正在使用 FS32K144HAT0MMHT 微控制器启动一个新的 ISO 26262 (ASIL-B) 项目，并想了解功能安全外设驱动器 (SPD) 的工作原理。 我们在哪里可以下载 SPD 软件包，我们是否需要特定的软件包名称，如 NXP 软件许可证 & 支持门户中的 SW32K1-SPD-D？ SPD 是免费的还是包含在标准 RTD/SDK 下载中，还是需要单独的许可证？ 是否有研究 SPD 早期发展驱动因素的范例或免费资料？ 如能就查找 SPD 或相关资源提供指导，将不胜感激。 谢谢！ Re: Inquiry about Safety Peripheral Drivers (SPD) for FS32K144HAT0MMHT – Availability and Free Sourc 你好，@KAVINKUMAR7、 S32K1 — 功能安全外设驱动器 (SPD) 仅包含以下驱动程序： 适用于 S32K1 的 扩展 MCEM 驱动程序 ，版本 1.0.1 https://www.nxp.com/webapp/swlicensing/sso/downloadSoftware.sp?catid=SW32K1-SPD-D&_gl=1*ao7djc*_ga*M.... 该驱动程序包含在 S32K1xx 标准软件包中，该软件包免费提供。 它兼容 S32K1/S32M24x 实时驱动程序，ASR R21-11，版本 2.0.0 P04。 不过，该驱动程序没有提供功能示例。 此致， 丹尼尔 Re: Inquiry about Safety Peripheral Drivers (SPD) for FS32K144HAT0MMHT – Availability and Free Sourc 您好， 本 SPD 支持生产。请确认是否适合在生产环境中使用？ Re: Inquiry about Safety Peripheral Drivers (SPD) for FS32K144HAT0MMHT – Availability and Free Sourc 你好，@KAVINKUMAR7、 是的，确实如此。请参阅版本说明。 此版本为 RTM（准备生产）级别。 此致， 丹尼尔 Re: Inquiry about Safety Peripheral Drivers (SPD) for FS32K144HAT0MMHT – Availability and Free Sourc 你好， 感谢您的回复。 我已经安装了最新的 S32 Design Studio IDE，并使用了版本说明中提到的 RTM（准备制造）RTD SDK。CAN 示例项目是使用提供的 SDK 和配置工具直接生成的。 但是，即使使用了这个设置，我仍然面临以下版本错误： 致命错误：port_ci_port_port_IP_TYPES.H：以下位置不会出现此类文件或目录 错误： board/port_ci_port_IP_CFG.c: 56 #include " port_ci_port_port_port_IP_TYPES .H " Re: Inquiry about Safety Peripheral Drivers (SPD) for FS32K144HAT0MMHT – Availability and Free Sourc 你好，@KAVINKUMAR7、 看来这是一个兼容性问题。 在正确的 S32DS IDE 版本中，只能安装 SPD 发行说明中指定的兼容的 RTD 和 SPD。不应存在其他 RTD 版本。如果需要多个 RTD 版本，建议安装单独的 IDE 实例。 由于您的后续问题不再与 SPD 有关，如果您需要进一步帮助，请创建一个新的主题。 此致， 丹尼尔

李尔 - [S32K3] 利用 DMA 进行 SPI 异步传输 你好，团队、 李尔写道 ------------------------------------------------------------------------------------- 我们正在对一个需要控制许多 SPI 设备的用例进行微控制器可行性分析。我正在使用 S32K344 开发板，我已将 SPI4 和 SPI5 配置为定期与 5 台设备通信。我已经成功地使用中断模式采取了同步和异步写入措施，但在尝试使用 DMA 时却没有成功。 我按照 SPI UM 和 IM 中的提示进行了操作，也看了一些示例，但还是无法正常工作。 我附上了我的配置，信道16的DMA ISR产生了触发信号，但没有发送任何数据，而且由于中断标志未被清除，代码被卡在中断中。 能否支持我们通过 DMA 配置 SPI？ -------------------------------------------------------------------------- 优先级：高 优先级：中等 RTD Re: Lear - [S32K3] SPI async transmission with DMA 你好@StefanoGattazzo 附件中的文件是空的，您能再检查一下吗？ Re: Lear - [S32K3] SPI async transmission with DMA 您好 cuongnguyenphu, 我想，这种配置应该是 cjecked。 BR Stefano Re: Lear - [S32K3] SPI async transmission with DMA 你好@StefanoGattazzo 您是否为 Tx 和 Rx 使用了散射和收集配置？ - 如果不使用 -> 请取消选中 Mcl/MclConfig/dmaLogicChannel_Type/dmaLogicChannel_EnableScatterGather 选项： - 如果使用 Scatter/Gather： 确保勾选为所有 ScatterGatherArrayType 启用 Scatter/Gather 配置： Re: Lear - [S32K3] SPI async transmission with DMA 您好 cuongnguyenphu, 李尔正在回答： -------------------------------------------------------------------------------------- 在只使用全局配置的情况下，我们可以使 SPI 异步与 DMA 配合使用，但这种配置会因 DMA ISR 而对 CPU 负载造成很大影响，因此这种配置对我们的特定用例没有用处。 这就是为什么我想让它在启用散射/散射选项的情况下工作，看看在这种模式下 CPU 负载是否会有所改善。我按照您的建议为所有 ScatterGatherArrayType 启用了 Scatter/Gather Config，但还是出现了同样的问题。由于 MCAL 文档不清楚，我在此附上项目配置，请与你们的 RTD 团队分享，看看他们能否帮助我们完成此配置。 ------------------------------------------------------------------------------------ BR 斯特凡诺 Re: Lear - [S32K3] SPI async transmission with DMA @StefanoGattazzo 在启用散射/聚集配置后，我建议您参阅以下章节 3.6.6 如何为序列配置 Dma 快速传输 章节。 我查看了该指令，配置 SpiEnableDmaFastTransfer 非常清楚。 我看到您使用 LPSPI_4 进行 Dma 快速传输，因此请按照此指南进行操作。 在您的配置中，我还发现一点，那就是 JobStartNotification 和 JobEndNotification 并不符合指南的要求： 序列中的 第一个作业只能支持 SpiJobStartNotification 和 SpiJobEndNotification Re: Lear - [S32K3] SPI async transmission with DMA 您好 cuongnguyenphu, 李尔回复： 用户手册中的信息是不够的。它没有详细说明如何配置 ScatterGatter 频道，我一直在尝试不同的配置，但无法连续发送多个频道。 请举例说明或详细说明每个 scatterGather 通道需要配置的参数。 Re: Lear - [S32K3] SPI async transmission with DMA 我正在为您创建一个 Scatter/Gather DMA 示例。这将被视为 BSSM 申请。 同时，请建议他们为 MCL 模块中的 Tx/Rx DMA 逻辑通道启用该节点：启用 DMA 请求。 此节点允许外围设备触发 DMA 请求 Re: Lear - [S32K3] SPI async transmission with DMA 您好 cuongnguyenphu, 李尔回答道： 难道不能召开一次调试会议，让我们审查配置，并由 RTD 团队支持我们进行测试吗？ 请提供合适的时间段和与会者。 Pd：我已启用 DMA 请求，但没有任何变化。 BR Stefano Re: Lear - [S32K3] SPI async transmission with DMA @StefanoGattazzo 我通过电子邮件将示例发给了李尔 Re: Lear - [S32K3] SPI async transmission with DMA 您好 cuongnguyenphu, 请发送至 [email protected] 我在度假。 谢谢，BR Stefano Re: Lear - [S32K3] SPI async transmission with DMA @StefanoGattazzo 请帮我测试一下这个例子，然后再发给李尔。 我创建了 1 个序列 Lpspi_1，其中 1 个工作 2 个通道以 SPI DMA 快速传输方式发送。 请按照 description.txt 进行构建和导线连接

应使用哪个 SDK 才能满足 FS32K144HAT0MMHT 的 ASIL B 标准？ 在 FS32K144HAT0MMHT 微控制器上开发符合 ASIL-B 标准的固件时，推荐使用哪种软件开发工具包 (SDK)？此外，应遵循哪些特定的固件设计实践、功能安全机制和实施指南，以确保完全符合 ASIL-B？ Re: Which SDK should be used to meet ASIL B standards for the FS32K144HAT0MMHT, and how can the firm 感谢您的回复。恩智浦网站提到 S32K144 支持某些 SCST 库。这些库的目的是什么，我们如何对其进行测试？ Lib 链接：结构核心自测 (SCST) 库| 恩智浦半导体 Re: Which SDK should be used to meet ASIL B standards for the FS32K144HAT0MMHT, and how can the firm 嗨，@ARIVALAGAN、 SDK 的开发并不符合 ISO26262 标准，而是采用了质量管理流程。 您可以参考实时驱动程序 (RTD)。它们以AUTOSAR 应用为目标，完全符合 ISO 26262 标准。 关于设计实践、机制、实施等，请记住，这些考虑因素完全由客户决定，以及项目需要满足的功能安全标准，因为ASIL等级适用于整个ECU系统。我的同事在另一个社区主题中对此做了更详细的解释：已解决：是什么让 MCU 符合 ASIL 标准？- 恩智浦社区。 RTD 和 S32K1 均被设计为独立安全单元 (SEOOC)，集成到 B 级以下的 ASIL 应用程序（S32K3 + RTD 最高可达 ASIL D）。因此，RTD 是一种旨在集成到应用程序中的软件，ASIL 级别取决于集成环境，使用的假设是功能安全软件包中提供的功能安全手册的一部分。 功能安全实施需要遵循一些文档、指南和软件，例如： AN14068-S32K3/S32K1 + FS23 硬件和功能安全应用-应用笔记 S32 框架提高车辆功能安全 | 恩智浦半导体 其余大部分文档在"Secure Files" 下。请遵循本指南：如何申请访问恩智浦的恩智浦微控制器和MPU功能安全文档。 致以最崇高的敬意， Julián。 Re: Which SDK should be used to meet ASIL B standards for the FS32K144HAT0MMHT, and how can the firm 嗨，@ARIVALAGAN、 SCST 符合 ISO 26262 功能安全标准，最高可达 ASIL B，目标诊断覆盖率 (DC) 为 90%。 所包含的测试涵盖了大部分内核指令，以及针对内核特定 IP 块的测试。主要是 核心控制逻辑（分支控制、异常控制） 核心数据路径包括 寄存器文件和寄存器复用 ALU、乘法器、加载/存储和其他执行单元。 指令解码器，16 位，32 位。 SIMD 逻辑 请记住，这是一款授权的高级软件。有关定价和订购的详细信息，请联系当地的恩智浦销售办事处。该软件包包括用户手册文档。 致以最诚挚的问候， Julián Re: Which SDK should be used to meet ASIL B standards for the FS32K144HAT0MMHT, and how can the firm 嗨，@ARIVALAGAN、 1.我无法与公众分享直接支持的联系方式。该空间严格用于技术支持。请改为联系您的代理商。 2.是的。SPD 是免费的标准软件，包含在硅片价格中： SW32K1-SPD-D 。请注意，SPD 需要特定的 RTD 软件包。它在版本说明文件中提到。 致以最诚挚的问候， Julián Re: Which SDK should be used to meet ASIL B standards for the FS32K144HAT0MMHT, and how can the firm 我还有一个疑问... 功能安全外设驱动器-FS32K144HAT0MMHT 免费吗 https://www.nxp.com/design/design-center/software/functional-safety-software/s32-safety-software-framework-saf-and-safety-peripheral-drivers-spd:SAF Re: Which SDK should be used to meet ASIL B standards for the FS32K144HAT0MMHT, and how can the firm 我能否获得技术支持团队在印度（钦奈和班加罗尔）的电子邮件 ID？ Re: Which SDK should be used to meet ASIL B standards for the FS32K144HAT0MMHT, and how can the firm 如何使用 Design Studio 软件在 S32K1 RTD 驱动器中使用 SPD？ 有适当的文件吗？ 能否推荐任何支持 SPD 的 RTD 版本？ Re: Which SDK should be used to meet ASIL B standards for the FS32K144HAT0MMHT, and how can the firm Hi@ARIVALAGAN SPD 不是免费的； 请联系您的代理商或恩智浦销售人员了解更多信息。 https://www.nxp.com/support/sample-and-buy/distributor-network:DISTRIBUTORS "我能否获得技术支持团队在印度（钦奈和班加罗尔）的电子邮件 ID？" 您可以咨询 TSR，了解这些地点是否提供恩智浦技术支持。 在线问答 https://www.nxp.com/support/support:SUPPORTHOME?tid=sbmenu

s32k312 hse ab-swap 重启方法？ 恩智浦专家，你好、 1.我使用的是 s32k312，HSE 版本为 1.13.0、2.40.0。 2.我正在实现 OTA 功能。 OTA 完成后，我需要致电 HSE 交换 ab，然后重启以运行新的应用程序。 我的问题是，我编写了一个演示程序，并调用" HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK" 服务。在不带任何参数的情况下，使用"IP_MC_ME" perphieral 重启单片机，但只起一次作用，然后单片机就无法运行了，可能是出现了一些硬故障。 那么，但是通过RESET引脚重启是可以的。 我的重启密码是 剧透 （高亮部分可供阅读） IP_MC_ME->MODE_CONF = mc_me_mode_conf_func_rst(1); IP_MC_ME->MODE_UPD = MC_ME_MODE_UPD_MODE_UPD(1); IP_MC_ME->CTL_KEY = mc_me_ctl_key_key(0x5AF0); IP_MC_ME->CTL_KEY = mc_me_ctl_key_key(0xA50F); IP_MC_ME->MODE_CONF = MC_ME_MODE_CONF_FUNC_RST(1); IP_MC_ME->MODE_UPD = MC_ME_MODE_UPD_MODE_UPD(1); IP_MC_ME->CTL_KEY = MC_ME_CTL_KEY_KEY(0x5AF0); IP_MC_ME->CTL_KEY = MC_ME_CTL_KEY_KEY(0xA50F)； 这个重启代码可以吗？还是我需要使用其他方法重启微控制器，使 ab 交换功能生效并运行新程序？ 谢谢。 Re: s32k312 hse ab-swap reboot method? 原则上是正确的，但请务必查看以下演示示例，您可以在其中详细调换程序 首先，我们提供了 Secure 启动 应用笔记，其中包括详细解释所有步骤的演示项目。可从以下网址下载 https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k3-microcontrollers-for-automotive-general-purpose:S32K3 应用笔记可以在这里找到： 文档-> 安全文件-> 安全启动应用笔记 v0.1.1.0(AN744511) 相关演示项目可在此处下载： 设计资源 -> 软件 -> 安全文件 -> SecureBootAppNoteDemo (SW745310)

复制： 关于 EB32.0.0 Im/Exporter 的问题 本帖复制自 此处 嗨，团队、 我的客户舍弗勒希望导出 arxml 文件。我在 EB32.0.0 上试过，该工具会报告一些奇怪的错误。 同样的程序也适用于 EB 29 和 K3 RTD。 您能帮忙检查一下这个问题吗？ 此致， Liek EB TRESOS 许可证 优先级：中等 来源：恩智浦内部来源：恩智浦内部 Re: Copy: Issue about EB32.0.0 Im/Exporter 你好@Luis_Garabo 首先，请参阅 RTD 发行说明，以验证哪个 EB Tresos 版本已通过相应的 RTD 版本进行了验证。 必须使用发行说明中指定的经过验证的 EB Tresos 版本，以确保功能正确和运行稳定。

i.MX93 A55 の Zephyr こんにちは、 i.MX93 Cortex-A55 で Zephyr を実行するための例が提供されており、hello_world をビルドし、u-boot プロンプト経由で DDR で実行できます。 u-bootの使用は避けたいです。ATF コードを参照しましたが、bl31 のビルドのみがサポートされています。「BootROM -> ATF BL2 -> ATF BL31 -> Zephyr」を実現したいのですが、BL2 をビルドするためのリファレンスはありますか? また、hello_world の例を OCRAM で実行したいのですが、手順を教えていただけますか。また、ここでもブートローダーが必要ですか。それとも JTAG 経由でバイナリを OCRAM に直接ロードできますか。 ありがとうございます Re: Zephyr on i.MX93 A55 こんにちは、 DDR 上で、BootROM --> BL2 --> BL3 --> Zephyr の順で Zephyr を起動できます。 内部 RAM で zephyr を実行したいです。ここに何か参考になるものはありますか? ありがとうございます

IMX8mp HDMI EDDC I2C configuration We are bringing up a new imx8mp board that we have designed. All is functional except the HDMI interface. It almost works with some monitors. Basically the issue is that the system can't read the DDC data across the HDMI's I2C bus. The design we have is identical to one we have used on another imx8mp board, but we are using the latest NXP 6.1.55_2.2.0 Yocto Linux system. Looking at the HDMI I2C signals to the monitor it looks like the SCL to SDA timings are a bit off. SDA is changing very close to the SCL -ve transition and we wonder if this could be the cause. This I2C bus appears to be driven by a special I2C EDID E-DDC interface in the imx8mp. I can't see any particular settings for this in the DTS. 1. Where is the configuration for this I2C type of device ? 2. Has anyone seen this issue before ? 3. Any ideas ? Re: IMX8mp HDMI EDDC I2C configuration I'm facing the same problem, but the pinout on my HDMI is correct. I was able to read EDID information from one display, but when I connect a different model, the I2C communication stops right after the first 8 clocks, since no acknowledge is send back from the display. Trying to read out the EDID information with an external Microcontroller over the same HDMI cable works fine. Were you able to fix the issue with the tight SDA hold timing? Could you please share the solution. BR Gabriel Re: IMX8mp HDMI EDDC I2C configuration I have found the issue. We are using a micro HDMI connector on this board. We used a Wurth 685119248123 part and went with the pinout defined on that datasheet. This was wrong. They have updated the datasheet to a 0002.000 version. However the DDC I2C timings do look a little tight to me. I tried increasing the value in the EDDC I2C DDC SDA Hold Register and timings look better to me. Sorry for the noise. Re: IMX8mp HDMI EDDC I2C configuration This is what the HDMI I2C lines when trying to read I2C device 0x50 address 0. There is no ack from the monitor.

AUTOSARドライバに基づくS32K358 HSE乱数生成 親愛なるサポート、 お客様AptivはS32K358で作業しています RTDバージョン: Crypto_43_HSE_TS_T40D34M60I0R0 HSE FW バージョン: HSE_FW_S32K358_9_2_72_0 Crypto RTDを統合し、MCUにHSEファームウェアをフラッシュした後、乱数を生成しようとしたところ、ファームウェアがHse_Ip_ServiceRequest()関数、具体的にはMu_Ip_IsResponseReady()を待機している間にスタックする問題が発生しています。参考までに、コールスタックのスクリーンショットを添付いたしますのでご確認ください。 以下の点についてご理解いただけますでしょうか。 この時点でファームウェアが停止してしまう理由は何でしょうか? この問題を解決するための推奨される解決策またはデバッグ手順はありますか? PS: BSWM構成でCSM_Init、CriIf_Init、Crypto_Initを構成しました CSM、CryIf は Vector Davinci で構成され、CSM、CryIF、Crypto の Init 関数は BSWM_Init コールアウトから呼び出されます。HSE はデモ APP を使用してインストールされ、以下に示すようにバージョン番号と MU ステータス レジスタを読み取ることによって検証されました。 お客様は、AUTOSAR xdm 構成 CSM、CriIf、および Crypto ドライバ (DEMOAPP のコードではない) に基づく実用的な AUTOSAR の例を求めています。Crypto xdm ファイルを添付しました。 (これまでのところ、NXP 側では Sunny X と Dhan Raj がデバッグ呼び出しに参加していなかったため、最終的なルート コースはまだ見つかっていません...) よろしくお願いいたします。 ヴィクトル ボード: S32K358 優先度: 重要 SWバリアント: 標準 Re: S32K358 HSE Random Number Generation based on AUTOSAR drivers こんにちは、クオンさん 助けていただきました。[email protected]例を作成しました。 お客様が試してみる来週までこのチケットをオープンのままにしておきましょう。 Sharepoint 上の例へのアクセスを許可します。 よろしくお願いいたします。 ヴィクトル   Re: S32K358 HSE Random Number Generation based on AUTOSAR drivers こんにちは@viktorfellinger 例を作ってみます。 その間、CANでお知らせいただけますか: 1.この問題はどのくらいの頻度で発生しますか?それは常に起こるのか、それとも散発的に起こるのか 2. Hse_Ip_ServiceRequest()呼び出し時のpRequestとpHseSrvDesc の値 この問題を解決できるかどうかを確認するために、pRequestのタイムアウト値を増やしてみて、問題がCANを通過するかどうかを確認してみませんか? Re: S32K358 HSE Random Number Generation based on AUTOSAR drivers こんにちは@viktorfellinger 何かフィードバックはありますか? 更新がない場合は、このトピックを閉じたいと思います。 お客様が後で別の質問をした場合、このトピックに再度言及することができます。

imx6ull ESAI SDKsの例はどこにありますか こんにちは、専門家の皆さん。 現在、imx6ullプラットフォームに取り組んでおり、ESAIを実装したいのですが、それに関するドキュメントはほとんどなく、「SDK_2.2_MCIM6ULL」にはドライバコードがありません。 CAN、誰かヒントをくれませんか?ありがとう Re: Where is imx6ull ESAI SDK example いくつかの例もいただければ幸いです。さまざまなデバイスツリーのesaiノードを見つけました。（例えばimx6ull.dtsi (linux-imx フォーク) を使用しましたが、うまく動作しません。fsl-esai-dai 2024000.esai: failed to init imx pcm dma: -517で失敗します。これは、DMA チャネルの登録に苦労しているため、ドライバの読み込みを延期することを意味します。esai ノードのデバイス ツリーに関するドキュメントや例はありません。 Re: Where is imx6ull ESAI SDK example 迅速なご返答ありがとうございます。SDKs を概観したところ、sai に関する例はいくつかありましたが、esai を参照する例はありませんでした。必要なのは、ベアメタルで esai 機能を有効にすることです。 私は何日もこの問題に取り組んできました。助けていただけると大変助かります。 @チャビラ Re: Where is imx6ull ESAI SDK example こんにちは@ryan_chen ！ NXP サポートにお問い合わせいただきありがとうございます。 この SDK のすべての例とドキュメントは、次のリンクからダウンロードできます。 https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-6-processors/i-mx-6ull-single-core-processor-with-arm-cortex-a7-core:i.MX6ULL それが存在しない場合は、探している例は利用できません。 間違いごめんなさい！ よろしくお願いします！ チャビラ

SR150 UWBIoT TWR 测距 - phRangingMesr.rssi 始终为 0。DS-TWR 是否支持 RSSI 或需要 CCC/RSSI？ 你好 我正在使用恩智浦SR150 UWBIoT MCUx SDK（v04.08.01），并将demo_ranging_controller+demo_ranging_controlee应用程序用于 DS-TWR 测距。 测距距离和信噪比打印正确，但RSSI 始终报告为 0，无论测距距离或天线状况如何。 输出示例（取自 PrintUtility.c→ printRangingData())： TWR[0].distance = 135 cm TWR[0].rssi= 0 使用的代码： pRangingData->ranging_meas.range_meas_twr[i].rssi 我在文档中找不到必须通过宏或配置启用TWRRSSI（RANGE_DATA_NTF）的任何地方。 供应商 SNR 字段正常工作，但phRangingMesr_t 中的 rssi 成员从未填充。 我的问题 SR150 在正常 TWR 测距会话 (RANGE_DATA_NTF) 中是否支持 RSSI？ （任何参数，如 NXP_EXTENDED_NTF_CONFIG、PHY 配置、会话类型等） 。 如果不是，那么RSSI 仅在以下情况下可用是否正确？ CCC_RANGE_DATA_NTF（CCC/CSA 我的）— Q8.8 RSSI_RX1/RSSI_RX2 TEST_RX_NTF / TEST_PER_RX_NTF（射频测试模式） - Q8.8 RSSI 值 是否有推荐的方法在同一个数据包上同时获取距离和真实校准 RSSI？ 任何官方确认或文件指针都将非常有用。 现在，信噪比打印正常，但在所有测距测试中，RSSI 仍为 0。 谢谢！ Re: SR150 UWBIoT TWR ranging – phRangingMesr.rssi always 0. Is RSSI supported in DS-TWR or requires 你好 希望你一切顺利。很抱歉给您带来不便，但由于该产品的信息受 NDA（保密协议）保护，因此不对外公开。 如需了解有关该芯片的更多信息，请联系在代理商网络中提供的代理商之一？或者，如果您有任何直接联系人帮助您获得此设备，请与他们联系。 如果您正在寻找有关我们 UWB 产品的信息，或者您对该技术感兴趣，我建议您查看我们合作伙伴（Trimension UWB 合作伙伴）提供的开发套件和模块。 如果您对这些套件/模块感兴趣，您需要直接与他们联系，了解他们可以提供的流程和支持，因为这项技术的支持途径就是通过他们。 文档和软件由相应的 UWB 模块合作伙伴分发。选择模块后，您将被引导到我们合作伙伴的页面，在那里您可以访问数据表、应用笔记和所需的支持 此致， 里卡多

LWIP - S32G 中的 TCP/IP 协议栈 你好， 我目前想在 S32G-VNP-RDB2 板 SJA1110 交换机中配置 IPv6 这个 TCP/IP 堆栈包含 在 TCP/IP 堆栈中目前我使用的是 2.1.2版本 Netiface -- ENABLE IPv6 IP 网络 -- 为 IPv6 添加了基本配置 我正在尝试创建一个链接本地地址，我应该能够在任何需要的地方使用这个 IPv6 地址。下面是需要与此代码连接的代码，这样我就可以从交换机 1 的任何端口 ping IP 地址。 ip6_addr_t ipaddr_v6; s8_t chosen_idx; IP6_ADDR(&ipaddr_v6, PP_HTONL(0xFE800000), PP_HTONL(0x0), PP_HTONL(0x3DD79303), PP_HTONL(0x126c0df0)); netif_add_ip6_address(&netif, &ipaddr_v6, &chosen_idx); netif.ip6_addr_state[chosen_idx] = IP6_ADDR_VALID; 那么需要在哪里进行集成 在 TCP/IP 协议栈中还需要做哪些更改 阿特金森 敬上 Re: LWIP - TCP/IP stack in S32G 您好@chenyin_h 事实上，您所附的 TCP/IP 协议栈图像显示的是 2.0.0，但目前我使用的是 1.4.0。 显示为"S32G TCPIP STACK 1.0.4 D2310 示例项目". 因此，我想我需要将 TCP/IP 协议栈 2.0.0 ，请为我导航，我在哪里可以找到您在片段 中共享的 TCP/IP 文件？ Atkinson Re: LWIP - TCP/IP stack in S32G 你好，@阿特金森 感谢您的回复。 1.由于软件管理器页面上没有该软件，也许它尚未公开，我建议首先使用 1.0.4 版。版本。 2.1.0.4 是 S32G TCP/IP 协议栈的内部版本，而不是 lwIP 的版本，使用的 lwIP 是 2.1.3、可以满足您的要求 BR 切宁 Re: LWIP - TCP/IP stack in S32G 嗨 @chenyin_h 谢谢你的回复！！ 目前我能看到我的 TCP/IP 堆栈版本是 1.4.0 你显示的 TCP/IP 堆栈的图片是 2.0.0 版 汽车软件包管理器 | 恩智浦半导体 我在这里查看了 S32G2 平台的最大容量为 1.4.0 对于 IPv6 它至少需要 2.0.0 或更高版本。那么我在哪里可以找到软件包？ 在内置 IPv6 之后你能详细说明一下吗。 在这种情况下，我们如何检查分配给该端口的 MAC 地址，更改 MAC 地址并深入配置？ Atkinson Re: LWIP - TCP/IP stack in S32G 你好，@阿特金森 感谢您的回复。 1.好吧，我建议使用基于 GMAC 的 lwIP 演示，PFE 演示已经过时了，而且依赖关系也不好找。 可从以下页面找到 RDB2 的 lwIP 演示（GMAC）。 要获得它，您可能需要将恩智浦账户中恩智浦配置的 S32G TCPIP 堆栈和 FreeRTOS 软件包安装到您的 S32DS 中，安装后，请按： 然后，您就可以找到我提到的演示。 2.默认设置为 IPv4 地址，当前演示可能不直接支持 IPv6。但我认为 IPv6 可能是支持的，因为它只与堆栈本身有关，您可能需要在 lwIP 中启用它，并测试是否存在问题。 BR 切宁 Re: LWIP - TCP/IP stack in S32G 你好@chenyin_h 1.)GMAC 端口有一个 lwIP 演示。PFE 端口也有一个旧的演示。 您能分享这两个实现吗？LWIP 堆栈在这里扮演什么角色？ 2.)从描述来看。看来你想使用 SJA1110 端口通过 LwIP 与其他网络设备通信？ 实际上，我想介绍包括 IPv6 在内的 lwip 堆栈的基本功能，所以我想在任一 SJA1110/S32G 中测试其可行性。 因此，基本上我想使用 IPv6 来传输 ping 信息或数据。 Atkinson Re: LWIP - TCP/IP stack in S32G 你好，@阿特金森 谢谢您的帖子。 从 S32G 正式软件的角度来看，GMAC 端口有一个 lwIP 演示。PFE 端口也有一个旧的演示版，但不能用于最新版本的软件组合。对于 RDB2 的 SJA1110 端口，没有直接的示例/演示。 从描述来看看来你想使用 SJA1110 端口通过 LwIP 与其他网络设备通信？ BR 切宁 Re: LWIP - TCP/IP stack in S32G 你好，@阿特金森 感谢您的回复。 您可以在恩智浦账户中查看是否可用，如果仍然不可用，可能是您的恩智浦账户尚未公开。 如前所述，1.0.4/2.0.0 是" S32GTCPIP STACK" 的版本号，而该协议栈基本上基于 lwIP2.1.3或更新的版本，因此我认为使用 1.0.4您提到的" S32GTCPIP STACK" 版本仍然符合您的要求。 BR 切宁 Re: LWIP - TCP/IP stack in S32G @Atkinson你能否更新一下你是否能在 s32g 上用 lwip 运行 tcpip，以及如何运行的？ 🙂

i.MX 数据表中 NVCC 的含义 你好 我正在查看 i.MX 数据表，经常看到以 NVCC_* 开头的引脚名称。 能否请您解释一下 NVCC 代表什么？ 此外，名称中包含 NVCC 的徽章有何意义？ 感谢您的支持。 顺祝商祺！ Re: Meaning of NVCC in i.MX Datasheet 您指的是哪种产品？ NVCC 是"Nominal Voltage Common Collector" 的缩写，NVCC_* 引脚是为一组 I/O 焊盘（如 GPIO、UART、SPI 等）提供电压的电源引脚。 如 NVCC_SD 为 SD 卡接口引脚供电。 Re: Meaning of NVCC in i.MX Datasheet 你好，丽塔、 谢谢您的解释。我所指的产品是 i.MX93。 我知道 NVCC 代表标称电压共集电极，而 NVCC_* 引脚是为特定 I/O 组（如 GPIO、UART、SPI）提供电压的电源引脚。NVCC_SD 为 SD 卡接口供电的例子非常有用。 感谢您的支持。 致以最诚挚的问候， tkato Re: Meaning of NVCC in i.MX Datasheet 你好@tkato， 不客气。 如有任何疑问，您可以创建新的主题，与我们自由联系。 祝您有美好的一天 顺祝商祺！ Rita