Unable to boot LX2160A processor out of PBI and DDR reset is low always Hi, We are using LX2160A in our custom board. Processor is not booting (DDR reset is low) Our configuration is: DDR4 x32bit @2600MTPS on both controllers. Flex SPI is the RCW SRC. HRESET is going high and ASLEEP is low. When we try to read the registers as per LX2160ARM we are getting below value 0x01E001FC (DCFG_SCRATCHRW3): looks like no error code +0 +4 +8 +C [0x01E001E4] 00000000 00000000 00000000 00000000 [0x01E001F4] 00000000 00000000 00000000 00000000 [0x01E00204] 00000000 00000000 00000000 00000000 [0x01E00214] 00000000 00000000 00000000 00000000 [0x01E00224] 00000000 00000000 00000000 00000000 0x01E6_0104 (RCW_COMPLETIONR): Service Processor has completed the RCW loading 0x01E6_0114 (PBI_COMPLETION): Service Processor has complete the PBI phase, also Service Processor Core is in Boot Holdoff and not released for Booting +0 +4 +8 +C [0x01E600F0] 00000000 00000000 00000000 00000000 [0x01E60100] 00000000 00000001 00000000 00000000 [0x01E60110] 00000000 00000001 00000000 00000000 [0x01E60120] 00000000 00000000 00000000 00000000 We are unable to boot DDR or validate DDR using DDRv tool in QCVS or get any UART prints What may be the possible cause of this issue? Do we need to modify any other registers other than RCW for processor to boot? Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always Would you please create a new thread to continue to discuss DDR bringing up issue? This thread was updated too long. DDR bringing up is  another topic and complex. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always 2. Can you try booting the board with disabling serdes and removing PBI commands? >>> I tried disabling serdes and removing PBI commands as suggested, I'm able to get UART prints, HRESET is high and ASLEEP is also low. UART log is attached below. But DDR initialization is failing. I checked MRST pin from processor it is low. It is not going high anytime. Do I need to add any other configuration for DDR initialization? What are the configurations required for DDR initialization? I'm using both controllers, 4GB DDR4 with 32bit width without ECC on each controller. All connections are one-to-one, no bit or byte swapping in DDR controllers. I have shared the schematic during initial conversation in this post itself. Attaching the RCW used to get the UART prints. Also, I tried the pbl file shared by you in previous post, HRESET is low when I try to boot. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always I generated ATF image bl2_flexspi_nor.pbl with your original PBL image, please try whether you can get output information from UART1(NOR UART0). Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always Can you confirm if RCW I shared for serdes disabled and PBI commands removed is valid? Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always Investigating. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always With new build commands, result is still looks same. I'm trying multiple rcw combinations with the new commands. I will share the results of the same. 1. UART logs says transmission is successful. You are able to see the print on console? or any toggling on oscilloscope? You are able to do this when booting from nor? >>> I couldn't get which UART logs you are saying, I'm assuming CCS logs I shared last week using UART commands. I was able to get it working by flashing "PBL_binary.bin" file generated using QCVS tool using the originally shared rcw configuration. I'm not getting any UART prints or observe any toggling in oscilloscope at that time. I was able to observe toggling after manually modifying registers 0x21c0024, 0x21c0028, 0x21c002c registers to 0x5e, 0x3c, 0x70 respectively in ccs. 2. Can you try booting the board with disabling Serdes and removing PBI commands? >>> I'm using the attached rcw file for disabling Serdes and removing PBI commands. I hope I'm doing it right. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always Please rebuild RCW with command $ flex-builder -c rcw -m lx2160ardb_rev2 2. $ flex-builder -c rcw -m lx2160ardb_rev2 Please modify RCW file components/firmware/rcw/lx2160ardb_rev2/XGGFF_PP_HHHH_RR_19_5_2/rcw_2200_750_3200_19_5_2.rcw according to your target board. $ flex-builder -c rcw -m lx2160ardb_rev2 I am analyzing the RCW and PBL. Meanwhile, I would like to confirm the following: 1. UART logs says transmission is successful. You are able to see the print on console? or any toggling on oscilloscope? You are able to do this when booting from nor? 2. Can you try booting the board with disabling serdes and removing PBI commands? Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always I tried the original RCW in LSDK 21.08 build environment as suggested by you. The result is still the same. HRESET is going high but ASLEEP is staying high. Original RCW was developed in QCVS tool, it generates PBL_binary.bin, when I flash that image then HRESET is going high and ASLEEP is going low. Same parameters I'm defining in LSDK environment, and it is not working. I also tried 2 more other rcw settings that work with bin file generated using QCVS but not using LSDK 21.08 environment. I have mentioned some error while building rcw image using "flex-builder rcw -m lx2160ardb_rev2", it is asking for GitHub credentials, and it is failing when I enter username and password. Will that cause any issues? What are the things processor checks before it drives ASLEEP zero? Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always No need additional settings for USB while building the image. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always Okay, I will try the same RCW in lsdk. We are not using USB in our design and USB related powers are not given. These pins are tied to ground. This is being done as per the recommendation in "AN5407_Design checklist" document. Also, I recently found "AN12114 - Implementation of IEEE 1149.6 on LX2160A_Rev.C" document which needs to be implemented. I'm not able to understand this document properly. Can you confirm do I have to add any additional setting or configuration related to USB while building the images? What does "AN12114 document" is about exactly? Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always No need to define PBI length value, it will be generated automatically while building. DDR controller configuration is configured in ATF source code, you need to decide these parameters with QCVS DDRv tool. First, please check whether there is console output from ATF BL2 running in OCRAM. Then consider DDR configuration issues. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always But it is used as a debugging experiment. it uses 600MTps of ddr frequency and all other clocks are as low as possible. I will try using the same rcw in lsdk. Should I have to define PBI length value in rcw? or it will be defined by lsdk while building? I see some PBI commands added while building the rcw files. Also, where I have to configure DDR configurations like timing parameters for DDR controller? Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always In your original description, it seems that using your original RCW, the processor is out of reset successfully. Would you please use your original RCW values in LSDK 21.08 build environment? Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always Discussing with the AE team. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always Hi @yipingwang I have tried generating the pbl and uboot file as per the procedure suggested by you and flashing in location 0x00000000 and 0x00100000 both files. now processor is releasing HRESET (going High) but ASLEEP is staying high. So, for safer side I disabled the serdes completely in rcw file and the result is same. attached both rcw and flash images generated as per your recommendation (lsdk provided by you and Ubuntu 20.04.6 in VM). Is there anything I'm missing in rcw configuration? There was an error as explained earlier while building rcw file. It was asking for username and password for some github repositories, log of the same is also attached. Also, I tried UART commands given by you. Directly it was not working even after I set the UARTEN (0x21c0030). I had to modify 0x21c0024, 0x21c0028, 0x21c002c registers to 0x5e, 0x3c, 0x70 respectively. above 3 registers were 0x00000000 before modification. Log of the same is also attached. This is same with both UART0 and UART1. Please guide how to proceed further and what may be the issue? Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always While building rcw it is asking for username and password for github.com I have provided something, and authentication failed but the image is getting generated. Can I use this file in my board? or do I have to provide proper details when it asks for username and password, and if I have to provide then what should I provide exactly? Below is the log for the same: repo: xserver tag: xorg-server-1.20.9 Cloning into '/home/sbc/Downloads/flexbuild_lsdk2108_github/components/apps/graphics/xserver'... Username for 'https://github.com': sbc Password for 'https://[email protected]': remote: Support for password authentication was removed on August 13, 2021. remote: Please see https://docs.github.com/get-started/getting-started-with-git/about-remote-repositories#cloning-with-https-urls for information on currently recommended modes of authentication. fatal: Authentication failed for 'https://github.com/freedesktop/xorg-xserver.git/' repo: gpulib tag: LSDK-21.08 repo: wayland tag: 1.18.0 Cloning into '/home/sbc/Downloads/flexbuild_lsdk2108_github/components/apps/graphics/wayland'... Username for 'https://github.com': sbc Password for 'https://[email protected]': remote: Support for password authentication was removed on August 13, 2021. remote: Please see https://docs.github.com/get-started/getting-started-with-git/about-remote-repositories#cloning-with-https-urls for information on currently recommended modes of authentication. fatal: Authentication failed for 'https://github.com/wayland-project/wayland.git/' make: *** [/home/sbc/Downloads/flexbuild_lsdk2108_github/include/app_repo_update.inc:28: graphics_repo_fetch] Error 128 make: Leaving directory '/home/sbc/Downloads/flexbuild_lsdk2108_github/packages/apps' make: Entering directory '/home/sbc/Downloads/flexbuild_lsdk2108_github/packages/apps/graphics' make: *** No rule to make target 'graphics_repo_fetch'. Stop. make: Leaving directory '/home/sbc/Downloads/flexbuild_lsdk2108_github/packages/apps/graphics' Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always The default rcw file (rcw_2200_750_3200_19_5_2.rcw) has only little few parameters defined. All 1024 bits are not defined. I'm just modifying the fields that are required specifically for our board. Is this okay? or I have to define all the rcw fields as per the reference manual document (lx2160arm): 4.9.8.9 Reset Control Word (RCW) Register Descriptions. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always You could install VM on your Windows PC, then install Ubuntu 20.04 on it, then install LSDK 21.08. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always Is it possible to run LSDK in windows PC using WSL or VM, if yes please provide procedure to install it in windows PC. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always For using LSDK, please make sure that you have modify RCW file with the following step correctly. Please configuring the target board as booting from flexspi NOR flash, please don't configure it as hard-coded RCW. 2. $ flex-builder -c rcw -m lx2160ardb_rev2 Please modify RCW file components/firmware/rcw/lx2160ardb_rev2/XGGFF_PP_HHHH_RR_19_5_2/rcw_2200_750_3200_19_5_2.rcw according to your target board. $ flex-builder rcw -m lx2160ardb_rev2 Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always I tried the lsdk commands and flashed the image, still there is not prints on UART. we have some issues with the Ubuntu PC. Is there any other method we can try this on windows?  running windows subsystem for Linux or through virtual machine? Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always I tried running these commands but I got all zeros when I read the registers. looks like it is unable to read. Also, when I try to configure a chain using ccs::config_chain {lx2160a dap} command then I'm getting error: Core not responding. There is some other issue also. when we keep the RCW_SRC in NOR flash mode processor is releasing HRESET. but when we change it to Hard coded mode then HRESET is always low. Unable to get why this is happening. this issue started a week ago when we flashed an image which had some wrong configuration of RCW in it. What may be causing this issue? Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always Is it possible to run this tool on a windows PC? There is some issue with the Ubuntu we were using. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always RCW seems fine, pin mux setting for UART is correct. SoC is out of reset. Chain on CCS is fine too. 0x01E60114 (PBI_COMPLETION) -- there was no error code reported For further debugging the issue, we will first check whether UART is working or not and then will move to DDR. For checking UART, please run the following commands on CCS display ::ccs::read_mem 86 0x21c0000 4 0 0x10 //UART1 registers display ::ccs::write_mem 86 0x21c0000 4 0 0x65 display ::ccs::write_mem 86 0x21c0000 4 0 0x66 Before transmitting please set UARTCR[UARTEN] (0x21c0030) Hope this help. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always 1. Please install the attached LSDK 21.08 to an Ubuntu 20.04 PC. Set up the build environment. $ cd flexbuild_lsdk2108_github $ source setup.env 2. $ flex-builder -c rcw -m lx2160ardb_rev2 Please modify RCW file components/firmware/rcw/lx2160ardb_rev2/XGGFF_PP_HHHH_RR_19_5_2/rcw_2200_750_3200_19_5_2.rcw according to your target board. $ flex-builder rcw -m lx2160ardb_rev2 3. $ flex-builder -c atf -m lx2160ardb_rev2 -b xspi Go to ATF source code folder flexbuild_lsdk2108_github/components/firmware/atf, please modify plat/nxp/soc-lx2160a/lx2160ardb/plat_def.h as the following, if you are using UART1 rather than UART0. #define NXP_CONSOLE_ADDR NXP_UART_ADDR Modify to: #define NXP_CONSOLE_ADDR NXP_UART1_ADDR Rebuild atf image: $ flex-builder -c atf -m lx2160ardb_rev2 -b xspi 4. You will get image bl2_flexspi_nor.pbl and fip_uboot.bin in folder flexbuild_lsdk2108_github/build/firmware/atf/lx2160ardb_rev2/. Please deploy bl2_flexspi_nor.pbl at 0x00000000 and fip_uboot.bin at  0x00100000 on the flexspi NOR flash. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always Investigating with your information. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always Please ask them to share 1. Reset register dump (0x1e6_0000 to 0x1e6_0bfc) >>> File attached. File name: register_dump_1e6_log.txt 2. RCW and PBI file. >>> File attached. File name: PBL_binary.bin I'm not adding any PBI commands as I'm using NOR flash to boot. 3. Schematic >>> File attached. File name: LX2160A_SCH   Please ask customer the following: 1. Using CCS, please ask them to configure config chain delete all config cc cwtap //for USB (if IP address is present config cc cwtap: ) show cc ccs::config_chain {lx2160a dap} display ccs::get_config_chain Based on this we can understand if processor is out of reset or not. >>> File attached. File name: ccs_command_log   2. Are they not able to get any UART prints? Even before DDR prints some info related to BL2 is printed. >>> No. Unable to get any prints from UART 1. Probed UART 0 signals, there was no activity observed on scope also.   3. Please check whether ddr_phy_firmware is present in the firmware image that they are programming. Check 0x800000 offset of Flash. >>> I'm not flashing any firmware. I'm not able to get the ddr_phy_firmware file. From where I will get the file required.   Clarification: 1. I'm using discrete DDR IC soldered on board, not DIMM modules. 2. I'm using NOR flash as RCW source and for boot.   I have some doubts: 1. I have tried changing RCW configuration, also tried running DDRv tool in QCVS. There was no improvement. 2. In beginning I have mentioned there was an error code as per register 0x01E60114 (PBI_COMPLETION), what does that mean? does it mean PBI image is not proper or image missing? 3. What may be the cause for no activity in UART signals. 4. How will I get the ATF BL2 and BL31 images from? 5. Which all configurations i need to make in order to get the processor to initialize DDR properly. 6. Is it possible to get image with minimal interfaces, just for checking DDR only so that I can use it to flash on the board and check or use it as my reference. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always Please ask them to share 1. Reset register dump (0x1e6_0000 to 0x1e6_0bfc) 2. RCW and PBI file. 3. Schematic Please ask customer the following: 1. Using CCS, please ask them to configure config chain delete all config cc cwtap //for USB (if IP address is present config cc cwtap: ) show cc ccs::config_chain {lx2160a dap} display ccs::get_config_chain Based on this we can understand if processor is out of reset or not. 2. Are they not able to get any UART prints? Even before DDR prints some info related to BL2 is printed. 3. Please check whether ddr_phy_firmware is present in the firmware image that they are programming. Check 0x800000 offset of Flash. On first instance, I would like to check UART and then DDR. Because if DDR initialization has failed then some prints related to DDR initialization would have come. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always Discussing with the AE team. Re: Unable to boot LX2160A processor out of PBI and DDR reset is low always I'd like to ask you a question about this one, it says 2.2G, but I'm not sure if it's a good one. * Frequencies: * Core -- 2200 MHz * Platform -- 750 MHz * DDR -- 3200 MT/s CGA_PLL1_CFG=0 CGA_PLL1_RAT=22 CGA_PLL2_CFG=0 CGA_PLL2_RAT=22 CGB_PLL1_CFG=0 CGB_PLL1_RAT=22 CGB_PLL2_CFG=0 CGB_PLL2_RAT=22 But the following selects a 4-split frequency, and in fact this 8 cores is not 550MHz? What exactly is this mains frequency after crossover? C1_PLL_SEL=2 C2_PLL_SEL=2 C3_PLL_SEL=2 C4_PLL_SEL=2 C5_PLL_SEL=2 C6_PLL_SEL=2 C7_PLL_SEL=2 C8_PLL_SEL=2 @yipingwang

Flashdownload with Linkserver: connect to target under reset required Hello,   we are using the MCU-Link debug adapter and a Kinetis K22 microcontroller. For automation purposes we want to use Linkserver to download an image into the flash. If the target controller is empty this works without a problem.  But now we have an application, where we reassign the SWD debug pins after the application starts running. Once the application has started the debug pins are used for a different purpose and it is not possible to connect to the controller via SWD. This means that it is necessary to hold the hardware reset line while connecting to the target. This exact process is working under Keil uvision IDE with the MCU-Link selected as a CMSIS-DAP debugger. There the setting is called "connect under reset", with "HW reset" selected. Now we want to be able to do the same with the Linkserver tool.  But I cannot find this option for the flash command. I have already experimented with a script to first issue a reset with "wiretimedreset" and then start linkserver, but this is not fast enough. The application is already running when the MCU-Link tries to connect. I also tried to make a script that holds the reset line with "wireholdreset" but it seems like the linkserver is removing the reset early on and then it cannot connect. I also know about the connect scripts, but the failure actually happens before this script is called:   linkserver output: INFO: Selected device MK22FN512xxx12:TWR-K22F120M INFO: Getting available probes INFO: Selecting probe by index INFO: Selected probe #1 12Z1C04R3SI0T (MCU-LINK (r0FF) CMSIS-DAP V2.263) INFO: MCU-Link firmware update `check`: not supported on probe ([12Z1C04R3SI0T] [MCU-LINK (r0FF) CMSIS-DAP V2.263]). Only probes running firmware V3.122 or later can be updated automatically Firmware update `check`: not supported - the update cannot be performed Ns: LinkServer RedlinkMulti Driver v25.3 (Mar 25 2025 18:34:18 - crt_emu_cm_redlink.exe build 945) Pc: ( 0) Reading remote configuration Wc(03). No cache support. Nc: Found generic directory XML file in Pc: ( 5) Remote configuration complete Nc: Reconnected to existing LinkServer process. Nc: Connecting to probe 1 core 0 (using server started externally) reports: 'Ee(42). Could not connect to core.' Nc: Retrying... Nc: Reconnected to existing LinkServer process. Nc: Server OK but no connection to probe 1 core 0 (after 3 attempts) - Ee(42). Could not connect to core. Wc: ============= SCRIPT: kinetisconnect.scp ============= Wc: Kinetis Connect Script Wc: Connecting to Probe Index = 1 Wc: Error: Probe not connected Wc: Error: Wire Ack Fault - target connected? Wc: Assert NRESET Wc: Reset pin state: 00 Wc: Error: Wire not connected Wc: Power up Debug Wc: Error: Wire not connected Wc: Error: Wire not connected Wc: No Debug Power Wc: ============= END SCRIPT =============================   So what we need is an option for linkserver to hold the reset line until it takes control of the microcontroller and writes the flash algorithm. I think this option would also be very helpful in other cases, where the microcontroller is in an unpredictable state. So is there a way to do this with linkserver?   Thank you for any help. Re: Flashdownload with Linkserver: connect to target under reset required Hi @m_p  Thank you very much, I am glad  that you  shared the solution you have found, it may help other users too ! My apologies, yes, it makes more sense to use preconnect script as it prepares the MCU for initial debug.  Diego Re: Flashdownload with Linkserver: connect to target under reset required Hello Diego, thank you for your comment. I have found a solution, but it is not in the reset scripts.  As far as I understand the reset scripts are called after the flash download is finished. But this is not what I needed. Just to state the problem again. what I need is that the reset line is activated before the debug connection is established. I want to use the Linkserver as a standalone tool to program boards. So I am running it from a batch file in a command line window. But your post made me look at the preconnect scripts. In the command line you can call the linkserver.exe with a .json configuration file. This configuration file determines which scripts are called. In all the examples I have looked at there was no preconnect script. The schema file "LinkServer_XXXX\devices\devices.schema.json" shows how to add the script into the configuration file. However the documentation on this is not very clear. For reference here is the modified configuration file: { "copyright": "Copyright 2023 NXP", "license": "SPDX-License-Identifier: BSD-3-Clause", "version": "1.0.0", "vendor": "NXP", "devices": [ { "board": "TWR-K22F120M", "device": { "name": "MK22FN512xxx12", "family": "K2x", "memory": [ { "location": "0x00000000", "size": "0x00080000", "type": "Flash", "flash-driver": "FTFA_2K.cfx" }, { "location": "0x20000000", "size": "0x00010000", "type": "RAM" }, { "location": "0x1fff0000", "size": "0x00010000", "type": "RAM" } ], "cores": [ { "type": "cm4", "name": "cm4" } ] }, "debug": { "protocol": "swd", "swo": true, "preconnect-script": "preconnect_HOLD_RESET.scp", "connect-script": "kinetisconnect.scp", "masserase-script": "kinetismasserase.scp" } } ] } Here is the preconnect script that i wrote: 1 Print "Preonnect Script" 10 REM check for debug probes 20 PROBELIST 30 REM open connection to debug probe 40 PROBEOPENBYINDEX a% 50 REM set the reset line 60 WIREHOLDRESET a% 0 Missing fact: the preconnect scripts have to be located in the folder "Linkserver_XXXX\binaries\ToolScripts\". If they are in the "Scripts"-Folder they are not found. Also there is no error message that the script is not found. Also the print statement in the .scp file is not showing up in the command line output. Now, everytime I run linkserver.exe with this configuration, I can connect to the microcontroller without a problem. Re: Flashdownload with Linkserver: connect to target under reset required Hi @m_p  Thank you for reaching out! I think that we could test using a custom reset script. By looking the MCUXpresso IDE documentation, we can see that there are some ways to handle how debugger manages reset, appart from connect. You could try these options but there is the option for  reset script. This is further described here: I did not find a Kinetis reset script, on  particular, but in the linksersver there are some reset scripts for other MCUs, they may help as referece , example path is C:\nxp\LinkServer_1.5.30\binaries\Scripts Please let me know if this helps, or any other related question you may have. Diego

S32G2RM serial / unique controller id Hello,  I'm searching for a unique / serial id of the S32G2RM controller. Found this for peritherals but in not in gerneral for the controller. Can you please give me hit where I can gut this?  Thank you very much in advance.  Best regards Ralph Re: S32G2RM serial / unique controller id Hi, We understand that the UID is put into the FUSEs available under the S32G platform. To be able to read them, S32G2 provides an OCOTP peripheral [Page 3358, S32G2 Reference Manual, Rev. 8, February 2024]. The Fuse Map of the S32G2 is embedded under the S32G2 Reference Manual by the name "S32G2_fuse_map.xlsx": Please, let us know.

Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) Dear NXP Support Team, I want to attach a sensor in the UART port of the board and access via A55 core. I have tried below things but neither of them worked. Total available port from UART1 to UART8 – 8 Nos The UART4 port as a Xbee interface is available like ttyXBee, so I also attempted to transfer data using c code and directly using command line but none of them where worked. Followed the URAT instruction from this website, and I am getting port ttyLP3, ttyLP5 and ttyLP6 port. The port ttyLP3 and ttyLP5 have no pinout on the board. The ttyLP6 is connected with the console port which is ttyACM0 (UART to USB), so we cannot use it. Tried to configure UART7 (Mikroe interface) but the tty node is not created, maybe it missed configuration from dts side. (I am unsure about it) The UART1 is connected to the Bluetooth chip, so it cannot be accessible. No details found from UART2 and UART8.   Can you guide me how to access the UART port using A55 core of the board and C language programming? Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) Hi @rk4! Your UART7 is configured as a rs485 in file ccimx93-dvk.dts &lpuart7 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart7>; linux,rs485-enabled-at-boot-time; digi,rts-gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; only delete the line linux,rs485-enabled-at-boot-time; and the uart7 should be listed in the device folder with the name ttyLP6 Best Regards! Chavira Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) Hello @Chavira ,  Please find attached dts file that I am using. Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) HI @rk4! Please share your device tree file. Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) Dear @Chavira ,  Thanks for prompt response. Could you tell me how to create a ttynode for UART7 (MIKROE interface) in A55 core? OR if its already available in it, can you tell me what is the name of it? Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) HI @rk4! Thank you for contacting NXP Support! I don´t have access to the device tree of that board since is not an NXP board. I can help you to analyze the device tree if you can share the device tree with me. Unfortunately we don´t have any guide of how to use UART ports in Linux, but you can check some guides in internet like this guide. For Further support please contact to digi support. Best Regards! Chavira

S32G2 load dtb I got dts both in ATF and in kernal.When the board boots,Which dtb it will actually use?Or it will load both? Thank u. Re: S32G2 load dtb Hi, Both DTB/DTS will be used. When booting, TF-A/uboot will use the TF-A DTS/DTB, when uboot passes the control to the kernel, the kernel will use its own DTB/DTS. There is no conflict between both. Both DTB/DTS should be configured accordingly, if not when uboot passes control to the kernel, devices might not be available to the kernel itself. Please, let us know. Re: S32G2 load dtb Sorry，I can not understand well and could you describe it more detailed.I can find the same device in DTS both in ATF and kernal. Do they conflict with each other? Re: S32G2 load dtb Hi, Both DTB's will be used at the end, but the one that is available under the root partition of the SD card should be the Kernel one. Please, let us know.

iMxRT1040 Boot FlexSPI and DQS Hi, I have a problem with my configuration to fit all the required peripherals. I plan to use external Quad SPI NOR Flash with no Strobe. (as the EVK). I need to use : CCM.CLKO1 [J4] and CCM.CLKO2 [J1]. I need one FlexSPI (for ext Flash) and one uSDHC for SdCard. The 2 clocks outputs prevent me from using uSDHC1. Then, I have to use uSDHC2 for the SdCard that has the CMD signal on [M4]. The [M4] pin is shared with FLEXSPI.A_DQS. What's the best way to use SdCard and boot on FlexSPI ? Can I boot easily on FLEXSPI2.A ? or should I use FlexSPI1.A with internal loopback Strobe ? Thanks in advance, Re: iMxRT1040 Boot FlexSPI and DQS Hi @jfz_arturia , Thank you for your interest in the NXP MIMXRT product, I would  like to provide service for you. Question: Can I boot easily on FLEXSPI2.A ? Answer: No, You can't.  In IMXRT1040RM reference manual, You can see that NOR Flash can only be  boot on FlexSPI1 Question: or should I use FlexSPI1.A with internal loopback Strobe ? Answer:  You can use this mode, but the max Frequency of operation is limited to 60MHz if you use this mode . https://www.nxp.com/webapp/Download?colCode=IMXRT1040RM https://www.nxp.com/docs/en/data-sheet/IMXRT1040CEC.pdf Wish it helps you. If you still have question about it, please kindly let me know. Wish you a nice day! Best Regards MayLiu

I2C MPC5478G Hi, I want to communicate with an amplifier using the MPC5748G. I'm using the i2c_transfer_mpc5748g sample code from the Power Architecture. The amplifier's address is 0x70. What modifications do I need to make to achieve this? also i2c driver sends adress->data  but i want to make it adress of amplifier(adress) ->amplifier register(subadress)-> data. Re: I2C MPC5478G Hi, the Slave device address is set within Component inspector and it is automatically sent as first byte after START is issued. The Slave’s register/memory address, must be stored into first byte(s) of the “txBuffer” depending on address size.   So assuming 16bit address is used and you want to write 8 bytes (1,2,3,..,8) to Slave address 0x000C, then prepare txBuffer as   txBuffer = {0x00, 0x0C, 1, 2, 3, 4, 5, 6, 7, 8};   and use I2C_DRV_MasterSendDataBlocking(instance, txBuffer, 10, true, timeout);   If you want to read 8 bytes from the same memory address then use this   I2C_DRV_MasterSendDataBlocking(instance, txBuffer, 2, false, timeout); // just memory/register address will be sent after Slave address so total 3 bytes, STOP is not generated I2C_DRV_MasterReceiveDataBlocking(instance, rxBuffer, 8, true, timeout); // Repeat Start is issued following Slave address and waiting reading for 8 bytes Hope it helps. BR, Petr

i.mx8MPの最大メモリ密度 こんにちは、NXPチームの皆様、 サポートされているLPDDR4メモリの最大密度 i.MX8MPはどれくらいですか？ ありがとうございます Re: i.mx8MPの最大メモリ密度 ダニエルさん、こんにちは。 この情報はとても役に立ちます。 よろしく、サイモン Re: i.mx8MPの最大メモリ密度 i.MX8MPのメモリ密度はダイあたり32 Gb（ギガビット）で、これはダイあたり4 GB（ギガバイト）に相当します。 答えが分かるといいですね。

If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. I am using GoldVIP-S32G2-v1.6.0 on S32G2 due to some circumstances and I am having a problem. I referred to the User Manual.pdf file of GoldVIP-S32G2 v1.6.0 and proceeded as follows. 1. I installed Goldvip- S32G2 v1.6.0 and EBTresos ACG8.8.7, S32DS 3.4. 2. Follow the steps in Figure 13.4 Building the M7 Application below.   2-1. Generated the default configuration information using EBTresos.   2-2. I built using Util of GoldVIP-S32G2-v1.6.0 and created an Elf file.   2-3. create goldvip-gateway.bin file using objcopy in S32DS Build_tools folder. 3. create an SDcard using fsl-image-goldvip-s32g274ardb2.sdcard and replace only the goldvip-gateway.bin file in the SDcard to write to the board. 4. I checked using Trace32 Debug and found that it booted well and LLCE_CAN0 and LLCE_CAN1 were set to use. 5. The problem was that even though I sent LLCE_CAN0 and LLCE_CAN1 using CANoe, CAN Interrupt did not work, so I could not check the can data coming in. I used GoldVIP-S32G2-v1.0.0 two years ago and experienced that the CanIf_RxIndication function shown in the screen below is called when CANoe successfully sends CAN data in the same way as above. Currently, I confirmed that the CanIf_RxIndication function is not called in the same way, and after debugging, I realized that receiving CAN data does not cause an interrupt. I would be grateful if you could let me know if I missed something and what else I can do and if you need more information to answer. S32G-VNP-RDB2 AUTOSAR GOLDVIP 1.6 Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. Thank you for your continued response. I'm resolved.  When I disable CanMultiplexedTransmission and change both Filter and Mask to 0, I get an interrupt. It looks like filter and mask were preventing the data from coming in. Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. Hi, We might be misunderstanding the overall inquiry. If so we do apologize. For the following comment: "After writing, a CAN data is sent via CANoe, but CANoe shows that the transmission was successful, but no RX interrupt occurs in Trace32." We understand that you are able to receive CAN frames under the S32G2, is this correct? This might seem to be related to Trace32 rather than S32G2 if you are able to receive CAN Frames. Can you replicate the examples available under the BSP User Manual?  Please, let us know. Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. Hello Thank you for the reply. I was refer to GoldVIP-S32G2-1.6.0-User-Manual.pdf. I have attached the file. I didn't use anything related to the Linux BSP.  I used the fsl-image-goldvip-s32g274ardb2.sdcard file provided by NXP to create the SDcard. and then I created the goldvip-gateway.bin file for Firmware and then replaced the goldvip-gateway.bin on the SDcard as described in the question above. After writing, a CAN data is sent via CANoe, but CANoe shows that the transmission was successful, but no RX interrupt occurs in Trace32. For reference, when I installed and developed the RTD and LLCE Driver using S32DesignStudio, I found that CAN Rx interrupts were generated. Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. Hi, We apologize for the delay. Can you help us share the respective logs of your system? Also, were you able to run the available examples for LLCE CAN under the BSP User Manual?  Overall, we have not seen any problems with LLCE CAN not receiving information, for which seems to be a configuration problem.  Please, let us know. Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. There is a typo in the above post. The version of GoldVIP I've been using is v1.1.0, not v1.0.0. I used GoldVIP-S32G2-v1.0.0 two years ago -> I used GoldVIP-S32G2-v1.1.0 two years ago

How to flush the uart FIFO with CTS enabled for S32K146 Hi support team, We're using UART Tx FIFO function with CTS feature enabled. After having checked with the errata file of S32K146, we find that the ERR051629 is related to our case. My understanding of this issue is that if the CTS pin is changed to low during the tx FIFO is flushing with CTS feature enabled, the transmit complete bit will not be set, the workaround is to clear the MODIR[TXCTSE] bit before setting FIFO[TXFLUSH] bit to 1 if the CTS feature is enabled, and then set the MODIR[TXCTSE] bit again, such as the following code changes based on the NXP RTD code: /** * @brief : Flush Tx Buffer * * This function causes all data that is stored in the transmit FIFO/buffer to be flushed. * * * @Param Base LPUART Base pointer */ static inline void Lpuart_Uart_Ip_FlushTxBuffer(LPUART_Type * Base) { Base->MODIR &= 0xFFFFFFFEu; /*Clear (MODIR[TXCTSE]) bit*/ Base->FIFO |= 0x00008000u; /*reset the transmit FIFO (FIFO[TXFLUSH] = 0b1)*/ Base->MODIR |= 0x00000001u; /*Set (MODIR[TXCTSE]) bit*/ } Is my understanding correct? If it's not correct, how should I handle this problem?  Re: How to flush the uart FIFO with CTS enabled for S32K146 HI @snowy, CTS_B is asserted when the input voltage level goes LOW. The CTS_B pin must assert for longer than one bit period to guarantee that a new transmission is started when the transmitter is idle. The transmitter checks the state of the CTS signal each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the TXD signal remains in the mark state and transmission is delayed until CTS is asserted. So, it will not stop transmitting, it will send the data present in the FIFO. Regards, Daniel Re: How to flush the uart FIFO with CTS enabled for S32K146 Hi Daniel, Thank you very much for your reply. Could you please help check the following question? If the CTS pin is changed to low during writing data into tx FIFO, will the data stop transmitting until the CTS pin be changed back to high? Or the tx will be abort directly with data lost? Re: How to flush the uart FIFO with CTS enabled for S32K146 Helle @snowy, Yes, this is correct. If you have any specific question, let me know, BR, Daniel

Availability of board design files for MIMXRT1180-EVK Hello, Would it be possible to share the board design files for the MIMXRT1180-EVK? There is a link in the user manual (UM12021) which unfortunatly does not work (The collateral "MIMXRT1180-EVK-DESIGNFILES" does not exist). Fixing the link would of course also help me. Thank you, Kind regards, Jasper Re: Availability of board design files for MIMXRT1180-EVK Hello, the documentation is not available yet on the page until the launch date will be confirmed. I suggest contact your sales representative. Best regards, Pavel

S32K314 lwip tcp/ip multiple definition issue Hello, I am currently applying the lwIP TCP/IP stack to the S32K314 product and encountered a "multiple definition" error, so I am leaving a question. When I add the TCP/IP stack to the peripherals and build, the following error occurs: However, when I remove the multiple definition issue using linker options, the build succeeds as follows: Using linker options to bypass the multiple definition issue does not seem like a proper solution, so I want to address the root cause of the problem. Thank you. Re: S32K314 lwip tcp/ip multiple definition issue Thank you! Re: S32K314 lwip tcp/ip multiple definition issue Hi @malove  In the actual example, fsdata.c is not included for the compilation. only fs.c included. You can exclude the fsdata.c from build to avoid fsdata.o generation. which will help you to solve the problem without modifying the linker options. Thanks, Sathish. Re: S32K314 lwip tcp/ip multiple definition issue Thank you @PavelL  Re: S32K314 lwip tcp/ip multiple definition issue Hello @malove , I see your point now. Please check this: Re: linker error:multiple definition of `_start' - NXP Community Solved: Multiple definitions of functions 'isprintf' etc - NXP Community   Link Order: Using Multiple Definitions with ARM GNU Linker and Eclipse. Best regards, Pavel Re: S32K314 lwip tcp/ip multiple definition issue Hello @PavelL  What I want to clarify is that I am not trying to have two static IP addresses. Instead, I am trying to resolve the issue where certain elements in the fsdata.c source file are being defined multiple times. However, this file is not something I wrote myself; it is part of the TCP/IP stack that I am using as is. I am not sure how to modify or resolve this issue. Re: S32K314 lwip tcp/ip multiple definition issue Hello @malove , what is your goal? To have two static IP addresses? As far as I know, dual stack IPv4 and IPv6 should work on lwip. However, I did a web search but I didn't find a solution - all questions like this one mapping multiple * IP addresses to one Ethernet interface (LWIP) - NXP Community stayed unanswered or the solution didn't work. So, it looks like not feasible. As David already replied to here S32K3 Lwip iperf test issue - NXP Community, LWIP is an open source and we do not have resources to support. Best regards, Pavel

If its normal behavior 88W8997 2.4G STA bgn mode can only get ~150 Mbps THP in shielding room. platform (Host CPU): i.mx8mm OS: Linux 5.15.71_2.2.1 HW: i.mx8mm customer board + WiFi module: AW-CM276MA-PUR (M.2) BSP version: Linux 5.15.71_2.2.1 Driver version and Wi-Fi and Bluetooth/Bluetooth LE Firmware version: PCIE8997--16.92.21.p55.3-MM5X16366.p5-GPL-(FP92) AP: ASUS and MSI AP Router in Shielding room Customer test 2.4G bgn mode 40MHz THP iperf test. Test 1: Default settings, only can get ~150Mbps Test 2: if set script before iperf test mlanutl mlan0 httxcfg 0x07F mlanutl mlan0 htcapinfo 0x21C20000 THP can reach ~240Mbps -> Customer has questions on Test 1. if its normal behavior? Note: there is no STA bgn mode 40MHz speed result reference data in RN. @Christine_Li  Please help to clarify. Re: If its normal behavior 88W8997 2.4G STA bgn mode can only get ~150 Mbps THP in shielding room. Hi, @yao_feng  Please see your email, I have sent my reply through SFDC's email. Best regards, Christine. Re: If its normal behavior 88W8997 2.4G STA bgn mode can only get ~150 Mbps THP in shielding room. Hi， @yao_feng  I will check it and reply you ASAP. Best regards, Christine.

EmiOSチャネルPWM出力を無効にする方法 こんにちは、EMIOSの特定のチャネルでPWM出力を無効にしたいです。これは関数を通じて実現できますか?その方法を教えてください。 日時:エミオスチャネルのPWM出力を無効にする方法 こんにちは@fengba_360  レジスタに書き込むことでそれを達成することは可能ですか?はい その場合、具体的なプランを教えてください。 主に EMIOS チャネルをディセーブルにするには、チャネルの制御レジスタ 2 とストップ クロックをクリアし、チャネルの制御レジスタをクリアし、An レジスタと Bn レジスタをクリアする必要があります (S32K3xx リファレンス マニュアル、Rev. 8 のセクション 63.8.6 を参照)。追加の手順がある可能性がありますが、一部のチャネル構成で異なります(手順についてはEmios_Pwm_Ip_DeInitChannel()関数で詳しく説明します)。 日時:エミオスチャネルのPWM出力を無効にする方法 レジスタに書き込むことでそれを達成することは可能ですか?その場合、具体的なプランを教えてください。 感謝！

如何禁用 emios 通道 pwm 输出 你好，我想禁用EMIOS特定通道的PWM输出。我可以通过函数实现这个吗？你能告诉我怎么做吗？ 回复：如何禁用 emios 通道 pwm 输出 嗨@fengba_360 是否可以通过写入寄存器来实现？是的 如果有的话，能告诉我具体的计划吗？主要是为了禁用EMIOS通道，您必须清除控制寄存器2并停止通道时钟，清除通道的控制寄存器并清除An和Bn寄存器（参考S32K3xx参考手册第63.8.6节，修订版8）。可能还有其他步骤，但取决于某些通道配置（步骤在 Emios_Pwm_Ip_DeInitChannel() 函数中有详细说明）。 回复：如何禁用 emios 通道 pwm 输出 是否可以通过写入寄存器来实现？如果有的话，能告诉我具体的计划吗？ 谢谢！

S32K344 Lock-step kernel HI, The S32K344 can be used with single-core, multi-core, or Cortex-M7 lock-step cores. I have learned that the highest level of ASIL B/D compliance can be achieved using lock-step nuclei. What do I need to do to be able to use the lockstep core ability Look forward to reply Re: S32K344 Lock-step kernel Hello, I need to verify. What do I need to do I do not understand. What do you need to verify? It is HW feature and once the Lockstep is enabled is in active all the time. If there is and issue in redundancy the FCCU will report fault. There is nothing you can verify. No user access to checker core is possible. there is just no interface. best regards, Peter Re: S32K344 Lock-step kernel HI, Thank you very much for your reply I see that the lock core of the S32K344 is enabled. As far as I know, both cores run the same program to keep them safe after the lockstep core is enabled. I need to verify. What do I need to do Re: S32K344 Lock-step kernel Hello, All information are available in reference manual. There is basically nothing to know as it is HW feature. You can learn more for example from this article: Best regards, Peter Re: S32K344 Lock-step kernel HI， Thank you very much， Can you share more information about S32K344 lockstep? I want to know more about the function of S32K344 lockstep Looking forward to your reply Re: S32K344 Lock-step kernel Hello, An example code using C40 IP driver to write in UTEST memory, please find it in the attachment. It writes 8 bytes with 0xAA in a free location after 0x1B001B00 address. So change the code accordingly to write lockstep_en in UTEST_Misc on first free location in DCF user space. Please be sure MPU is not protecting UTEST memory in your code. Best regards, Peter Re: S32K344 Lock-step kernel Thank you very much for your reply， Forgive me for not understanding your reply Do you have a sample program for my reference？ Re: S32K344 Lock-step kernel Hello, You need to simply switch the device into lock step mode via DCM records. In S32K3xx_DCF_clent excel sheet attached to the reference manual you can see the All you need to do is to program DCF client UTEST_MISC to UTEST memory with bit LOCKSTEP_EN set to 1. For details please refer to reference manual : 21.3 UTest NVM sector You will do the write to DCF user space area of UTEST: Best regards, Peter

MIMXRT1061CVL5B Queries Hello team, We had few queries regarding MIMXRT1061CVL5B: 1. Can we use standard SPI instead of Quad SPI for interfacing NAND Flash? 2. Is there any max capacity limit for external Flash? 3. If we are using same supply for SNVS and main domain, can only main domain be turned off such that we can achieve low sleep/standby current? Or we need to provide separate supplies for both rails? 4. Can the MCU boot from external NAND Flash? Please share details about the booting process. i.MXRT 106x Re: MIMXRT1061CVL5B Queries Hello Omar, Thanks for the feedback. Re: MIMXRT1061CVL5B Queries Any pin capable of interrupt can be used as wake-up source from low power modes different from SNVS mode. Re: MIMXRT1061CVL5B Queries Hello Omar, Thanks for the feedback. I kindly request you to let me know which section of Datasheet or RM has to be referred to know about how many pins are wake-up capable in Suspend Mode. Re: MIMXRT1061CVL5B Queries Hello, I hope you are well. 1. If you plan to use the NAND flash as booting device then it is not possible, for this FlexSPI interface is used. Standard SPI can be used for data but performance will be limited to LPSPI. 2. It is limited to the available addressing space of FlexSPI on the system memory map. 3. If SNVS is also supplied by the main domain then you will be limited when entering on SNVS low power mode only. 4. Yes, it can boot from NAND Flash but it will not support XIP, please refer to chapter 9.6.2 for more details for booting. 5. Yes, that one pin is only limited to wake the device from SNVS mode but other GPIO can be used as wakeup on other power modes.  Best regards, Omar Re: MIMXRT1061CVL5B Queries 5. Can we have more wake-up pins in any other version which has similar features as this, as MIMXRT1061CVL5B has only 1 wake-up capable pin.

Can you provide the FS26 datasheet? Hi, Can you provide the FS26 datasheet?

PDB Interrupt in S32K144 how to enable How to enable the interrupt in PDB module of S32K144 MCU via Autosar RTD of 2108 Re: PDB Interrupt in S32K144 how to enable Hi, Thank you so much for your interest in our products and for using our community. There is no PDB example with autosar mcal, but you could refer to the following community thread: https://community.nxp.com/t5/S32K/ADC-project-using-MCAL/td-p/1616331 Hope it helps you. Have a nice day! Re: PDB Interrupt in S32K144 how to enable Also, in Channel Configuration. I cant select channel Index value of 0 for anothe channel. So how i am supposed multiple channels via PDB for ADC?

NTAG 424 Tamper encryption Hi, need help with NTAG424 TT: enabling tamper function with key 0 (or 1,2,3,4 doesn't care) using SetConfiguration option 07 i get 9100 as response so seems everyting ok. But in the NDEF message the mirroring of TT is always in clear as the key remains at E as the default value. I tried with my Python app and with TagExplore, result is the same. Any hint? Mario Re: NTAG 424 Tamper encryption Im having the same problem! Can you help me? How did you solve it?? Re: NTAG 424 Tamper encryption Thanks Daniel, with several try and fix i managed to have the TTStatus encrypted in NDEF. Mario Re: NTAG 424 Tamper encryption Thanks Daniel, reading better the datasheet, TTStatuskey is not used to encrypt the tamper status in NDEF but as authentication to issue the GetTTStatus command. Unfortunately i dont' find how to encrypt TTStatus in NDEF: i red on AN12196 that is possible using the EncData but don't know how. Moreover fig. 3 and 4 at page 9 show the encryption of TTStatus OR Static data, i'd like to have both if possible Thanks, Mario Re: NTAG 424 Tamper encryption Hi  could you please let me know your detail steps, so I can reproduce your issue on my side with RFIDDiscover? Regards Daniel