Regarding the limitations of Key Scramble settings Hi NXP According to NXP application note, OTFAD_KEY_SCRAMBLE and ALIGN were arbitrary word and byte. But when I set non-SPT default values (0x33AA55CC & 0x1B), the RT10101 fails to decrypt and boot .[On my EVT board] .It stops in ISP mdoe. =================================================================== On the NXP RT1010 EVB, writing the default settings(0x33AA55CC & 0x1B) allows it to boot successfully. The following are the steps on NXP EVB Step 1. Burning fuses[OTFAD KEK & SCRAMBLE] => boot successfully. Step 2. Burning fuses[HAB] => boot successfully. =================================================================== On non-NXP EVB device, writing the non-default settings ,the RT10101 fails to decrypt and boot and stops in ISP mdoe. The following are the steps on my EVT board Step 1. Burning fuses[OTFAD KEK] => boot successfully. Step 2. Burning fuses[HAB] => boot successfully. Step 3. Burning fuses[SCRAMBLE] => boot Fail. I use SPT for programming, and during the programming process, it will verify that the SPT fuses settings match the device. Therefore, my settings should be correctly written to my EVT board. Using the SPT OTP setting function, I also confirmed that my settings were successfully written to the eFuses. I tried changing the OTFAD encryption block to an unwritten block (e.g., 0x60020000), and my EVT board can boot normally. =>This indicates that there might be an issue with the decryption process. =================================================================== Based on the above successful and failed boot cases: 1. Does the order of writing eFuses affect the functionality of OTFAD and Scramble? 2. Are there any configuration limitations for OTFAD_KEY_SCRAMBLE and ALIGN? Does this mean there is an issue with OTFAD and Scramble? Re: Regarding the limitations of Key Scramble settings Hi Stefano, Here is an update for your problem: for i.MX RT116x/7x, the image_enc utility was replaced by nxpimage already in SEC v7. That's why SEC v7 produces same problem in keyblob as SEC v10. For RT117x kindly use SEC v6. You can still use the processor with your custom fuses, only the keyblob needs to be fixed (bootable_images\otfad_keyblobs.bin).  Alternatively, it shall be also possible to generate keyblob in SEC v6 and replace the keyblob generated by SEC v10 (it is possible to add hook into SEC v10 build script). To do this, you must have all keys and all OTFAD parameters same in both workspaces. We are sorry for inconvenience Re: Regarding the limitations of Key Scramble settings Hello Marek, I can confirm that image produced with V7 using a scramble value of 0x19a8c836 and a scramble align of 0xd6 doesn't work - while using the default values the image works. Note however that I used different keys and random counter. I carefully checked fuse settings on the non-working board (the one with the mentioned scramble values) and they look correct. Apparently, image_enc tool is producing a bad key blob. As a side note, I am surprised that issues on such a sensitive topic (image protection) are not being appropriately addressed: how is it possible that, although ages have passed, it is still not possible to reliably get a correctly formed bootable image from SPT? Best regards, Stefano Re: Regarding the limitations of Key Scramble settings Hi Stefano, scramble for RT116x/7x and RT10xx is confirmed bug in MCUXpresso Secure Provisioning tool v10 and currently there is not planned any hotfix. RT117x is supported since MCUXpresso Secure Provisioning tool v5, so we recommend to use older version (v7). There is not known such problem for image_enc tool. For the input image, kindly follow the description in chapter 6.2.1.1 and disable XIP_BOOT_HEADER_ENABLE (images with the header are not supported in tool version 7). We are sorry for inconvenience Re: Regarding the limitations of Key Scramble settings Hello, having same trouble on rt1176 using SEC V10 - can you confirm the problem still exists on V10? Besides, since V7 does not accept binary images with boot header nor ELF files (at least, not those built within MCUXpresso IDE v11.9.0 Build 2144), I'm having hard times with V7 too - and the encrypted image (from blinky sample) does not work anyway. Looks like older image_enc tool suffers the same bug with some scrambling value and/or align. I am quite surprised this issue has not been addressed yet, since it is actually a security flaw - scrambling is definitely useless if you can (safely) use only default values. Kudos Stefano Re: Regarding the limitations of Key Scramble settings Hi Omar, yes, use SEC v7. The problem is in nxpimage utility, which is used to generate keyblob since SEC v8. In the older versions, keyblob was generated using image_enc utility. Re: Regarding the limitations of Key Scramble settings Hi @marek-trmac     I am using SPT V9.0.1.  Do you mean that I need to use version V7.0 to generate the correct keyblob data based on my scramble values ?  Re: Regarding the limitations of Key Scramble settings Hi Omar, we confirm the problem, we found the keyblob is generated wrongly for same scramble values. The problem is reproducible since SEC tool v8. Could you use SEC tool v7? In version 7 the tool uses image_enc utility to generate the keyblob and there is no such issue. We are sorry for the inconvenience. We'll fix the problem for next release. Re: Regarding the limitations of Key Scramble settings Hi @marek-trmac  Thank you for your reply.  what ALIGN fuse value did you burn? =>Since the setting values are intended for future production, it is inconvenient to disclose them. I can only say that I have set them within the range of 0x00 to 0xFF. Does default OTFAD settings works on your custom board? =>Due to concerns about causing the aforementioned situation again, I am currently not burn any scramble config( OTFAD_KEY_SCRAMBLE and ALIGN) to the custom board. Re: Regarding the limitations of Key Scramble settings Hi Omar, what ALIGN fuse value did you burn? Does default OTFAD settings works on your custom board? Re: Regarding the limitations of Key Scramble settings Hi @marek-trmac      Thank you for your reply.     I have used SPT to erase the flash in the above steps, and then used SPT to rewrite the updated KEY blobs and firmware. Re: Regarding the limitations of Key Scramble settings Hi Omar, after you burn SCRAMBLE, you need to update key blobs (because key blobs are affected by the SCRAMBLE). There is application note with details about OTFAD encryption on RT101x, which might help: AN12670 How to use encrypted XIP boot.in i.MX RT1010 About ALIGN, please refer to chapter "Key blob KEK details" in Security Reference Manual.

spi5に関連するハードウェアリセット コミュニティの皆さん、こんにちは。 ボード:S32G399AAAVUC ソフトウェア:bsp40 Mcoreでspi5を使用し、Acoreのデバイスツリーでspi5ノードを無効にすると、奇妙な問題が発生しました。shutdownコマンドを使用し、シャットダウンが完了した後にハードウェアのリセットが発生しました。問題を解決するためにAcoreのデバイスツリーでspi5ノードを削除しましたが、再びは発生しませんでした。特にこのノードはすでに無効になっているため、この問題の原因を知りたいです。なぜ削除する必要があるのですか? S32G3の  Re: spi5に関連するハードウェアのリセット こんにちは、 @chenyin_h あなたの通知をどうもありがとう、私はより高いレベルのデバイスツリーがそのステータスを大丈夫に設定しているのを見つけました。心から感謝します。 BRの ヤン

ADC SC1 への DMA 書き込み 皆さん、こんにちは サンプリングしたいADC入力は>8個あり、FTM PWM INITトリガと同期しています。 これにはPDBを使用しています。しかし、W 以外の S32K を使用しているため、PDB で CH0 と CH1 をバックツーバック リンクすることはできません。 私は、DMA(ADC COCOによってトリガーされる)がADC_SC1nを書き換えて、より多くの入力をパルスごとに「リンク」する解決策が機能することを考えました。しかし、DMAを介してSC1nに書き込むと、PDBがADCを再度トリガーできなくなるようです(最初のチャネルのESがハイになります)。 これを達成する方法について誰かがアドバイスできますか? ありがとうございます ジョーイ

imx93evk 重建内核映像并替换 ！这是我为imx93evk构建的命令 $ mkdir imx-yocto-bsp $cd imx-yocto-bsp $ repo init -u https://github.com/nxp-imx/imx-manifest-b imx-linux-scarthgap -m imx-6.6.36-2.1.0.xml $ repo 同步 $ mkdir -p 下载 $ CD下载 $ mkdir linux-imx；cd linux-imx $ git clone https://github.com/nxp-imx/linux-imx.git $ cd../.. $导出BSPDIR = $（pwd） $ DISTRO=fsl-imx-wayland MACHINE=imx93-11x11-lpddr4x-evk 源 imx-setup-release.sh -b buildwayland $ bitbake imx-图像多媒体 构建完成后，目录 imx-yocto-bsp/buildwayland/tmp/sysroots组件/imx93_11x11_lpddr4x_evk/imx-boot/boot 将包含 imx-boot-imx93-11x11-lpddr4x-evk-sd.bin-flash_单启动 ! 正在使用 $ sudo ./uuu-b emmc_all imx-boot-imx93-11x11-lpddr4x-evk-sd.bin-flash_singleboot ！更新图像以反映我在 linux-imx 中所做的内核更改的正确方法？ ! 推荐的仅构建 Linux 内核并仅替换内核的方法是什么？ 是吗 $ cd linux-imx $制作imx93_11x11_evk_defconfig $ make ！我应该专门刻录哪个映像来替换内核？ BR，科林         回复：imx93evk 重建内核映像并替换 完成重建后，您可以使用scp命令将内核映像复制到您的主板 回复：imx93evk 重建内核映像并替换 是的，您能提供我们可以遵循的步骤吗？ 回复：imx93evk 重建内核映像并替换 这里您是否只需要重建并更新板上的内核？

Calibration features Hello,  I wonder if FreeMaster is capable of being used as a calibration tool. For example, calibrate a thermistor with a NXP board.  Another question on top of this: is it possible to apply a function to a raw signal before it is displayed on a graph in FreeMaster? Thanks  Re: Calibration features Hi @Vast-Horizon, Yes, you can use FreeMASTER as calibration tool. Here's an example of how it could be used in such scenario: Implement the algorithm in the embedded application Store algorithm parameters in global volatile variables Use FreeMASTER to read algorithm parameters at runtime Use FreeMASTER to update parameter values to fine tune the algorithm You can also apply transformation functions on the variables before those are displayed. This option is available in the Variable menu (Project -> Variables -> Edit): Note: transformations are applicable only to REAL values (top right option) Hope it helps, Iulian

About MC33PT2000 software：BASIC-FRDMPKPT2000EVM We used the same PSC assembly code in the file(BASIC-FRDMPKPT2000EVM) with the PT2000 IDE to generate the PT2000_LoadData.c file, but it is different from the file in BASIC-FRDMPKPT2000EVM, as shown in the picture.  user code: Original: The number of arrays is different. One is unsigned short PT2000_code_RAM1[105], another is  unsigned short PT2000_code_RAM1[107]. Is there an error in the document assembly code? Can you provide consistent code? Re: About MC33PT2000 software：BASIC-FRDMPKPT2000EVM Thank you！ I didn't changed anything on  BASIC-FRDMPKPT2000EVM Project. The download address: The Original C code: But,Both methods worked, so the issue is resolved. Thank you very much! Re: About MC33PT2000 software：BASIC-FRDMPKPT2000EVM Hello Hongyu, Where did get your BASIC-FRDMPKPT2000EVM Project? For PSC assembly code, we usually call it microcode. Can you share your SW project here? I think you have changed something on your  BASIC-FRDMPKPT2000EVM Project but you didn't notice. Or you can generate a new BASIC-FRDMPKPT2000EVM Project as below way and try it again And below is the Original RAMx section as your first page. Re: About MC33PT2000 software：BASIC-FRDMPKPT2000EVM Hello Hongyu, I have asked our application engineer who is in charge of the PT2000 to look into it. He is currently OoO, but will be back next week.  Thank you in advance for your patience. BRs, Tomas

Debuggers cannot connect to MIMXRT1062 after core calls NVIC_SystemReset Hi, I'm here to bring back a ghost from the past.  Specifically, this thread. I'm working on the port of Mbed OS CE to MIMXRT1062, and have run into this issue when trying to set up our test suite.  Basically, anytime the code running on the M7 core calls NVIC_SystemReset, debuggers lose the ability to connect to the core. LinkServer prints: Ns: MCUXpresso IDE RedlinkMulti Driver v11.6 (Oct 3 2022 08:09:13 - crt_emu_cm_redlink.exe build 9) Pc: ( 0) Reading remote configuration Wc(03). No cache support. Nc: Found chip XML file in I:/RPL/mbed-os/targets/upload_method_cfg/redlink_cfgs\MIMXRT1052xxxxB.xml Pc: ( 5) Remote configuration complete Nc: Restarted LinkServer process (PID 30668). Wc: ============= SCRIPT: RT1050_connect.scp ============= Wc: RT1050 Connect Script Wc: DpID = 0BD11477 Wc: APID = 0x04770041 Wc: Disabling MPU Wc: Configure FlexRAM for 256KB OC RAM, 128KB I-TCM, 128KB D-TCM Wc: Finished Wc: ============= END SCRIPT ============================= Nc: Probe Firmware: DAPLink CMSIS-DAP (ARM) Nc: Serial Number: 0227000047784e4500559004d7450044ddb1000097969900 Nc: VID:PID: 0D28:0204 Nc: USB Path: \\?\hid#vid_0d28&pid_0204&mi_03#7&316d2a6&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030} Nc: Using memory from core 0 after searching for a good core Pc: ( 30) Emulator Connected Xr: Pc: ( 40) Debug Halt Nc: connection failed - Ep(03). Invalid ID for processor... Retrying Nc: Using memory from core 0 after searching for a good core Nc: On debug connection - reset using system reset Pc: ( 30) Emulator Connected Pc: ( 40) Debug Halt Ed:02: Failed on connect: Ep(03). Invalid ID for processor. Et: Probe(0): Connected&Reset. Was: NotConnected. DpID: 0BD11477. CpuID: 00000FFF. Info: Nc: Last stub error 0: OK Nc: Last sticky error: 0x0 AIndex: 0 Nc: Debug bus selected: MemAp 0 Nc: DAP Speed test unexecuted or failed Nc: Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled. Pc: (100) Target Connection Failed PyOCD prints: 0000350 I Target type is mimxrt1060 [board] 0000405 I DP IDR = 0x0bd11477 (v1 MINDP rev0) [dap] 0000433 I AHB-AP#0 IDR = 0x04770041 (AHB-AP var4 rev0) [discovery] 0000446 W Invalid coresight component, cidr=0x0 [rom_table] 0000450 I IMXRT Boot Mode: Boot From Fuses [target_imxrt] 0000458 I CPU core #0: Unknown (CPUID=0x00000000) r0p0, v6.0-M architecture [cortex_m] 0000471 I Loading /home/jamie/Mbed/mbed-os/cmake-build-develop-mimxrt1060evk/hal/tests/TESTS/mbed_hal/rtc_reset/test-mbed-hal-rtc-reset.bin at 0x60000000 [load_cmd] 0000496 I IMXRT Boot Mode: Boot From Fuses [target_imxrt] 0000499 I IMXRT Boot Device: 0 [target_imxrt] 0000545 C cannot write registers r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, psp, msp, lr, pc, xpsr, cfbp because core #0 is not halted [__main__] OpenOCD prints: Info : 114 157 adi_v5_swd.c:370 swd_connect_single(): SWD DPIDR 0x0bd11477 Debug: 115 160 arm_adi_v5.c:679 dap_dp_init(): imxrt.dap Debug: 116 160 arm_adi_v5.c:711 dap_dp_init(): DAP: wait CDBGPWRUPACK Debug: 117 160 arm_adi_v5.h:638 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000 Debug: 118 164 arm_adi_v5.c:719 dap_dp_init(): DAP: wait CSYSPWRUPACK Debug: 119 164 arm_adi_v5.h:638 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000 Debug: 120 166 cmsis_dap.c:808 cmsis_dap_swd_write_from_queue(): refusing to enable sticky overrun detection Debug: 121 169 openocd.c:151 handle_init_command(): Examining targets... Debug: 122 169 target.c:1843 target_call_event_callbacks(): target event 19 (examine-start) for core imxrt.cpu Debug: 123 169 arm_adi_v5.c:1095 dap_get_ap(): refcount AP#0x0 get 1 Debug: 124 173 arm_adi_v5.c:1038 dap_find_get_ap(): Found MEM-AP AHB3 at AP index: 0 (IDR=0x04770041) Debug: 125 181 arm_adi_v5.c:825 mem_ap_init(): MEM_AP Packed Transfers: disabled Debug: 126 181 arm_adi_v5.c:836 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0 Debug: 127 185 target.c:2628 target_read_u32(): address: 0xe000ed00, value: 0x00000000 Error: 128 185 cortex_m.c:2363 cortex_m_examine(): [imxrt.cpu] Cortex-M PARTNO 0x0 is unrecognized Debug: 129 185 target.c:1843 target_call_event_callbacks(): target event 20 (examine-fail) for core imxrt.cpu Basically it seems like, in this situation, the CPU ID reads as 0, so no debugger is able to talk to the core. The original thread (linked above) implied that this error was due to not doing a JEDEC reset of the flash.  However, I dug into the article linked by the thread, and it looks like this is an issue specific to using the flash chip in XIP Enhanced mode. In this mode, normal commands don't work, so when you reset the chip, boot will fail if you do not use a JEDEC reset that gets the chip out of XIP Enhanced (AKA Continuous Read) mode first. However, this situation does not match the configuration that the MIMXRT1060_EVK board is in. I double checked all the flash sequences, and we do not enable XIP Enhanced mode -- in fact, the flash doesn't support it at all. Additionally, the MCU does continue to work after being reset. It just cannot be flashed. This is conclusive proof that this issue is not caused by an inability for the MCU to read its XIP flash. Instead, what I think is going on here is either (a) resetting the MCU somehow disables the ARM JTAG TAP, so the CPU will not talk over the debug port, or (b) resetting the MCU is interfering with some pin mapping used by SWD, so the SWD connection itself dies after the MCU is reset.   Would really appreciate if someone on the NXP side could confirm that this is an issue and explain what's going on here. For now, I did find one workaround, which is to pass "-Oconnect_mode=pre-reset" to pyocd.  This causes it to issue a reset before connecting, which appears to prevent the issue from happening.  Unfortunately, I have not been able to find a similar workaround with LinkServer, which makes it basically unusable for my application.  At minimum, I would really appreciate if you guys could add a "reset before connect" option to LinkServer, or some kind of fallback mode that detects when the MIMXRT CPUID is 0 and tried to reset it. i.MXRT 106x Re: Debuggers cannot connect to MIMXRT1062 after core calls NVIC_SystemReset Hi @MultipleMonomials , As far as I know, it should be at the evaluation stage at the moment. The real implementation will take some time, but if the project is deployed, it should greatly improve everyone's debugging experience in RT MCUs. The debugging experience is not only soft reset, but even the FDCB header of XIP will be improved. Thanks for your understanding! Best regards, Gavin Re: Debuggers cannot connect to MIMXRT1062 after core calls NVIC_SystemReset Thanks for looking at this Gavin. Do you know if any fix/workaround for this is on the LinkServer roadmap anytime soon? (either a fix for the actual issue or a way to make LinkServer do a HW reset before connecting). It makes it all but impossible to use LinkServer for our automated test suite in Mbed OS -- we have to use PyOCD and it's way slower. Re: Debuggers cannot connect to MIMXRT1062 after core calls NVIC_SystemReset Hi @MultipleMonomials , I've double-checked the internals for you over the last few days, and losing the debugger connection after calling NVIC_SystemReset seems to be the expected behavior. "0x202090" is ROMboot entry address. The linkserver debug probe will hold the MCU immediately after NVIC_SystemReset. And I have not found linkserver to have a similar feature as you describe. Sorry for that. Best regards, Gavin Re: Debuggers cannot connect to MIMXRT1062 after core calls NVIC_SystemReset Hi Gavin! I do not believe that this issue is related to Mbed OS at all.  In fact, Mbed OS is built on top of the MCUXpresso SDK, and we use the bootup code and NOR flash configs from the SDK almost unmodified. This issue should be reproducible by adding a call to NVIC_SystemReset() to any existing MCUXpresso project.  (it would probably be a good idea to reset only when a button is pressed to avoid sending the board into a reset loop). Yep, I am using an MIMXRT1060 EVKB board running DAPLink firmware, with LinkServer 24.9.75. Thanks for your help on this, hope this makes sense! Re: Debuggers cannot connect to MIMXRT1062 after core calls NVIC_SystemReset Hi @MultipleMonomials , Thanks for your interest in NXP MIMXRT series! Since the official SDK from NXP does not contain a support project for MEBED OS, it may be necessary for you to provide us with more information. Thanks in advance!  1. Can the phenomenon you mentioned be reproduced using the NXP SDK examples? Or does it only exist in the Mebed project? 2. If the latter, can you provide a reproducible routine? 3. Also, just to confirm with you, the environment you are using is DAP Debugger + LinkServer, right? Best regards, Gavin

how imx8mm evk platform ddr4 calibrate? HI ALL I am study the ddr4 calibrate steps now, and have some confuse for ddr4 calibrate with following link. https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467 From the MSCALE_DDR_Tool_User_Guide.pdf,  it seems that the target platform didn't need run any sd card image when ddr4 calibrate, why MSCALE_DDR_Tool.exe can download the bin file to the target? regards jason Re: how imx8mm evk platform ddr4 calibrate? all of these  .bin files will be downloaded. Re: how imx8mm evk platform ddr4 calibrate? I means that when run the MSCALE_DDR_Tool.exe tool，my platform didn't run any image,  the download log as follow: Downloading file 'bin\lpddr4_train1d_string_v201709.bin' ..Done Downloading file 'bin\lpddr4_train2d_string_v201709.bin' ..Done Downloading file 'bin\lpddr4_imem_1d_v201709.bin' ..Done Downloading file 'bin\lpddr4_dmem_1d_v201709.bin' ..Done Downloading file 'bin\lpddr4_imem_2d_v201709.bin' ..Done Downloading file 'bin\lpddr4_dmem_2d_v201709.bin' ..Done Downloading IVT header...Done Downloading file 'bin\m845s_ddr_stress_test.bin' ...Done Download is complete Waiting for the target board boot... so which one use the usb port download the bin files? Re: how imx8mm evk platform ddr4 calibrate? hi @jxingyang   Because for DDR calibration part. only need run the DDR firmware is OK. do not need full iamge.

S32G TSNの こんにちは、専門家 s32g399aとsja1110スイッチを使用していました。TSNのオン/オフの設定やCBSやその他のシェーピング機能の有効化など、TSN機能をどのように設定できますか。何か仕様はありますか?ありがとうございます。 日時:S32G TSN タンクはたくさんあります。

Create .wic file that contains signed flash.bin and Image Hello, I have successfully been following the instructions from uboot-imx/doc/imx/habv4/guides/mx8m_secure_boot.txt at lf_v2022.04 · nxp-imx/uboot-imx to enable HABv4 on my iMX8MP. I now have: The signed bootloader signed_flash.bin The signed kernel Image_signed.bin The (unsigned) OS image .wic Currently, I have been flashing the .wic file to an SD card and manually replaced flash.bin and Image with their signed counterparts. I was wondering whether there is a way I could modify my Yocto recipe so that the resulting .wic file already has the signed flash and Image? many thanks, Alex i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Yocto Project Re: Create .wic file that contains signed flash.bin and Image Update: the issue was due to a malformed imx-boot file that caused the length field not to match the actual size of the bootloader. It has now been fixed however uuu still fails to flash the signed .wic to eMMC. It reaches 10% and then hangs, eventually erroring with HID(W): LIBUSB_ERROR_TIMEOUT (-7). Re: Create .wic file that contains signed flash.bin and Image Thank you, it seems that it is possible for me to replace the bootlader and kernel files in the deploy folder with their signed version (signed_flash.bin becomes imx-boot and Image_signed.bin becomes Image). However, the new .wic file works when burned on an SD card, but seems to have problems when using uuu. In` particular, even after adding the tag to the bootloader file, the uuu command errors with "This wic boot length is wrong". The command used to flash the new (signed) wic file to eMMC is: `uuu.exe -b emmc_all ` The output: uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.5.182-0-gda3cd53 Success 0 Failure 1 2:14-2016A80 1/ 1 [This wic boot length is wrong ] SDPS: boot -scanterm -f -scanlimited 0x800000 I was wondering if you knew what the cause of this error could be, before I dive into the mfgtools code to try reverse engineer it?  Many thanks, Alex Re: Create .wic file that contains signed flash.bin and Image Hello, The i.MX BSP package contains several root file systems. They are named with the following convention: [image name]-[backend]-[platform][board].[ext4|wic]. The ext4 extension indicates a standard file system. It can be mounted as NFS, or its contents can be stored on a boot media such as an SD/MMC card. Check the Linux user guide to how to burn and copy firmware with hab container: https://www.nxp.com/docs/en/user-guide/IMX_LINUX_USERS_GUIDE.pdf Regards

S32K3xx FlexCANレガシーおよび拡張RXFIFO DMA S32K344 FlexCANに取り組んでいますが、FlexCANの使用中にいくつか質問があります。 1. DMAは実際にS32K344でどのように機能し、どのように使用するのですか? 2. 従来の FIFO を DMA と統合し、拡張 FIFO を DMA と統合する方法 3. DMAの使用中に何か影響はありますか? Re: S32K3xx FlexCAN legacy and Enhanced RXFIFO DMA こんにちは、 この例のMCALバージョンを証明していただけますか?ありがとうございます。

SRAM 和 SDRAM 可以在一个设计中与 imxrt1062 接口 你好 我正在使用 IMXRT1062 控制器设计新产品。我已经与 SRAM 连接并验证它正在工作。我现在还计划与 SDRAM 接口，以便可以根据需要访问 SRAM 和 SDRAM。 是否可以使用 IMXRT1062 与 SRAM 和 SDRAM 连接？ i.MXRT 106x 回复：SRAM 和 SDRAM 可以在一个设计中与 imxrt1062 接口 你好@VishalAvg ， 感谢您对 NXP MIMXRT 系列的关注！ 是的，这可以通过 SEMC 来完成。SEMC 是一款针对高性能和低引脚数而优化的多标准存储器控制器。它可以通过共享地址和数据引脚在同一应用中支持多个外部存储器。支持的接口包括 SDRAM、NOR 闪存、SRAM、NAND 闪存和 8080 显示接口。 此致， 加文

How can I get a new S32DS_Power_Win32_v2017.R1 activation code? when I install the software,can't active it,the tip is :Error sending an activation request to a remote activation server and processing theresulting response. License can not be generated, it is already expired.How can I get a new activation code? Activation | Installation | Licensing | Installer Download Re: How can I get a new S32DS_Power_Win32_v2017.R1 activation code? Thank you Re: How can I get a new S32DS_Power_Win32_v2017.R1 activation code? Hi, Your S32DS for PA license has been extended. Please activate S32DS again with your old code. 

Download Safety Library for NXP Microcontroller Hi Everyone, I am trying to find the IEC60730 Safety Library for NXP MKE1xZ Series of Micro-controller. Earlier this was available as separate download, but recently as per the below mentioned link, this should be a part of the SDK Package. https://www.nxp.com/applications/enabling-technologies/functional-safety/iec-60730-safety-standard-for-household-appliances:APIEC60730 I downloaded the SDK version 2.16, but couldn't find it, can someone please help where can i find them? Freedom Development Platform Kinetis E Series MCUs Re: Download Safety Library for NXP Microcontroller Hi Thank you for your response. It's a bit confusing, if someone is working on MKE15Z, he/she will download the MKE15Z SDK, I hope in future version of SDK this is fixed and updated. Anyways thanks for your response, it helps alot. Re: Download Safety Library for NXP Microcontroller Hi, Thank you so much for your interest in our products and for using our community. For KE1xZ devices we have 4 evaluation boards: FRDM-KE15Z, FRDM-KE16Z, FRDM-KE17Z512 and FRDM-KE17Z. And just the FRDM-KE17Z512 has the IEC60730B Safety Library in the SDK version 2.16.000. However if you look for Middleware in MCUXpresso SDK Builder you can find all the SDKs that contains it. And for example, FRDM-KE15Z has this Middleware, but in SDK version 2.13.0: And apology for the confusion. And hope it helps you. Have a nice day!

Not able to mass erase/flash after running AN12255SW Flash Remap After running the example AN12255SW "Flash Remap Test" in MCUXpresso, I'm not able to reflash my RT106x. Also I'm not able to do a mass erase in order to reprogram again. I'm using an MCU-Link (LinkServer) debugger with MCUXpresso. Any attempt to program/mass erase shows that 0 SWD devices are connected, then I receive the following serial output when performing a mass erase: Executing flash operation 'Erase' (Erase flash) - Fri Jan 10 08:57:39 CST 2025 Checking MCU info... Scanning for targets... Executing flash action... MCUXpresso IDE RedlinkMulti Driver v11.10 (Jul 2 2024 19:33:51 - crt_emu_cm_redlink.exe build 741) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/.../workspace/flash_remap_test/Debug\MIMXRT1062xxxxA.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Connecting to probe 1 core 0 (using server started externally) reports: 'Ee(42). Could not connect to core.' Retrying... Reconnected to existing LinkServer process. Server OK but no connection to probe 1 core 0 (after 3 attempts) - Ee(42). Could not connect to core. ============= SCRIPT: RT1060_connect.scp ============= RT1060 Connect Script DpID = 0BD11477 Error: Wire Ack Fault - target connected? Error: Wire Ack Fault - target connected? Disabling MPU Error: Wire Ack Fault - target connected? Error: Wire Ack Fault - target connected? Configure FlexRAM for 768KB OC RAM, 128KB I-TCM, 128KB D-TCM Error: Wire Ack Fault - target connected? Error: Wire Ack Fault - target connected? Error: Wire Ack Fault - target connected? Finished ============= END SCRIPT ============================= Failed on connect: Ee(42). Could not connect to core. No connection to chip's debug port (100) Target Operation Failed Unable to perform operation! Command failed with exit code 1 I've encountered problems reflashing before, but usually this is solved by erasing the chip and then programming again.. is there a way to recover from this and test AN12255SW again? Thanks i.MXRT 106x Re: Not able to mass erase/flash after running AN12255SW Flash Remap Hi @schafbo  Thank you for letting us know! I am glad that you can keep developing.  Diego Re: Not able to mass erase/flash after running AN12255SW Flash Remap Nevermind, I see that LPUART1 is used. After setting the boot mode pins I was able to set the MCU into serial download, then reset and program again. Thanks! Re: Not able to mass erase/flash after running AN12255SW Flash Remap Diego, I'm not using an eval board, but the boot mode pins can be set to serial download with some effort. I am using the process outlined in the doc "Recover_RT1064". Is there a specific UART line on the MCU that I need to use, or it can work with any of them? Re: Not able to mass erase/flash after running AN12255SW Flash Remap Hi @schafbo  Have you tried an erase when the MCU is in serial  downloader mode? If SWD keeps failing, please try to do a recover using MCUXpresso Secure Provisionining Tool, this tool sends erase commands over UART/USB. Please let me know your results.  Diego 

Getting started with LPC1778FBD208 Hi Expert, Im using LPC1778FBD208 with 208 pin numbers. Im using pin 59 to blink LED. Currenlty using Keil IDE and managed to works on GD32 MCU. Can you guide me how to build in project for LPC in Keil. Im very appreciate if you can share me the full project sdk. I just need to open, build & flash. Im using CMSIS-DAP to flash the code. Thanks in advanced. Re: Getting started with LPC1778FBD208 Hi @aus_swsol  Sorry, we have reported the download issue to our website team and will resolve it as soon as possible so that you can download the resources. BR Harry Re: Getting started with LPC1778FBD208 Hi Harry, Kindly please attach KEIL project with example using LPC1778FBD208 CMSIS & standard library for me to get startup with. Thanks in advanced. Re: Getting started with LPC1778FBD208 Hi @aus_swsol  Sorry, our LPCopen official website has some issues, we will resolve this problem as soon as possible. https://github.com/openxc/nxp-cdl/tree/master This code is not officially maintained by us. So I still suggest that you import keil examples from LPCopen. BR Harry Re: Getting started with LPC1778FBD208 *additional reply other problem:- 1) the LED to blink also was wrong. below is my code, but the LED that blink is at P2[27] which is pin 47. i want to blink led at P2[18] which is pin 59. 2) i need to enter debug mode, run debug mode. then  exit the debug mode to make it run. why? if i reset power, the board doesnt blink pin 47. thanks in advanced Re: Getting started with LPC1778FBD208 Hi Harry, This is what happened when I clicked Can you please provide me the latest stable SDK with example for LPC1778FBD208? Im using Keil. currently my solution is using the library from this github. Im not sure this is official stable version or not. https://github.com/openxc/nxp-cdl/tree/master Lib I used was from these two folder and managed to blink the LED. CMSISv2p00_LPC177x_8x LPC177x_8xLib However, I need a full example for these library to fast plot my project. Thanks in advanced Re: Getting started with LPC1778FBD208 Hi @aus_swsol  You can access to the NXP lpcopen website LPCOpen Software for LPC17XX | NXP Semiconductors And download the lpc1788 Keil packet. You can modify the project according to your needs based on this Keil project. BR Harry

i.MX93 Linux OCRAMを共有メモリとして こんにちは 私はimx93、非セキュアで作業しています。 これが私の問題です:私はlinux a55とm33の間の共有メモリとしてocramを使用したいと思います。 私はLinuxユーザースペーステストプログラムとm33テストプログラムの両方を持っていますが、どちらもocramにアクセスできますが、最初の96KB(20480000 - 20497ff)だけです。もっと手に入れることはできますか?フル640KB? Linux テストプログラムは 0x20480000 で mmap を使用します。バスが0x20498000以上になるとバスエラーが発生します。 注:私はetosuやrpmsgをまったく使用しません。 Linuxはocramをどのように使用しますか?96KBを640KBに増やすことはできますか? 感謝 クリス

i.MX93 Linux OCRAM as shared memory Hello I'm working with an imx93, non-secure. Here's my problem: I want to use ocram as shared memory between the linux a55 and the m33. I have a linux user space test program and an m33 test program that can both access the ocram, but only the first 96KB (20480000 - 20497fff). Can I get more of it? The full 640KB? The linux test program uses mmap at 0x20480000. It gives a bus error if it goes at or above 0x20498000. Note: I won't be using the ethosu or rpmsg at all. How does linux use ocram? Can I increase the 96KB to 640KB? Thanks Chris Re: i.MX93 Linux OCRAM as shared memory Hi You can try to modify ocram permission settings in ATF:plat/imx/imx93/trdc_config.h Add more memory blocks in trdc_n_mbc, 0-5 means six memory blocks(6*16KB=96KB), you need add more. Best Regards Zhiming

RTM Date of FRDM-IMX93 Hi IMX93 Champ  Can you please let us know when the FRMD-IMX93 evk would be available from the market?  Let us know RTM date of FRDM-IMX93. Customers are ready for placing order. Thanks. Regards,  JK Re: RTM Date of FRDM-IMX93 Thanks a lot for your kind answer. Re: RTM Date of FRDM-IMX93 Hi @JK_Cha  You can order this board from below link now FRDM i.MX 93 Development Board | NXP Semiconductors Regards Daniel

S32G3 GMAC0 and PFE_MAC1 SGMII mode Hello, If I configure GMAC0 and PFE_MAC1 to use SGMII (1G), does that mean both interfaces will utilize SerDes pins for external communication, allowing their respective dedicated pins (e.g., gmac_tx0, gmac_tx1, etc.) to be reassigned to other interfaces? Additionally, if GMAC0 is configured for SGMII, can I still use the GMAC_PPS pin for PPS output? Similarly, if PFE_MAC1 is set to SGMII, can I still connect its PPS pin to another module? Thanks, XD Re: S32G3 GMAC0 and PFE_MAC1 SGMII mode Thank you for the explanation, Celeste! Thanks, XD  Re: S32G3 GMAC0 and PFE_MAC1 SGMII mode Hi @XD , Thank you for your answer. As per your questions: [Q1]: If I configure GMAC0 and PFE_MAC1 to use SGMII (1G), does that mean both interfaces will utilize SerDes pins for external communication, allowing their respective dedicated pins (e.g., gmac_tx0, gmac_tx1, etc.) to be reassigned to other interfaces? [A1]:Given that you are designing a customized board, I recommend you refer to the document "User guide S32G3 Hardware Design Guidelines". S32G3 has two SerDes instances, each SerDes instance has a mux option between PCIe and SGMII. The following mux option can be chosen on the SerDes channels. In addition, I have checked the S32G3 IOMUX Sheet. Regarding your question, I believe it is correct. [Q2]: Additionally, if GMAC0 is configured for SGMII, can I still use the GMAC_PPS pin for PPS output? Similarly, if PFE_MAC1 is set to SGMII, can I still connect its PPS pin to another module? [A2]: Likewise, the answer is yes. For more details, you can refer to Chapter 53 SerDes Subsystem of the S32G3 Reference Manual. The S32G3 SerDes Subsystem Reference Manual is also recommended. I hope the above answers can solve your confusion. Best regards, Celeste Re: S32G3 GMAC0 and PFE_MAC1 SGMII mode Hi Celeste, Thank you for your response. We are designing our own board, using the RDB3 reference design as a reference. Our plan is to configure both GMAC0 and PFE_MAC1 to operate in SGMII mode. Thanks, XD Re: S32G3 GMAC0 and PFE_MAC1 SGMII mode Dear @XD , I apologize for the late response. I would like to know whether you are using the reference board or a customized board. The answers to your questions may vary depending on this. Best regards, Celeste