ADC High Speed Configuration Issue on K312 ( RTD 2.0.1) Hello NXP Team, Due to specific reasons, we are still using RTD version ‌2.0.1‌ for our project on the K312。 I noticed discrepancies regarding the ‌ADC Clock configuration for highest conversion speeds‌ between the User Manuals from ‌2022‌ and ‌2025‌. I have two specific questions regarding this: For the ‌HSEN bit‌ in the ‌AMSIO register‌, which value should I set to enable High Speed mode in our RTD 2.0.1 context? Should it be set to ‌1‌ or ‌3‌? The 2022 manual does not describe or provide configuration guidance for the ‌CMPCTRL0‌ bit. Do I need to explicitly configure the ‌CMPCTRL0 bit‌ to achieve the highest conversion speeds using High Speed ADC mode? If configuration is necessary, would it be sufficient to modify the Adc_Sar_EnableHighSpeed() function accordingly? Thank you for your support! Re: ADC High Speed Configuration Issue on K312 ( RTD 2.0.1) Dear Pavel, Thank you for your support. That has resolved my question. Best regards, Jianjie Re: ADC High Speed Configuration Issue on K312 ( RTD 2.0.1) Hello @jianjie , I have received feedback from our application team. The ADC clock configuration has evolved over time and both settings are valid. That said, we do not recommend modifying the RTD driver manually. To ensure correct behavior and compatibility, it is always advised to use the latest available RTD package, which incorporates the most up-to-date configuration logic. Best regards, Pavel Re: ADC High Speed Configuration Issue on K312 ( RTD 2.0.1) Hello @jianjie , Thank you for your interesting query and for sharing your observations regarding the ADC AMSIO HSEN configuration. I have reviewed your comments and can confirm the discrepancies you noted between the different versions of the Reference Manual. Please be informed that your query is currently being investigated internally. I will keep you updated as soon as further information becomes available. Thank you for your patience and understanding. Best regards, Pavel

MIMXRT1176DVMAA - Not detecting over the JTAG Hi Team We developed a custom board based on MIMXRT1176DVMAA, and unfortunately,  device could not detecting over the JTAG. During my troubleshooting, I found that internal LDO output "VDDA_1P0" (Pin N11) is not showing voltage (0V) and this output connected to VDD_MIPI_1P0 (Pin F10) DSI lines interface. Could this be a problem preventing the device detecting over JTAG? Verified the PMIC power sequence, all voltage rails sequence is as per the datasheet recommended. Thanks. Regards, Gopala Re: MIMXRT1176DVMAA - Not detecting over the JTAG Hi @gopalakrishna ， Thank you so much for your interest in our products and for using our community. Regarding "During my troubleshooting, I found that internal LDO output "VDDA_1P0" (Pin N11) is not showing voltage (0V) and this output connected to VDD_MIPI_1P0 (Pin F10) DSI lines interface." Could you provide more detailed information? Have you followed the design of the MIMXRT1170-EVKB board? https://www.nxp.com/webapp/Download?colCode=MIMXRT1170HDUG Please refer to the user guider "Hardware Development Guide for the MIMXRT1160/1170 Processor" particularly Chapter 3 "Power Supply," to confirm whether your board design complies with the requirements outlined in Table 1 "Processor Power Supply Capacitors When Using On-Chip DC-DC Regulators." Did you add 1 ms R/C delay , DCDC_PSWITCH should delay 1 ms with respect to DCDC_IN to guarantee that DCDC_IN is stable before the DC-DC starts up. Please use an oscilloscope to measure the power-up sequence of the RT1170. Best Regards MayLiu

K312 上的 ADC 高速配置问题（RTD 2.0.1） 您好，NXP团队， 由于特殊原因，我们在 K312 上的项目仍在使用 RTD2.0.1版。 我注意到2022和2025用户手册中关于最高转换速度的 ADC 时钟配置存在差异。 对此，我有两个具体问题： 对于AMSIO 寄存器中的HSEN 位，我应该设置哪个值才能在 RTD 2.0.1 环境中启用高速模式？应该设置为1还是3？ 2022 手册未对CMPCTRL0位进行描述或提供配置指导。是否需要明确配置CMPCTRL0 位，才能使用高速 ADC 模式实现最高转换速度？如果需要配置，是否只需相应修改 Adc_Sar_EnableHighSpeed() 函数即可？ 感谢您的支持！ Re: ADC High Speed Configuration Issue on K312 ( RTD 2.0.1) 亲爱的帕维尔 感谢您的支持。这就解决了我的问题。 顺祝商祺！ 建杰 Re: ADC High Speed Configuration Issue on K312 ( RTD 2.0.1) 你好@jianjie、 我已收到我们申请团队的反馈意见。随着时间的推移，ADC 时钟配置已发生变化，两种设置均有效。 不过，我们不建议手动修改 RTD 驱动程序。为确保正确的行为和兼容性，始终建议使用最新的可用RTD代码包，该代码包包含最新的配置逻辑。 顺祝商祺！ 帕维尔 Re: ADC High Speed Configuration Issue on K312 ( RTD 2.0.1) 你好@jianjie、 感谢您提出有趣的问题，并分享了您对 ADC AMSIO HSEN 配置的看法。 我已经查看了你的评论，可以确认你注意到的不同版本的参考手册之间的差异。请注意，您的问题目前正在内部调查。一旦有进一步的信息，我将及时向你们通报。 感谢您的耐心和理解。 顺祝商祺！ 帕维尔

K312 上的 ADC 高速配置问题（RTD 2.0.1） 您好，NXP团队， 由于特殊原因，我们在 K312 上的项目仍在使用 RTD2.0.1版。 我注意到2022和2025用户手册中关于最高转换速度的 ADC 时钟配置存在差异。 对此，我有两个具体问题： 对于AMSIO 寄存器中的HSEN 位，我应该设置哪个值才能在 RTD 2.0.1 环境中启用高速模式？应该设置为1还是3？ 2022 手册未对CMPCTRL0位进行描述或提供配置指导。是否需要明确配置CMPCTRL0 位，才能使用高速 ADC 模式实现最高转换速度？如果需要配置，是否只需相应修改 Adc_Sar_EnableHighSpeed() 函数即可？ 感谢您的支持！ Re: ADC High Speed Configuration Issue on K312 ( RTD 2.0.1) 亲爱的帕维尔 感谢您的支持。这就解决了我的问题。 顺祝商祺！ 建杰 Re: ADC High Speed Configuration Issue on K312 ( RTD 2.0.1) 你好@jianjie、 我已收到我们申请团队的反馈意见。随着时间的推移，ADC 时钟配置已发生变化，两种设置均有效。 不过，我们不建议手动修改 RTD 驱动程序。为确保正确的行为和兼容性，始终建议使用最新的可用RTD代码包，该代码包包含最新的配置逻辑。 顺祝商祺！ 帕维尔 Re: ADC High Speed Configuration Issue on K312 ( RTD 2.0.1) 你好@jianjie、 感谢您提出有趣的问题，并分享了您对 ADC AMSIO HSEN 配置的看法。 我已经查看了你的评论，可以确认你注意到的不同版本的参考手册之间的差异。请注意，您的问题目前正在内部调查。一旦有进一步的信息，我将及时向你们通报。 感谢您的耐心和理解。 顺祝商祺！ 帕维尔

Edgelock2Go Is the S32K311 an Edgelock 2Go enabled device? Re: Edgelock2Go Hi https://www.nxp.com/products/security-and-authentication/authentication/edgelock-2go:EDGELOCK-2GO S32K3 is not listed in Supported Products.   I consulted with my EdgeLock 2GO colleague, who told me: this is the plan but I don't have a date for it yet. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: Edgelock2Go If you need EdgeLock 2GO support today, you’d typically look at devices that already have integration with the EdgeLock 2GO platform (such as secure elements like the SE05x family or certain wireless MCUs and processors that explicitly appear in the supported list on NXP’s website)    

LS1048ardb SERDES 匹配 DPL 文件 你好 我是恩智浦 Layerscape 硬件的新手，正在使用 LS1048ardb 平台。我想提一下 DPMAC2 以太网设备（我认为这是基本以太网的普遍用法 “eth0”），但是通过阅读恩智浦论坛的各种帖子，我需要一个与 SERDES 相匹配的 DPL 文件。如果没有 DPL 文件，我就会得到预期的 uboot 错误： "fsl-mc：DPL 未部署，DPAA2 以太网不工作" 我在恩智浦论坛上找到了几个生成 "空 "DPL 文件的帖子，使用该 dtb 后，我得到了这个错误： "fsl-mc：部署数据路径布局 ...警告：固件返回错误 (GSR: 0x3f)" 在恩智浦技术支持论坛的一些回复中（针对 ls1088ardb），我通过提供 SERDES 值，恩智浦工程师可以生成一个适当的 DPL 文件。 以下是我从 mii/mdio 和 SERDES 值中收集到的一些信息，希望对您有所帮助： = > mii 设备 MI I 设备：'FSL_MDIO0' '' FSL_MDIO1 ' 当前设备：' FSL_MDIO0 '= > mii 信息 PHY 0x01：OUI = 0x80028，型号 = 0x23，Rev = 0x01，1000BaseT，FDX => mdio 列表 FSL_MDIO0： 1 - TI DP83867<--> DPMAC2@sgmii FSL_MDIO1： 看似相关的Uboot启动数据： 使用 SERDES1 协议：18 (0x12) 使用 SERDES2 协议：13 (0xd) 网：DPMAC2@sgmii [PRIME] fsl-mc：启动管理复杂...成功 fsl-mc：管理综合体已启动（版本：10.12.0，启动状态：0x1）启用 1000BT 全双工/半双工广告 若能得到任何帮助，我将不胜感激。 Re: LS1048ardb SERDES Matched DPL File 您好@brian-wood 感谢您分享您的发现，您已经在 DTS 中添加了下一项，对吗？ >>> &davinci_mdio { phy0：ethernet-phy@0 { //PHY0已定义并传给 phy-handle reg =<0>; ti,rx-internal-delay = ； ti,fifo-depth = ; }; }; & cpsw_port1 { phy-mode ="rgmii-rxid" ； phy-handle =<& phy0>; }; < < < " 我想这与 FSL MC 如何创建网络有关）" 其实不然，它与以太网内存映射有关，但我们无法修改。 遗憾的是，没有一种简单的方法，8( ，你可以省略 DPL，但这不是一个好主意，因为 DPL 的目的不是描述硬件属性，而是描述 MC 应创建的逻辑对象的初始拓扑结构和属性。 BR LFGP Re: LS1048ardb SERDES Matched DPL File 你好，LFGP、 我想感谢您在解决这个问题时提供的建议。我发现了问题；我们使用的是 TI83867 phy，我需要将 “ ti，fifo-depth = < DP83867_PHYCR_FIFO _DEPTH_4_B_NIB >;” 添加到我的 ph y 设备树节点。我现在有以太网了，但还有一个后续问题。 一切就绪后，我看到了一个 "eth0"，但同时也看到了一个 "mac2"（我想这与 FSL MC 的联网方式有关）。是否有一种简单的配置更改方法，可以让一切都变成 "eth0"？还是只有 "Mac2"？ 我没有修改 DPC 文件的权限，所以如果我可以修改 DPL 文件或其他文件，那将会很有帮助。 感谢您的帮助。 Re: LS1048ardb SERDES Matched DPL File 亲爱的@brian-wood, 'PHYAD:0" 意味着 PHY 没有被识别。 请使用下一个链接查看 LS1088 RDB 的 DTS 和 DTSi。 https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 还请 AN5125 介绍 DTS https://www.nxp.com/docs/en/application-note/AN5125.pdf 如果你的自定义板使用 SERDES 来获取 SGMII 或 RGMII，而没有外部 PHY，那么你的 DTS 将使用 PCS 节点来设置 macX Re: LS1048ardb SERDES Matched DPL File 你好，LFGP、 我决定试试我的 DPL 文件，同时将上游 6.14 Linux 内核切换到与 LSDK1812（几年前他们建立这个平台时使用的）相匹配的恩智浦 4.14 内核，这样我就能在 eth0 上调用 DPMAC2 了。 🙂 但我遇到了一个问题，FSL 管理综合体似乎将 eth0 连接到了 PHY 0，而不是 PHY 1（我相信我在 DTS 中的设置是正确的）。作为一项健全性检查（因为我对使用设备树还很陌生），我使用 PHY 1 的所有设置是否正确： &emdio1 { status ="okay" ； mcp_debug_phy： emdio1_phy@1 { 兼容 ="ethernet-phy-ieee802.3-c22" ； 中断 =<0 2 0x4> ； reg =<0x1> ； phy-connection-type ="sgmii" ； }; }; &dpmac2 { phy-handle =<& mcp_debug_phy> ； phy-connection-type ="sgmii" ； }; 但当我给 eth0 分配了一个 IP 地址后尝试 "ping "时，却没有出现任何错误或 rx/tx 计数增加（使用 ifconfig 进行检查）。当我使用 "ethtool eth0 "时，发现它显示连接到 PHYAD 0： # ethtool eth0 eth0 的设置： 支持的端口：[ ] 支持的链接模式：未报告 支持暂停帧使用：无 支持自动协商：不支持 支持 FEC 模式：未报告 广告链接模式：未报告 广告暂停帧使用：无 广告支持自动协商：无 广告支持的 FEC 模式：未报告 速度：未知！ 双工： 端口：双绞线 PHYAD：0 收发器：内部 自动协商：关闭 MDI-X：Unknown Link detected: no # 我没有更改 "fsl-ls1088a.dtsi "的默认设置、但如果希望使用 PHY 1，这样做对吗？ /* TODO: WRIOP (CCSR?) */ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, * E-MDIO1: 0x1_6000*/ compatible ="fsl,fman-memac-mdio"; reg =<0x0 0x8B96000 0x0 0x1000>; device_type ="mdio"; little-endian; /* 强制驱动程序进入 LE 模式 */ /* 在 QDS 上不需要，但在 RDB 上需要 */ #address-cells =<1>; #size-cells =<0> ； }; DPL 中是否有什么需要调整的地方，以便连接正确的 PHY？ 非常感谢你们的帮助。 Re: LS1048ardb SERDES Matched DPL File 亲爱的@brian-wood，希望这条信息能让你感觉良好。 我需要澄清一下你的自定义板。 你在定制板中使用 LS1048A 吗？或者你正在使用的 Layerscape 设备是什么？ 您的设计是基于 LS1048ARDB 吗？恩智浦没有 LS1048ARDB。 另一方面，您可以在 DPAA 参考手册中找到 DPL 设置。 BR LFGP Re: LS1048ardb SERDES Matched DPL File 嗨，LFGP， 快速检查一下，这个 ls1048ardb 平台使用的是 2018.09 版本的 uboot 和 10.12.0 版本的 fsl_mc，我可以在这个平台上使用 6.14 Linux 内核吗？我想知道，我在使用 FSL 管理综合体调用 DPL 节点时遇到的恩智浦/FSL 内核驱动程序错误是否是由于 fsl_mc 支持的内容不匹配（并导致 mc_send_command() "不支持的操作 "失败）？ 我已经阅读了前面提到的文档链接，但无法链接到eth0，因为我处于部分状态（由于在Linux内核启动期间启用 DPL 文件时出现 “不支持的操作” 失败）。启动后运行 “ls-listni、restool 等...” 时，我确实看到了同样的 “不支持的操作”，这使我觉得我的 fsl_mc、restool 和 Linux 内核 6.14 版本不匹配。 下面是更多的 uboot 信息，希望对您有所帮助： U-Boot 2018.09 gpu_bl_01Feb2021 tf/cpsw-15234-bl-u-boot a996f0a3（2021 年 2 月 1 日-18:04:24 -0700） SoC：LS1048A Rev1.0 (0x87032110) 时钟配置：CPU0 (A53): 1200 MHz CPU1 (A53): 120 0 MHz CPU2 (A53): 1200 MHz CPU3 (A53): 1200 MHz 总线：500 MHz DDR：1600 MHz RESET 配置字 (RCW)：00000000： 30004014 00000030 00000000 000030 00000000 000010：00000000 0000 0000 0020000 0020000 00000000 000020：02e12980 00000080 00000000 0000000 00000030：00fff054 00000000 00000000 00000000 00000040： 00000000 00000000 0000000 00000040：00000000 00000000 00009：00000000 0000000 00000000 000070：33330002 00009555 I2C：就绪 动态随机存取存储器(DRAM)：根据训练值初始化 DDR 控制器 内存初始化正常，检查 ERR_D ETECT 寄存器后在 DDRC 上没有错误 ERR_DETECT=0 3.9 GiB DDR 3.9 GiB（DDR4，64 位，CL=12，ECC 开 启） 警告：请在 cpo_sample = 0x4b board >/ ddr.c 将优化 cpo **boot_all_cores env var=true... 继续唤醒二级内核从 fbd4b000 开始 所有 (4) 个内核都已启动。 使用 SERDES1 协议：18 (0x12) 使用 SERDES2 协议：13 (0xd) MMC: FSL_SDHC: 0 从闪存加载环境...OK In: serial Out: serial Err: serial Model：Boeing Dual MCP Green V0.2_1 (NXP Layerscape 1048a) Net：DPMAC2@sgmii [PRIME] Warning：DPMAC2@sgmii (eth0) using random MAC address - 16:af:d1:f3:8a:cf crc32+ fsl-mc：启动管理复杂程序...成功 fsl-mc：管理综合体已启动（版本：10.12.0，启动状态：0x1） 启用 1000BT 全双工/半双工广告按任意键停止自动启动：0 Re: LS1048ardb SERDES Matched DPL File 亲爱的@brian-wood、 LS1088A 和 LS1048A 添加新 DPNI 的程序相同，请查看我上一篇文章中的链接。 Re: LS1048ardb SERDES Matched DPL File 感谢你的回复，我已经通读了恩智浦关于这款基于LS1048ardB的定制板的许多文档（我猜有四个GPP内核与LS1088ardB略有不同）。这是一个大约 5 年前开发的平台，我继承了它并将其用于简单的 dpmac2 以太网概念验证。 我添加了一些驱动程序调试代码，可以看到这些 dmesg（从最后一次成功的 fsl_mc 调用到 "不支持的操作 "故障），并认为可能是我的 DPL 文件中的某些设置不正确导致了故障（见所附 DPL dts）： [ 14.200954] FSL_MC_DPRC DPRC.1：BJW：（mc_send_command）FSL MC 响应：0，状态：命令成功完成 (0x0) [ 14.211772] FSL_MC_DPRC DPRC.1：BJW：（dpni_set_pools）FSL MC 调用 mc_send_command() [ 14.226219] fsl_mc_dprc dprc.1：BJW：（mc_send_command）FSL MC 响应：0，状态：不支持的操作 (0xb) [ 14.236254] FSL_DPAA2_ETH DPNI.1：dpni_set_pools() 失败 [ 14.241672] fsl_dpaa2_eth dpni.1：BJW：（dpaa2_eth_bind_dpni）错误：-524 我的 DPL 文件是根据我从恩智浦文档（如https://docs.nxp.com/bundle/GUID-487B2E69-BB19-42CB-AC38-7EF18C0FE3AE/page/GUID-C254A494-0853-4C94-8AD0-7D9C2739B5D3.html）中看到和读到的示例编写的。 我不太确定我可能需要提供哪些信息来帮助根本原因出现 DPMAC2 @sgmii 以太网问题（我能够启动这个平台并使用以太网进行 uboot/tftp），但无法在 Linux 中启动并运行。因此，如果还需要其他信息，我很乐意提供。 Re: LS1048ardb SERDES Matched DPL File 亲爱的@brian-wood， 我想你是指 LS1088ARDB， 如果你想配置 DPMAC2，请按照下一个链接中显示的步骤进行 https://community.nxp.com/t5/Layerscape-Knowledge-Base/LS1088ARDB-LS1088ARDB-PB-How-to-create-a-DPAA2-network-interface/ta-p/1128669

FLEXSPI two channel I deploy an application with imxRT1062 with 2 Flash device. One connected to FLEXSpiA port A1 (is used to code storage and running) and the second to FLEXSpiB port B1 (data storage). I have follow this topic https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-2nd-flexSPI-not-boot-device-to-store-NVM-data/m-p/1284876 and I change this define: #define EXAMPLE_FLEXSPI FLEXSPI2 #define FLASH_SIZE 0x400000 /* 32Mb/4MByte */ #define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI2_AMBA_BASE #define FLASH_PAGE_SIZE 256 #define EXAMPLE_SECTOR 20 #define SECTOR_SIZE 0x1000 /* 4K */ #define EXAMPLE_FLEXSPI_CLOCK kCLOCK_FlexSpi2 #define FLASH_PORT kFLEXSPI_PortB1 #define EXAMPLE_FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackFromDqsPad I can't read and write data to portB1. I use eaimxrt1062_flexspi_nor_polling_transfer example with this config: Nothing signal (DATA, SCK, CS) active. I've checked the correct pin configuration.  Is it possible use two FLEXSPI at same time? Re: FLEXSPI two channel Hi @Maurizio2 , Thank you so much for your interest in our products and for using our community. Question: Is it possible use two FLEXSPI at same time? Answer: Yes, it is possible. Please refer to the following link,  this application note is highly relevant to your needs. https://www.nxp.com/docs/en/application-note/AN12564.pdf Please carefully check the pin and clock configuration of flexspi, as well as the settings of the LUT table. Wish it helps you. If you still have question about it, please kindly let me know. Best Regards MayLiu

MPC5746Cのフラッシュメモリアレイの整合性チェック こんにちは、 MPC5746C のフラッシュ メモリ アレイの整合性チェックに取り組んでいます。 MPC5746C リファレンス マニュアルに記載されている手順に基づいて関数を作成しました。この機能を実行すると、継続的なリセットが行われます。 手順に基づいて、以下のコードが記述されます。そして、while ループ内で継続的にリセットを行っています。しかし、ブレークポイントを維持し、ステップごとに実行すれば、動作します。 一度ご確認いただき、フィードバックや解決策をご提供いただけますでしょうか。 静的void WaitForAIDBitSet(uint32_t タイムアウト) { 揮発性 int 遅延; (遅延 = 0; 遅延 < 1000; 遅延++) の場合 { __asm__ volatile ("nop"); } while ((C55FMC.UT0.B.AID == 0) && (タイムアウト > 0U)) { タイムアウト - ; } } uint8 フラッシュメモリ整合性テスト(void) { uint32_t misr_result[10]; /* ウォッチドッグを無効にする */ Wdg_modeSwitchInt(FALSE); /* ステップ 1: UTest モードに入る */ C55FMC_UT0 = 0xF9F99999; /* ステップ2: ECC設定 - ECCエラー報告を無効にする */ C55FMC.MCR.B.EER = 0; // ECCイベント情報 C55FMC.MCR.B.SBC = 0; // シングルビット訂正 /* ステップ3: PFLASHの読み取り動作を構成する */ PFLASH.PFCR1.B.RWSC = 0x04; // 待機状態 PFLASH.PFCR1.B.APC = 0x01; // プリフェッチ有効 /* ステップ4: SELx経由でテストするフラッシュブロックを選択する */ C55FMC.SEL0.R = 0x00FF0FFC; C55FMC.SEL1.R = 0x00000000; C55FMC.SEL2.R = 0x00000000; C55FMC.SEL3.R = 0x00000000; /* ステップ5: シーケンシャルアドレッシングを使用する */ C55FMC.UT0.B.AIS = 1; /* ステップ 6: MISR レジスタをシードする */ C55FMC_UM0 = MISR_SEED; C55FMC_UM1 = MISR_SEED; C55FMC_UM2 = MISR_SEED; C55FMC_UM3 = MISR_SEED; C55FMC_UM4 = MISR_SEED; C55FMC_UM5 = MISR_SEED; C55FMC_UM6 = MISR_SEED; C55FMC_UM7 = MISR_SEED; C55FMC_UM8 = MISR_SEED; C55FMC_UM9 = MISR_SEED; /* ステップ7: 配列整合性操作を開始する */ C55FMC.UT0.B.AIE = 1; /* ステップ8: AID = 1（操作完了）を待機します */ WaitForAIDBitSet(0xFFFFFF); // タイムアウト制限を追加する /* ステップ9: MISR値を読み戻す */ misr_result[0] = C55FMC_UM0; misr_result[1] = C55FMC_UM1; misr_result[2] = C55FMC_UM2; misr_result[3] = C55FMC_UM3; misr_result[4] = C55FMC_UM4; misr_result[5] = C55FMC_UM5; misr_result[6] = C55FMC_UM6; misr_result[7] = C55FMC_UM7; misr_result[8] = C55FMC_UM8; misr_result[9] = C55FMC_UM9; /* ステップ10: AIEをクリアする */ C55FMC.UT0.B.AIE = 0; /* ステップ11: 必要に応じてウォッチドッグを有効にする */ Wdg_modeSwitchInt(TRUE); /* ステップ12: MISRの結果を比較する */ if ((misr_result[0] == MISR_UM0) && (misr_result[1] == MISR_UM1) && (misr_result[2] == MISR_UM2) && (misr_result[3] == MISR_UM3) && (misr_result[4] == MISR_UM4) && (misr_result[5] == MISR_UM5) && (misr_result[6] == MISR_UM6) && (misr_result[7] == MISR_UM7) && (misr_result[8] == MISR_UM8) && (misr_result[9] == MISR_UM9)) { FLS_SAFE_STATE_INACTIVE を返します。 } それ以外 { return FLS_SAFE_STATE_ACTIVE; // 整合性チェックに失敗しました } } Re: Flash memory array integrity check on MPC5746C こんにちは、 この関数は、フラッシュ ブロックの実際の MISR 値と output.txt の予想値を比較します。 MISR ツールをセットアップするには、詳細な readme.txt とフォルダーの開始アドレスの例を参照してください。 完全なツールを添付します。Web サンプルでは一部の doc/example ファイルが欠落しているようです。 これで疑問がすべて解消されることを願っています。 よろしくお願いいたします。 ピーター Re: Flash memory array integrity check on MPC5746C ツールがどのようにして期待されるゴールデン署名を計算するのか理解できませんでした。 予想される署名を計算する手順を教えてください。そして、例にあるツールはどのように機能しますか? Re: Flash memory array integrity check on MPC5746C こんにちは、 もう一つの質問があります。計算された MISR 署名値をどのように CAN 検証できるのでしょうか?つまり、取得した署名が正しいかどうかをどのように判断CANのでしょうか? 検証戦略の概要 既知のメモリ領域 (テスト配列など) の MISR シグネチャを計算します。 結果を事前に計算された参照署名 (ゴールデン値) と比較します。 値が一致する場合、メモリの内容は有効であると見なされます。 配列の整合性チェックを完了するために、MISR 署名値を計算して検証するサンプル コードを共有していただけますか? #include "MPC5746C.h" // Replace with actual header for your environment #define ARRAY_SIZE 256 #define CRC_BASE_ADDRESS 0xFF000000 // Replace with actual CRC module base address uint32_t test_array[ARRAY_SIZE] = { /* Fill with known values */ }; uint32_t expected_signature = 0x12345678; // Replace with your golden MISR value void init_crc_module(void) { // Enable CRC module clock // Configure CRC settings (polynomial, seed, etc.) // This is platform-specific and may require register-level access } uint32_t calculate_misr_signature(uint32_t *data, uint32_t size) { volatile uint32_t *crc_data_reg = (uint32_t *)(CRC_BASE_ADDRESS + 0x04); // Data input register volatile uint32_t *crc_result_reg = (uint32_t *)(CRC_BASE_ADDRESS + 0x10); // Result register for (uint32_t i = 0; i < size; i++) { *crc_data_reg = data[i]; } return *crc_result_reg; } int main(void) { init_crc_module(); uint32_t signature = calculate_misr_signature(test_array, ARRAY_SIZE); if (signature == expected_signature) { // Signature matches // Memory integrity is validated } else { // Signature mismatch // Possible memory corruption } return 0; } この例を見てください。これは同じ C55 フラッシュ モジュールのものです。 https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5744P-FlashArrayIntegrityCheck-test-SSD-GHS614/ta-p/1099524 よろしくお願いいたします。 ピーター Re: Flash memory array integrity check on MPC5746C マシン チェック例外のためリセットが発生しています。 もう一つの質問があります。計算された MISR 署名値をどのように CAN 検証できるのでしょうか?つまり、取得した署名が正しいかどうかをどのように判断 CAN ますか? 配列の整合性チェックを完了するために、MISR 署名値を計算して検証するサンプル コードを共有していただけますか? Re: Flash memory array integrity check on MPC5746C こんにちは、 デバッグ モードではリセットは発生しないため、この問題は何らかのタイマーによって発生していると想定されます。デバッガーによって無効化される SWT と同様。 リセット理由は、RGM [FES/DES] レジスタから読み取ることがCANます。 よろしくお願いいたします。 ピーター

Flash memory array integrity check on MPC5746C Hello,  We are working on checking the flash memory array integrity check on MPC5746C. Based on the steps mentioned in the MPC5746C reference manual we have written the function. When execute this function, continuous reset is happening. Besed on the steps, below code is written. And it is giving continuous reset in while loop. But if I keep breakpoints and go step by step it is working. Could you check once and provide your feedback or solution? static void WaitForAIDBitSet(uint32_t timeout) { volatile int delay; for (delay = 0; delay < 1000; delay++) { __asm__ volatile ("nop"); } while ((C55FMC.UT0.B.AID == 0) && (timeout > 0U)) { timeout--; } } uint8 Flash_Memory_Integrity_Test(void) { uint32_t misr_result[10]; /* Disable watchdog */ Wdg_modeSwitchInt(FALSE); /* Step 1: Enter UTest Mode */ C55FMC_UT0 = 0xF9F99999; /* Step 2: ECC Config - Disable ECC error reporting */ C55FMC.MCR.B.EER = 0; // ECC Event Reporting C55FMC.MCR.B.SBC = 0; // Single Bit Correction /* Step 3: Configure PFLASH read behavior */ PFLASH.PFCR1.B.RWSC = 0x04; // Wait States PFLASH.PFCR1.B.APC = 0x01; // Prefetch Enable /* Step 4: Select flash blocks to test via SELx */ C55FMC.SEL0.R = 0x00FF0FFC;  C55FMC.SEL1.R = 0x00000000; C55FMC.SEL2.R = 0x00000000; C55FMC.SEL3.R = 0x00000000; /* Step 5: Use sequential addressing */ C55FMC.UT0.B.AIS = 1; /* Step 6: Seed the MISR registers */ C55FMC_UM0 = MISR_SEED; C55FMC_UM1 = MISR_SEED; C55FMC_UM2 = MISR_SEED; C55FMC_UM3 = MISR_SEED; C55FMC_UM4 = MISR_SEED; C55FMC_UM5 = MISR_SEED; C55FMC_UM6 = MISR_SEED; C55FMC_UM7 = MISR_SEED; C55FMC_UM8 = MISR_SEED; C55FMC_UM9 = MISR_SEED; /* Step 7: Start Array Integrity Operation */ C55FMC.UT0.B.AIE = 1; /* Step 8: Wait for AID = 1 (operation complete) */ WaitForAIDBitSet(0xFFFFFF); // Add a timeout limit /* Step 9: Read back MISR values */ misr_result[0] = C55FMC_UM0; misr_result[1] = C55FMC_UM1; misr_result[2] = C55FMC_UM2; misr_result[3] = C55FMC_UM3; misr_result[4] = C55FMC_UM4; misr_result[5] = C55FMC_UM5; misr_result[6] = C55FMC_UM6; misr_result[7] = C55FMC_UM7; misr_result[8] = C55FMC_UM8; misr_result[9] = C55FMC_UM9; /* Step 10: Clear AIE */ C55FMC.UT0.B.AIE = 0; /* Step 11: Enable watchdog back if needed */ Wdg_modeSwitchInt(TRUE); /* Step 12: Compare MISR results */ if ((misr_result[0] == MISR_UM0) && (misr_result[1] == MISR_UM1) && (misr_result[2] == MISR_UM2) && (misr_result[3] == MISR_UM3) && (misr_result[4] == MISR_UM4) && (misr_result[5] == MISR_UM5) && (misr_result[6] == MISR_UM6) && (misr_result[7] == MISR_UM7) && (misr_result[8] == MISR_UM8) && (misr_result[9] == MISR_UM9)) { return FLS_SAFE_STATE_INACTIVE; } else { return FLS_SAFE_STATE_ACTIVE; // Integrity check failed } } Re: Flash memory array integrity check on MPC5746C Hello, The function compares the actual MISR values of the flash blocks with the expected values from output.txt. To setup a MISR tool you can refer to detailed readme.txt and folder start address examples. Attached is the complete tool, as it seems that some doc/example files are missing from the one in web example. Hope this will clear all doubts. Best regards, Peter Re: Flash memory array integrity check on MPC5746C We did not understand how the tool works to calculate the expected Golden signature.  Could you please provide the steps to calculate the expected signature. and How the tool present in the example works? Re: Flash memory array integrity check on MPC5746C Hello, I also have another question - how can we validate the calculated MISR signature value? In other words, how can we determine whether the signature we’re getting is correct? Validation Strategy Overview Calculate the MISR signature for a known memory region (e.g., a test array). Compare the result against a precomputed reference signature (golden value). If the values match, the memory content is considered valid. Could you please share sample code that calculates and validates the MISR signature value in order to complete the array integrity checks? #include "MPC5746C.h" // Replace with actual header for your environment #define ARRAY_SIZE 256 #define CRC_BASE_ADDRESS 0xFF000000 // Replace with actual CRC module base address uint32_t test_array[ARRAY_SIZE] = { /* Fill with known values */ }; uint32_t expected_signature = 0x12345678; // Replace with your golden MISR value void init_crc_module(void) { // Enable CRC module clock // Configure CRC settings (polynomial, seed, etc.) // This is platform-specific and may require register-level access } uint32_t calculate_misr_signature(uint32_t *data, uint32_t size) { volatile uint32_t *crc_data_reg = (uint32_t *)(CRC_BASE_ADDRESS + 0x04); // Data input register volatile uint32_t *crc_result_reg = (uint32_t *)(CRC_BASE_ADDRESS + 0x10); // Result register for (uint32_t i = 0; i < size; i++) { *crc_data_reg = data[i]; } return *crc_result_reg; } int main(void) { init_crc_module(); uint32_t signature = calculate_misr_signature(test_array, ARRAY_SIZE); if (signature == expected_signature) { // Signature matches // Memory integrity is validated } else { // Signature mismatch // Possible memory corruption } return 0; } You can have a look at this example, it is for same C55 flash module. https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5744P-FlashArrayIntegrityCheck-test-SSD-GHS614/ta-p/1099524 Best regards, Peter Re: Flash memory array integrity check on MPC5746C The reset is occurring because of a Machine Check Exception. I also have another question - how can we validate the calculated MISR signature value? In other words, how can we determine whether the signature we’re getting is correct? Could you please share sample code that calculates and validates the MISR signature value in order to complete the array integrity checks? Re: Flash memory array integrity check on MPC5746C Hello, Since reset is not happening when you are in debug mode, I would assume that issue is caused by some timer. Like SWT which is disabled by debuggers. You can read reset reason from the RGM [FES/DES] registers. Best regards, Peter

Feasibility of Upgrading from Nanbield to Scarthgap Yocto for Production – i.MX8QXP Hi NXP Team, We are currently working with the i.MX8QXP platform (imx8qxpc0mek) and have our Yocto setup based on the Nanbield release. As part of our roadmap planning, we would like to understand the feasibility of upgrading to the latest LTS Yocto release Scarthgap  for production use. Could you kindly confirm: Whether Scarthgap is recommended and stable for production builds on the i.MX8QXP? Are there any known compatibility issues or feature gaps (e.g., with modules like display, BT,WiFi, USB-PD, GNSS, eSIM, IMU, power management, STR, etc.) that we should be aware of compared to Nanbield? Do you foresee any migration concerns regarding SCFW porting, Linux BSP layers, or peripheral validation? Is SCFW support and NXP maintained layers (e.g., meta-freescale, meta-imx, meta-nxp-qt6-layer, etc.) already updated for Scarthgap for this SoC? Your input will help us assess the effort required for a potential LTS upgrade and ensure compatibility with our ongoing peripheral and thermal validation plans. Re: Feasibility of Upgrading from Nanbield to Scarthgap Yocto for Production – i.MX8QXP Hello, A1. Yes Scarthgap is LTS on NXP and yocto, You can find it on  6.6.52 BSP: https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX A2. NXP does not support Nanbield. is not LTS A3. Yes. A4. For Scarthgap yes. Regards

reduced Tx network throughput speeds when writing large files over NFS When running  iperf3 -s over the 10Gbase-t ethernet interface (using TQMLS1046A devkit) the benchmark shows 7.34 Gbaud (Giga bits per second) when the devkit sends (Tx) large data files (note that network path between the two systems is configured  with an MTU size of 9000 bytes for Jumbo frame). When TQMLS1046A is setup to receive the same workload (large files over NFS) on the Rx path of the ethernet interface we get the following error: [ 1068.551554] fsl_dpaa_mac 1af2000.ethernet enet_exp: Err FD status = 0x00080000 My interpretation of this might be misconfiguration of the FSL DPAA ethernet drivers in the kernel config but I don't know where to start. Re: reduced Tx network throughput speeds when writing large files over NFS Testing the changes and will provide an update on whether this is sufficient to resolve our issue. Re: reduced Tx network throughput speeds when writing large files over NFS Please configure the following option in Linux Kernel configuration file. FSL_DPAA_ETH_JUMBO_FRAME - "Optimize for jumbo frames" Optimizes the DPAA1 Ethernet driver throughput for large frames termination traffic (For example, 4K and above). Using this option in combination with small frames increases significantly the driver's memory footprint and may even deplete the system memory. Also, the skb truesize is altered and messages from the stack that warn against this are bypassed.

I²C接続状態に応じたPCA9539リセットの問題 こんにちは、 PCA9539 I/O エクスパンダーを使用していますが、I2C 接続状態に依存すると思われる予期しないリセット問題が発生しました。 問題は次のとおりです。 I²C 通信を介して PCA9539 のすべての出力ポートを HIGH に設定します。 出力ピンは予想どおり HIGH のままです。 ただし、SDA/SCL プローブ (I2C バスの監視に使用) を取り外すと、PCA9539 はリセットされ、出力ピンがデフォルト状態に戻ります。 このプロセス中、VCC は安定したまま継続的に供給され、RESET ピンはプルアップ抵抗を介して HIGH に保持されます。 MCUからの意図的なリセット信号や電源サイクルはありません 追加メモ: 同一のテスト条件下では、この問題は PCA9538 では発生しません。 I2C プルアップ抵抗が存在します。 電源は安定しており、コンデンサで分離されています。 イベント中、RESET ピンは異常なアクティビティを示しません。 プローブを切断する際のグリッチまたは不完全な START/STOP 条件により、PCA9539 の内部 I2C ステート マシンが障害状態になり、リセットのような動作が発生する可能性があると思われます。ただし、明示的なリセットや電源サイクルなしで PCA9539 が出力レジスタをクリアできるかどうかを確認するドキュメントは見つかりませんでした。 私の知る限り、I2C I/O エクスパンダーのCASE、電源が供給されている限り、I2C プローブがコネクテッドされているかどうかに関係なく、構成が保持されるはずです。この理解が正しいかどうか確認していただけますか? 質問: PCA9539 が RESET ピンのアサーションや電源サイクルを行わずに出力レジスタまたは I2C ロジックをリセットできる条件はありますか? プローブの取り外し中に SDA/SCL にグリッチが発生すると、デバイスが障害状態になり、構成された出力が失われる可能性がありますか? 機能が似ているにもかかわらず、なぜこの動作は PCA9539 では発生し、PCA9538 では発生しないのでしょうか? I²C バス接続に関係なく、電源が供給されている限り、I2C I/O エクスパンダーはその構成を維持するというのは正しいですか? この動作に関する洞察や公式ドキュメントがあれば、大変助かります。 よろしくお願いします。

32DS3.4安装问题 安装过程中装S32K3xx development package是遇到问题，见图片 Re: 32DS3.4安装问题 我这边安装SW32K3_RTD_4.4_R21-11_3.0.0_D2303_DS_updatesite实时驱动 现在编译没有问题了 Re: 32DS3.4安装问题 请问是已经安装完S32K3 RTD 3.0.0了？ 有没有根据工程里那个description.txt描述的Update Code? Before running the example a configuration needs to be generated. First go to Project Explorer View in S32 DS and select the current project. Select the "S32 Configuration Tool" menu then click on the desired configuration tool (Pins, Cocks, Peripherals etc...). Clicking on any one of those will generate all the components. Make the desired changes(if any) then click on the menu "ConfigTools->Update Code". Re: 32DS3.4安装问题 你好 我就在你给我的这里有一些FAE做的RTD3.0.0的示例 All Example S32K312 DS3.5 RTD-3.0.0下载了个S32K312_UART_DMA的程序后  辨析报错了如下图 Re: 32DS3.4安装问题 从S32K3 RTD 2.0.3之后，RTD就没有再包含S32K312的demo了。  网上能找到一些S32K312的示例，但都不像S32K344那样包含各个外设模块。 这里有一些FAE做的RTD3.0.0的示例 All Example S32K312 DS3.5 RTD-3.0.0 请问你按照我之前给你的链接，还能下载到RTD2.0.x吗？“Previous” tab里也找一下。 Re: 32DS3.4安装问题 你好 我这边S32DS3.6.3安装好了 我这边买的S32K312MINI-EVB开发板 请问官网的demo程序在哪块找？ Re: 32DS3.4安装问题 好的 我装一个新的版本试试 Re: 32DS3.4安装问题 Hi 抱歉 我看你之前是想要在S32DS v3.6.1里安装S32K3 RTD 2.0.x。 但如果你以前没下载过旧版本RTD的话，可能现在只能看到几个更新版本的RTD了。 点击 S32K3 Standard Software -> Automotive SW - S32K3/S32M27x - Real-Time Drivers for Cortex-M S32DS v3.6.x开始安装RTD简化了很多，只需要照着Offline Package Installation Setup步骤选择下载好的RTD离线包(_DesignStudio_updatesite.zip)就行了。 不建议使用S32DSv3.4这么旧的版本，现在的S32DS已经升级到v3.6.3了。 Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

i.mx53 快速用户板 我的主板附带的 microSD 卡不好。在哪里可以下载最新的 iso Linux 镜像，该镜像将使用此快速入门板启动？ 评估板 Re: i.MX53 Quick User Board 您好， 请参考此文档进行版本。 https://www.nxp.com/webapp/Download?colCode=IMX53_1109_LINUXDOCS_BUNDLE &location=null& fsrch=1 &sr=1 &Parent_nodeId=from%20search&Parent_pageType=from% 20search& Parent_nodeId=from%20search&Parent_pageType=from% 20search Best Regards, Zhiming

MBDTで生成されたコードをMatlabからS32DSにエクスポートする Matlab v2021b で MBDT を使用してコードを生成しました。ただし、組み込みコーダを使用してコードを生成した後、projectinfo.xml ファイルを s32DS にインポートしようとしました。しかし、エラーを下回っています。 S32DS V3.5を使用しています。S32DSのバージョンを変更してみる必要がありますか? 誰か、これを手伝ってください。 よろしくお願いします。 ロヒット Re: Export MBDT generated code from Matlab to S32DS こんにちは、 @rohit1749さん Simulink モデルのビルド プロセスとそれに続くコード生成に続いて、次の手順では modelName_Config フォルダーを S32 Design Studio (S32DS) にインポートします。 ファイル -> インポートを押してください 一般 -> 既存のプロジェクトをワークスペースへ -> 参照 -> modelName_Config フォルダを選択 その後、S32DS でアプリケーションをビルドおよびデバッグできるようになります。 進捗状況をお知らせください。 よろしくお願いいたします。 ドラゴス

Issue with sw1 regulator Hi, I hope this message finds you well. We are currently working with the PF5020 in (TBB) mode SW1 regulator, and we have encountered an issue. While writing to the SW1 RUN VOLT register, the values do not appear to be reflected on the SW1LX pin as expected. Could you please provide guidance on why this might be happening or suggest any troubleshooting steps we should follow to resolve this issue? And please provide sw1 regulator configuration sequence. Best regards, [Shivani] Re: Issue with sw1 regulator If you want to operate TBB mode please use our recommend socket board or EVB and use the special timing to enter into TBB mode then update the registers. PF502x Programming Board | NXP Semiconductors For more detail  you can read  attached file from page21--- 7.2 Operating in TBB mode

WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hello, I am working on the i.MX8ULP  and trying to use the WDOG32 in interrupt mode before it triggers a reset. Even though I have configured the watchdog with interrupt enabled, it is still behaving as a normal watchdog — it resets the system directly without generating an interrupt. void WDOG0_IRQHandler(void) { PRINTF("Watchdog IRQ triggered! Count = %u\r\n", wdog_irq_count); /* Clear interrupt flag */ WDOG32_ClearStatusFlags(WDOG0, kWDOG32_InterruptFlag); wdog_irq_count++; SDK_ISR_EXIT_BARRIER; } /* Get default configuration */ WDOG32_GetDefaultConfig(&config); /* Enable interrupt mode */ config.enableInterrupt = true; config.timeoutValue = WDOG_TIMEOUT_VALUE; NVIC_EnableIRQ(WDOG0_IRQn); for (temp = 0; temp < DELAY_TIME; temp++) { __NOP(); } /* Initialize WDOG32 with config */ WDOG32_Init(WDOG0, &config); while(1) { } I have attached full wdog32.c file also in that watchdog IRQ i have put watchdog refresh but still it is resetting after timeout occurs. Are there any additional initialization needed for WDOG32 interrupt mode and in this i only required interrupt not reset is it possible? i.MX8ULP Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, @Bio_TICFSL  Have you checked with the EVK to bootup on 0.9V when watchdog is resetting?  Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, @Bio_TICFSL  I have tested with the EVK using the watchdog example code at the default high frequency, and it boots fine. However, when I lower the voltage to 0.9V  (as in my earlier code snippet), after a watchdog timeout occurs the core gets stuck during bootup. If you have tested this on the EVK at 0.9V. Could you please share the exact code/configuration that you used on the EVK for this test? Regards, Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, The code is fine I just looking something that decrease the voltage, because  ~9.0 volts boot ok with the EVK. Regards Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hii, @Bio_TICFSL  status = UPOWER_ChngRTDDomBias(DRIVE_MODE_UD); assert(status == 0); status = UPOWER_ChngPmicVoltage(PMIC_BUCK2, PMIC_VOLTAGE_0_9V); if (status == 0) { status = UPOWER_GetPmicVoltage(PMIC_BUCK2, &voltage); if (status == 0 && voltage == PMIC_VOLTAGE_0_9V) { // success } else { assert(false); } } else { assert(false); } During debugging I found that: When the PMIC is set to 0.9V in ARBB mode, after a watchdog reset the core gets stuck during boot. If I increase the PMIC voltage to 1.0V or 1.1V, the reset and boot work fine, even at lower frequencies. I need to keep the PMIC voltage at 0.9V to save power, but with this setting the system cannot reliably boot after a watchdog reset. 👉 What might be causing this issue at 0.9V, and are there any recommended changes or workarounds to ensure the core can boot properly after a reset at this voltage? Any help or guidance would be appreciated. Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP On the Cortex-M33 of the i.MX8ULP, I have configured the M33 core to run in ARBB mode. When the watchdog timeout occurs, it tries to reset the core. However, during the reboot process the core seems to get stuck, because before the reset the code had switched the M33 into ARBB mode, which runs at a lower frequency. What modifications are required so that if the core is running in ARBB mode and a watchdog reset occurs, it can successfully boot up again? Re: WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hii, @Bio_TICFSL  I am able to use the watchdog in non-interrupt mode, and it is resetting the system as expected. However, I require the watchdog interrupt mode, and I am not sure about the correct configuration steps for enabling and handling the interrupt. Can you please guide me on how to enable WDOG32 in interrupt mode so that my code actually enters the WDOG32 IRQ handler before reset? Re: WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hello, Yes, it should be possible according to Reference Manual, look at chapter 9.1.7 Power mode details (real-time domain): As you can see all the necessary components to WDOG0 are available during ARBB mode, but maybe there is the possibility that uPower is gating clock of this WDOG or maybe of entire PBRIDGE0. Please take a look to the uPower Firmware User's Guide. Regards

WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hello, I am working on the i.MX8ULP  and trying to use the WDOG32 in interrupt mode before it triggers a reset. Even though I have configured the watchdog with interrupt enabled, it is still behaving as a normal watchdog — it resets the system directly without generating an interrupt. void WDOG0_IRQHandler(void) { PRINTF("Watchdog IRQ triggered! Count = %u\r\n", wdog_irq_count); /* Clear interrupt flag */ WDOG32_ClearStatusFlags(WDOG0, kWDOG32_InterruptFlag); wdog_irq_count++; SDK_ISR_EXIT_BARRIER; } /* Get default configuration */ WDOG32_GetDefaultConfig(&config); /* Enable interrupt mode */ config.enableInterrupt = true; config.timeoutValue = WDOG_TIMEOUT_VALUE; NVIC_EnableIRQ(WDOG0_IRQn); for (temp = 0; temp < DELAY_TIME; temp++) { __NOP(); } /* Initialize WDOG32 with config */ WDOG32_Init(WDOG0, &config); while(1) { } I have attached full wdog32.c file also in that watchdog IRQ i have put watchdog refresh but still it is resetting after timeout occurs. Are there any additional initialization needed for WDOG32 interrupt mode and in this i only required interrupt not reset is it possible? i.MX8ULP Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, @Bio_TICFSL  Have you checked with the EVK to bootup on 0.9V when watchdog is resetting?  Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, @Bio_TICFSL  I have tested with the EVK using the watchdog example code at the default high frequency, and it boots fine. However, when I lower the voltage to 0.9V  (as in my earlier code snippet), after a watchdog timeout occurs the core gets stuck during bootup. If you have tested this on the EVK at 0.9V. Could you please share the exact code/configuration that you used on the EVK for this test? Regards, Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, The code is fine I just looking something that decrease the voltage, because  ~9.0 volts boot ok with the EVK. Regards Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hii, @Bio_TICFSL  status = UPOWER_ChngRTDDomBias(DRIVE_MODE_UD); assert(status == 0); status = UPOWER_ChngPmicVoltage(PMIC_BUCK2, PMIC_VOLTAGE_0_9V); if (status == 0) { status = UPOWER_GetPmicVoltage(PMIC_BUCK2, &voltage); if (status == 0 && voltage == PMIC_VOLTAGE_0_9V) { // success } else { assert(false); } } else { assert(false); } During debugging I found that: When the PMIC is set to 0.9V in ARBB mode, after a watchdog reset the core gets stuck during boot. If I increase the PMIC voltage to 1.0V or 1.1V, the reset and boot work fine, even at lower frequencies. I need to keep the PMIC voltage at 0.9V to save power, but with this setting the system cannot reliably boot after a watchdog reset. 👉 What might be causing this issue at 0.9V, and are there any recommended changes or workarounds to ensure the core can boot properly after a reset at this voltage? Any help or guidance would be appreciated. Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP On the Cortex-M33 of the i.MX8ULP, I have configured the M33 core to run in ARBB mode. When the watchdog timeout occurs, it tries to reset the core. However, during the reboot process the core seems to get stuck, because before the reset the code had switched the M33 into ARBB mode, which runs at a lower frequency. What modifications are required so that if the core is running in ARBB mode and a watchdog reset occurs, it can successfully boot up again? Re: WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hii, @Bio_TICFSL  I am able to use the watchdog in non-interrupt mode, and it is resetting the system as expected. However, I require the watchdog interrupt mode, and I am not sure about the correct configuration steps for enabling and handling the interrupt. Can you please guide me on how to enable WDOG32 in interrupt mode so that my code actually enters the WDOG32 IRQ handler before reset? Re: WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hello, Yes, it should be possible according to Reference Manual, look at chapter 9.1.7 Power mode details (real-time domain): As you can see all the necessary components to WDOG0 are available during ARBB mode, but maybe there is the possibility that uPower is gating clock of this WDOG or maybe of entire PBRIDGE0. Please take a look to the uPower Firmware User's Guide. Regards

MBDT 何时支持 RTD 6.0.0 和 S32DS 3.6？ 我需要使用 S32K3 TCP/IP 协议栈 3.0.0、它基于 RTD 6.0.0 和 S32DS 3.6。 目前，MBDT 的最新版本是 1.6.0、基于 RTD 5.0.0 和 S32DS 3.5。 请问是否计划让 MBDT 支持 RTD 6.0.0 和 S32DS 3.6，这样我就可以在自定义代码中调用 TCP/IP 3.0.0？ 感谢您处理此事。 Re: When will MBDT support RTD 6.0.0 and S32DS 3.6? 你好，@pro778tw、 感谢您对 S32K3 基于模型的设计工具箱的关注。 将在本季度末发布的下一个工具箱版本（ MBDT S32K3 版本 1.7.0）中增加对 RTD 6.0. 0 和 S32DS 3.6 的支持。 顺祝商祺！ 德拉古

GTM Configure Tools license request Hi everyone, I'm trying to apply for a license for the GTM configure tools. When sending the relevant email to complete the process, I encountered a "Delivery incomplete" error from Gmail. The system shows there was a temporary problem delivering the message, and Gmail will retry for 20 more hours. But I'm worried this might affect the license application progress. Has anyone else faced a similar email delivery issue when applying for this license? How did you resolve it? Any suggestions on what I can do to make sure the email gets through successfully would be really appreciated. Thanks in advance!   Re: GTM Configure Tools license request Hello, Try it now. I was able request add GTM SW to your account. You should see it now in your NXP account. Best regards, Peter Re: GTM Configure Tools license request @petervlna  Thank you so much for your quick response and willingness to help resolve my GTM access issue—it’s really appreciated! Best regards Re: GTM Configure Tools license request Hello, Unfortunately admin is out of office and I have no info when he will be back. Could you please rise a request to : [email protected] for adding your account to access for GTM download / license access? Best regards, Peter Re: GTM Configure Tools license request Hello, OK, I will inform you once to access is successfully added. Best regards, Peter Re: GTM Configure Tools license request @petervlna  Thank you for your prompt response and assistance. I would like to request access to the GTM folder for the license using my email account: [email protected]. Please let me know if any further information is needed from my side to complete this process. I appreciate your help in coordinating with the admin to add the necessary permissions. Best regards Re: GTM Configure Tools license request Hello, Looks like you do not have access to the GTM. From what email account you would like to get access to GTM folder for license? I will ask admin to add the right for you. Best regards, Peter Re: GTM Configure Tools license request @petervlna  When I download other software from NXP, the process correctly redirects me to the Product List interface as shown in your previous image. However, when I attempt to download the GTM Configure Tools, it does not redirect to that Product List interface. Instead, it redirects to a different interface (as described below/attached). Thank you for your assistance.   Best regards,   Re: GTM Configure Tools license request Hello, The only reason could be that you do not have access to that SW. You can try manually find it in product list under NXP Software: Best regards, Peter Re: GTM Configure Tools license request  @petervlna  I've already downloaded the GTM configuration tools from the website you mentioned and installed it. But I'm wondering where the license download button you mentioned is. Also, on this interface, there's no display of the license key you referred to, and I can't find it through search either. Do you know what might be causing this? Re: GTM Configure Tools license request Hello, Licenses can be obtained via the https://www.nxp.com/gtmconfigtool website. If you are a new to the website, you will need to create a login account. Both trial and permanent licenses can be generated from there. For a trial license, select the 'Download' button. For the permanent license, select the 'Buy' button. You will be presented with an option to generate a license on the 'License Keys' tab on the Product Download page. Thereafter, you can proceed to 'My Account' and then 'Software Licensing and Support' to maintain your licenses and access updated product downloads. Actually the above statement is not fully true as I had to go via NXP SW account to the GTM to be able to download the license. The online request via GTM tool for license is not working for many years, as the email is sent to freescale email address which no longer exists. Best regards, Peter