S32K144H Cannot Establish Connect Hello, guys.  l am meeting a problem. l have got some new S32K144H chip. It did not work like this when l try to connect it with j-flash. l cannot unlock it with normal methods. l have never flash it. I heard a statement，like this "When the chip is empty, the RESET pin will exhibit periodic pulses."  Is it correct? l test my board, reset pin is always high. There is a 5V pull-up on reset. Is this effect my result or this is not a empty chip.  May be others ever flash it? Re: S32K144H Cannot Establish Connect Hi @Tom77854  Yes, that's correct, empty chip will reset periodically. It was discussed here, for example: https://community.nxp.com/t5/S32K/S32K144-New-Empty-Chip-Resets-Automatically-in-a-Certain-Period/m-p/1577829/highlight/true#M19832 The reset signal works as pseudo open drain. Pull-up resistor will not prevent the device to pull the reset pin down.  So, the chip is probably not empty. If the "unsecuring" does not work, mass erase may be disabled or CSEc may be enabled. In this case, there's no way to recover.  Do you know history of the chip? If the reset is not toggling, it's not brand new device.  Regards, Lukas Re: S32K144H Cannot Establish Connect Thanks for your answer. l will contact supplier.

在 TresOS 中使用 S32K14 AutoSAR 操作系统时出错 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 我安装了 tresos Studio 23.0、Autosar OS（SW32K14-OS401-RTM-1.0.0 b4.0.98）和 Autosar MCAL（SW32K14-MCAL401-RTMC-1.0.4）。 但当我尝试生成操作系统配置文件（.c、.h）时，却出现了以下 3 个错误： 1.The external generator for module Os_TS_T40D2M4I0R98 terminated with exit code 7 Used generator commandline：C:\EB\tresos\plugins\Os_TS_T40D2M4I0R98\ssc\bin\generator\sg.exe 2.Failed to run generator"Os_TS_T40D2M4I0R98GeneratorId" (mode:"verify") for module"Os_TS_T40D2M4I0R98" 3.外部生成器出错：C:\EB\tresos\workspace\oooooll\output\generated\epc\project.epc(1816)AUTOSAR/AR-PACKAGES/AR-PACKAGE [短名称='OS'] /元素/ECUC模块配置值 [短名称='OS'] /容器/ECUC-容器值 [短名='task_environce'] /参考值/ECUC-参考值 [定义-ref='/ts_t40d2m4i0r98/os/ostaskEventref']: 3254：“VALUE-REF” 的多重性检查错误二手生成器命令行：C:\EB\tresos\plugins\Os_TS_T40D2M4I0R98\ssc\bin\generator\sg.exe 我想知道问题出在哪里？以及如何解决？ 谢谢。 Re: Error While using S32K14 AutoSAR OS in TresOS @sandipta_mohan1你解决了这个问题吗？ Re: Error While using S32K14 AutoSAR OS in TresOS 哦，对不起，以上回答无法解决这个问题。在我师傅的帮助下，我们尝试了多次，发现 JRE 环境没有安装。 Re: Error While using S32K14 AutoSAR OS in TresOS 我的 AUTOSAR 操作系统是 4.0.98，EB 是 21.0.0，请尝试上面这些答案并不能解决问题，但我尝试卸载 21.0.0，然后安装 EB 24.0.1，却没有显示这两个错误。 Re: Error While using S32K14 AutoSAR OS in TresOS 我也有同样的问题。您能帮我解决这个问题吗？ Re: Error While using S32K14 AutoSAR OS in TresOS <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 你好，桑迪普塔-莫汉蒂 , 您似乎没有在配置中添加 OsTaskEvenRef 的值。请您尝试添加。 请注意，用户还需要在 OsEvent 中添加至少一个元素，以使列表显示在OsTaskEvenRef中。 顺祝商祺！ 洪

s32デザインスタジオのライセンス更新 アクティベーションID: 3F79-FF2D-6AFB-38F0 私のS32 Design Studioのライセンスが間もなく期限切れになります。更新したいのですが。 @jiri_kral

s32k144 DS StudioおよびSDK、RTDツールのセットアップ 皆様、 私はDS Studio 3.5を使用しています。 S32k144 SDKをインストールできません。解決策を教えてください。 DS Studio 3.4をインストールする必要がありますか？もし必要なら、ダウンロードリンクを教えてください。 よろしくお願いいたします。 チャルダッタ Re: s32k144 DS studio and SDK, RTD tool setup こんにちは、チャルダッタさん。 S32K1 SDK RTM 4.0.3 を使用する必要がある場合は、インストールしてください。 S32K1 SDK RTM 4.0.3 S32DSで v3.4 議論を参照 どこで入手できますか？S32_SDK_S32K1xx_RTM_4.0.3 。 S32K1 SDK 4.0.x を S32DS v3.5 または v3.6 にインストールすることは推奨されません。現在入手可能な情報によると、S32SDK S32K1XX 4.0.x を統合する予定はありません。S32DS 3.5以降のバージョンにインストールしてください。   しかし、最新のS32K1 RTDを使用することをお勧めします。旧SDKはバグ修正のためのアップデートは行われません。 Application Code Hub から K1 FRDM Bundle をクリックしてください。そして、 FRDM_Installation_Guide_2026_03.pdf のセクション 4. インストール手順 に従ってください。 よろしくお願いします、 ロビン ------------------------------------------------------------------------------- 注記： この投稿があなたの質問への回答になっている場合は、「解決策として承認」ボタンをクリックしてください。ありがとう！ - 最後の投稿から7週間はスレッドをフォローしますが、それ以降の返信は無視されます。 後日、関連する質問がある場合は、新しいスレッドを作成し、閉じられたスレッドを参照してください。 -------------------------------------------------------------------------------

UJA1169 can not write Mode control register (0x01) with S32k312 I try to write UJA1169 registers. As for register Lock control register (Address: 0x0A), it seems OK to write the value I want. But as for Mode control register (0x01), the register value not change. The details is like below: What's the different of the write operation of them？How can I successfully write Mode control register? Re: UJA1169 can not write Mode control register (0x01) with S32k312 I read SBC configuration control register (Address: 0x74) the value is value 0x10. Watchdog status register (0x05) value is 0x01, at the begining. that seems means SBC is not in Force normal mode. Re: UJA1169 can not write Mode control register (0x01) with S32k312 Hi, What is the device's operational state? If FNM, the SBC restricts writes to most control registers. BRs, Tomas

RT1052におけるSDRAMのIPTXDATレジスタの設定に関する問題 NXPテクニカルサポート： こんにちは！ 以下は、NXP公式RT1052 SDKに含まれる.iniファイルからのSDRAM初期化セクションです。 FUNC void _sdr_Init(void) ヤージュ // IOMUXの設定 _WDWORD(0x401F8014, 0x00000000); _WDWORD(0x401F8018, 0x00000000); _WDWORD(0x401F801C, 0x00000000); _WDWORD(0x401F8020, 0x00000000); _WDWORD(0x401F8024, 0x00000000); _WDWORD(0x401F8028, 0x00000000); _WDWORD(0x401F802C, 0x00000000); _WDWORD(0x401F8030, 0x00000000); _WDWORD(0x401F8034, 0x00000000); _WDWORD(0x401F8038, 0x00000000); _WDWORD(0x401F803C, 0x00000000); _WDWORD(0x401F8040, 0x00000000); _WDWORD(0x401F8044, 0x00000000); _WDWORD(0x401F8048, 0x00000000); _WDWORD(0x401F804C, 0x00000000); _WDWORD(0x401F8050, 0x00000000); _WDWORD(0x401F8054, 0x00000000); _WDWORD(0x401F8058, 0x00000000); _WDWORD(0x401F805C, 0x00000000); _WDWORD(0x401F8060, 0x00000000); _WDWORD(0x401F8064, 0x00000000); _WDWORD(0x401F8068, 0x00000000); _WDWORD(0x401F806C, 0x00000000); _WDWORD(0x401F8070, 0x00000000); _WDWORD(0x401F8074, 0x00000000); _WDWORD(0x401F8078, 0x00000000); _WDWORD(0x401F807C, 0x00000000); _WDWORD(0x401F8080, 0x00000000); _WDWORD(0x401F8084, 0x00000000); _WDWORD(0x401F8088, 0x00000000); _WDWORD(0x401F808C, 0x00000000); _WDWORD(0x401F8090, 0x00000000); _WDWORD(0x401F8094, 0x00000000); _WDWORD(0x401F8098, 0x00000000); _WDWORD(0x401F809C, 0x00000000); _WDWORD(0x401F80A0, 0x00000000); _WDWORD(0x401F80A4, 0x00000000); _WDWORD(0x401F80A8, 0x00000000); _WDWORD(0x401F80AC, 0x00000000); _WDWORD(0x401F80B0, 0x00000010); // EMC_39、DQS PIN、SIONを有効にする // パッド Ctrl // ドライブ強度 = 0x7 でドライブ強度を上げる // そうしないと、data7 ビットが失敗する可能性があります。 _WDWORD(0x401F8204, 0x000110F9); _WDWORD(0x401F8208, 0x000110F9); _WDWORD(0x401F820C, 0x000110F9); _WDWORD(0x401F8210, 0x000110F9); _WDWORD(0x401F8214, 0x000110F9); _WDWORD(0x401F8218, 0x000110F9); _WDWORD(0x401F821C, 0x000110F9); _WDWORD(0x401F8220, 0x000110F9); _WDWORD(0x401F8224, 0x000110F9); _WDWORD(0x401F8228, 0x000110F9); _WDWORD(0x401F822C, 0x000110F9); _WDWORD(0x401F8230, 0x000110F9); _WDWORD(0x401F8234, 0x000110F9); _WDWORD(0x401F8238, 0x000110F9); _WDWORD(0x401F823C, 0x000110F9); _WDWORD(0x401F8240, 0x000110F9); _WDWORD(0x401F8244, 0x000110F9); _WDWORD(0x401F8248, 0x000110F9); _WDWORD(0x401F824C, 0x000110F9); _WDWORD(0x401F8250, 0x000110F9); _WDWORD(0x401F8254, 0x000110F9); _WDWORD(0x401F8258, 0x000110F9); _WDWORD(0x401F825C, 0x000110F9); _WDWORD(0x401F8260, 0x000110F9); _WDWORD(0x401F8264, 0x000110F9); _WDWORD(0x401F8268, 0x000110F9); _WDWORD(0x401F826C, 0x000110F9); _WDWORD(0x401F8270, 0x000110F9); _WDWORD(0x401F8274, 0x000110F9); _WDWORD(0x401F8278, 0x000110F9); _WDWORD(0x401F827C, 0x000110F9); _WDWORD(0x401F8280, 0x000110F9); _WDWORD(0x401F8284, 0x000110F9); _WDWORD(0x401F8288, 0x000110F9); _WDWORD(0x401F828C, 0x000110F9); _WDWORD(0x401F8290, 0x000110F9); _WDWORD(0x401F8294, 0x000110F9); _WDWORD(0x401F8298, 0x000110F9); _WDWORD(0x401F829C, 0x000110F9); _WDWORD(0x401F82A0, 0x000110F9); // SDRコントローラレジスタの設定/ _WDWORD(0x402F0000,0x10000004); //MCR _WDWORD(0x402F0008,0x00000081); // BMCR0 _WDWORD(0x402F000C,0x00000081); // BMCR1 _WDWORD(0x402F0010,0x8000001B); // BR0、32MB _WDWORD(0x402F0040,0x00000F07); // SDRAMCR0 _WDWORD(0x402F0044,0x00652922); // SDRAMCR1 _WDWORD(0x402F0048,0x00010920); // SDRAMCR2 _WDWORD(0x402F004C,0x50210A08); // SDRAMCR3 _WDWORD(0x402F0090,0x80000000); // IPCR0 _WDWORD(0x402F0094,0x00000002); // IPCR1 _WDWORD(0x402F0098,0x00000000); // IPCR2 _WDWORD(0x402F009C,0xA55A000F); // IPCMD、SD_CC_IPREA SDRAM_WaitIpCmdDone(); _WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF SDRAM_WaitIpCmdDone(); _WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF SDRAM_WaitIpCmdDone(); _WDWORD(0x402F00A0,0x00000030); // IPTXDAT _WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS SDRAM_WaitIpCmdDone(); _WDWORD(0x402F004C,0x08080A01); // 初期化完了後にSDRAMの自己リフレッシュを再度有効にします。 } 公式のリソースマネージャ（リファレンスマニュアル）を確認しましたが、ステートメント「_WDWORD(0x402F00A0,0x00000030); // IPTXDAT」でレジスタ0x402F00A0のデータがx00000030に設定されている理由がまだ理解できません。実際、この部分はリソースマネージャではほとんど説明されていません。これは「0011 = CASレイテンシ = 3クロックサイクル」を設定するためだという説がネット上でありますが、それは正しいのでしょうか？ ありがとう！ Re: RT1052的SDRAM的IPTXDAT寄存器的配置问题 ありがたい！ Re: RT1052的SDRAM的IPTXDAT寄存器的配置问题 こんにちは、 @FromCH0 さん。 弊社製品にご関心をお寄せいただき、また弊社のコミュニティをご利用いただき、誠にありがとうございます。 "_WDWORD(0x402F00A0,0x00000030); // IPTXDAT _WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS" は、SDRAM メモリ内のモード レジスタに書き込むために使用されます。 SDRAMを初期化するには、SDRAMメモリ内のモードレジスタを設定する必要があります。以下は、SDRAM内のモードレジスタの例です。レイテンシモード、バーストタイプ、バースト長などを設定します。 つまり、0x00000030はSDRAM内部のモードレジスタの設定値に対応します。CASレイテンシを3、バースト長を1に設定した。 お役に立てれば幸いです。 よろしくお願いいたします。 メイ・リウ

Clearing GPIO ISR Hello everyone, We tried to follow the IMXRT1176 reference manual to gain access to GPIO_DISP_B2_00 pin from CM7 core. gpio_pin_config_t config = { kGPIO_DigitalInput, 0, kGPIO_IntRisingEdge, }; SETUP(IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01, 1, AD_PULL_UP + AD_SLEW_SLOW); GPIO_PinInit(GPIO5, 1, &config ); This happens in the pin_mux during the start-up. Somewhere later in our application we code which initialises the interrupt for that gpio: GPIO_PortClearInterruptFlags(GPIO5, 0xFFFFFFFF); GPIO_PortEnableInterrupts(GPIO5, 1 << 1); NVIC_SetPriority(GPIO5_Combined_0_15_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); EnableIRQ(GPIO5_Combined_0_15_IRQn); volatile uint32_t a = GPIO_PortGetInterruptFlags(GPIO5); PRINTF("%lu\r\n", a); This code prints: 4 294 901 757  Which is 0x FFFE FFFD --> 0b1111 1111 1111 1110 1111 1111 1111 1101 As you can see it looks like the pin 1 bit is 0. So we can assume reset affected it. However what i don't get, is why are the other bits set to 1, and why is bit 17 set to 0? Reference manual states 1402/6259: ``` Interrupt status bits Bit n of this register is asserted (active high) when the active condition (as determined by the corresponding ICR bit) is detected on the GPIO input and is waiting for service. The value of this register is independent of the value in IMR register. When the active condition has been detected, the corresponding bit remains set until cleared by software. Status flags are cleared by writing a 1 to the corresponding bit position ``` So i would assume that all values should be 0 as it's default reset state. Other GPIOs also follow somewhat similar pattern and have many bits set in it's ISR register. Could someone point me to what i misunderstand here? Thanks in advance for any help 🙂 Best Regards, Jakub Re: Clearing GPIO ISR Hi @jslota13245 , The misunderstanding is that the GPIO ISR reset value only describes the register state immediately after reset. It is not a guarantee of what software will read later during boot. The ISR is a latched status register: once the configured condition is detected, the bit stays set until software clears it, and this is independent of IMR. To determine which interrupt sources are currently enabled, we can use: GPIOx->ISR & GPIOx->IMR;  For RT1170, NXP also documents erratum ERR050643: DISP_B2 pins can see a brief internal pull-up pulse during initial power-up, so GPIO_DISP_B2_00 may legitimately have a pending status before the application reads the ISR. Therefore, a non-zero ISR after startup does not mean reset failed. Best regards, Gavin Re: Clearing GPIO ISR Dear @Gavin_Jia, thank you very much for detailed response. Your message has cleared up few things. 1) Just to confirm, as you could've noticed, in the example code i sent before, we explicitly write 0xffff ffff to status register to clear it, we do some no operation cycles, after that operation we almost immediately try to read it and get non-zero values in GPIO->ISR. That would mean that hardware has registered interrupt condition on most of pins between clear/read calls, which is hard to believe, since we don't even use them. This happens after the early start-up when GPIOs are initialized. So what you're suggesting is there is some hardware noise that may cause this behaviour when we write 0xffffffff to GPIO->ISR? 2) By the way, reading forums i found this thread: https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/GPIO-ISR-and-Clearing-ISR/m-p/1059441 With this answer: ''In your case you need to beware that the interrupt status of bits that are not configured for interrupt operation will read as being pending. Therefore you can not use just a check of the interrupt status like'' I was wondering if it's true because it somewhat fits the observed behavior. However I couldn't find anything about it in reference manual. Once again thank you very much for your support! Best Regards, Jakub

[Filter: smut] harshi03's post body matched "*shit*", board "imx-processors". [Filter: smut] harshi03's post body matched "*shit*", board "imx-processors". Post Subject: Re: Dual Display Enablement on i.MX8QuadMax with AAOS 14 Post Body: Hi,Thanks for response I have attached the screen shot that shows dtbo image used for flashing on imx8qm. Thank you, Harshitha  Body text "shit" matched filter pattern "*shit*". Post by User[id=261159,login=harshi03] has message uid 2350020. Link to post: Re: Dual Display Enablement on i.MX8QuadMax with AAOS 14

i.MX6ULZ: UART SDP works, OCRAM writes work, USB SDP enumerates but write always times out Hi, I’m bringing up a custom i.MX6ULZ board and I’m stuck in an odd state where the Boot ROM is clearly alive, but I can’t get reliable USB SDP transfers or any proof that a raw OCRAM payload executes after jump-address. Board / setup MCU: i.MX6ULZ, custom PCB USB: USB OTG1 over USB-C connector UART: UART1 broken out and connected through CH340 USB-UART No DDR populated yet Two separate assembled boards from the same PCB design show very similar behavior What is definitely working Boot ROM over UART SDP works sdphost can: read registers/memory write a raw binary to OCRAM at 0x00900000 Reading back OCRAM after write confirms the contents changed, so OCRAM writes are real USB behavior Over USB, the board is recognized by UUU as: MX6ULL SDP: 0x15A2 0x0080 USB attach is working well enough to enumerate uuu starts the SDP write, progress goes to 100%, then fails with timeout USB hardware details USB-C used in USB2 device mode CC1 and CC2 each have 5.1k pulldown to GND D+ and D- initially had 4.7 ohm series resistors, later replaced with 0 ohm for testing ESD diode was also removed for testing None of these changes fixed the USB SDP write timeout issue D+ and D- both measure ~0V with DMM at idle USB_OTG1_VBUS was checked before BGA reflow and had raw 5V from VBUS at the MCU-side net Power / internal rail observations POR_B is solid high when expected VDD_HIGH_CAP around ~2.5V VDD_SOC_CAP and VDD_ARM_CAP are present VDD_USB_CAP around ~3.0V NVCC_PLL around ~1.1V I did not observe obvious dips on VDD_USB_CAP or NVCC_PLL during the USB write attempt with a DMM Long story short ROM over UART clearly works OCRAM writes clearly work USB SDP clearly enumerates Yet USB SDP write always times out And I still cannot prove my raw OCRAM code executes Questions Is there any common mistake in custom i.MX6UL/ULZ USB OTG bring-up that could cause this kind of partial behavior? Does anything in the description stand out as suspicious or inconsistent? Thanks, Sam i.MX6 All i.MX6UL Re: i.MX6ULZ: UART SDP works, OCRAM writes work, USB SDP enumerates but write always times out here are screenshots of a writing attempt using uuu. as mentioned, it goes to 100% but then times out. I forgot to mention that once it fails, querying using uuu -lsusb takes much much longer to excute:  Re: i.MX6ULZ: UART SDP works, OCRAM writes work, USB SDP enumerates but write always times out Hi @samprince  Could you please share your uuu file, and i will test your scenario on my board. B.R

ビット・フィールド こんにちは、 私はMC9S12DG256コントローラーを使用しており、IDEはCodeWarrior 5.2です。オプションビットのフィールドサイズ縮小を無効にすると、メモリ割り当ては開始位置ではなく中間位置から開始されます。例えば、私の変数はint型ですが、0ではなく8から始まります。0から始まるようにしたいです。添付のスクリーンショットをご覧ください。 Re: Bit field こんにちは、 あなたがプレイしているゲームは、ビットフィールド要素（unsigned char、unsigned int）の定義されたサイズと、MSBに関連しています。LSB順、MSb順、LSb順。ヘルプを読んだ後、さまざまなオプションを組み合わせて試してみることをお勧めします。 ビットフィールドについてもっと詳しく知りたい場合は、以下のすべての出現箇所を確認することをお勧めします。 さらに、アイテムを選択すると、同じ名前の他のオプションが表示される場合があります。それぞれ異なるコンテンツに繋がっているので、すべて開いてください。 ...またはインストールディレクトリ c:\Program Files (x86)\Freescale\CWS12v5.2\Help\pdf\ に移動してください。 ファイル Compiler_HC12.pdf を開く そして、bitfield キーワードの存在をそれぞれ検索します。 よろしくお願いいたします。 ラディスラフ

I want to use multiple can rx and send with different message Id I want to use multiple Can Rx messages and I need to send same messages through different id’s. If anyone has working model please share here Re: I want to use multiple can rx and send with different message Id Hello @Sachinkumarar15, There is an existing example inside the RTD package for a simple FlexCAN configuration, along with some additional ones in our community: [RTD600 MCAL & IP] S32K3X4EVB-T172 FlexCAN Example Interrupt/Polling Example S32K344 FlexCAN_Ip TX/RX/EnhanceRXFIFO DMA test S32DS3.5 RTD400 You can modify them to receive and transmit multiple IDs. For Rx, simply modify the Rx filter, and for Tx, you can re-use the same Tx data and change the msg_id.  Best regards, Julián

複数のCAN RXを使用し、異なるメッセージIDで送信したい 複数のCAN-Rxメッセージを使用したいのですが、同じメッセージを異なるID経由で送信する必要があります。動作するモデルをお持ちの方がいらっしゃいましたら、こちらで共有してください。 Re: I want to use multiple can rx and send with different message Id こんにちは、 @Sachinkumarar15 さん。 RTDパッケージ内には、シンプルなFlexCAN構成の既存のサンプルがあり、さらにコミュニティにもいくつかの追加サンプルがあります。 [RTD600 MCAL & IP] S32K3X4EVB-T172 FlexCAN 割り込みのサンプル / ポーリング 例：S32K344 FlexCAN_Ip TX/RX/EnhanceRXFIFO DMAテスト S32DS3.5 RTD400 複数のIDを受信および送信するように変更できます。受信（Rx）の場合は、Rxフィルターを変更するだけで済み、送信（Tx）の場合は、同じTxデータを再利用してmsg_idを変更できます。 よろしくお願いします、 ジュリアン

LPC55S06: Determine Lifecycle property In-App Hi there, I am currently experimenting with secure boot on a LPC55S06 controller and wanted to know: is there is an equivalent API accessible from user application (non-bootloader context) to determine the Lifecycle state (property 17, described below), without entering the bootloader? For instance, I saw this status return code: kStatus_FLASH_SealedFfrRegion (137) in status_t But I think there should be a better way to determine the lifecycle state than trying to do a flash operation on the sealed ffr region and evaluating that the return code == kStatus_FLASH_SealedFfrRegion (137). Also I see no API in the SDK for this (using SDK 26.03). According to UM11126 Chapter 8, Table 420: LifeCycleState: Tag: 17 (11h) Indicates whether Flash security is enabled: 0x5aa55aa5 - Device is in development lifecyle 0xc33cc33c - Device is in deployment lifecycle Currently getting the value through blhost: blhost -p , -- get-property 17 Thanks! LPC55xx Re: LPC55S06: Determine Lifecycle property In-App Hello Carlos, coolest profile pic! Thanks for the quick answer, this workaround works for me. Re: LPC55S06: Determine Lifecycle property In-App Hi @sjrzcis  Thanks for your post! The Lifecycle value can only be read through the bootloader. There is no API available to access this parameter from the user application. We apologize for any inconvenience this may cause. As a workaround, I recommend adding a custom parameter to your image to indicate the device’s lifecycle state.

S32K344 - DMAスキャッターギャザーを使用してADCマルチチャネル値を取得する方法 私のプロジェクトでは、ADC0/ADC1/ADC2モジュールに分散配置された50個のADCチャネルを使用しました。各モジュール内のADCチャネルはランダムに配置されており、連続チャネルと不連続チャネルが混在していた。ADCモジュールはスキャンモードを使用し、起動後は中断やMCUの介入なしに、継続的にADC変換を実行します。チャネルのすべてのADCサンプリング値は、DMAモジュールを介して関連するメモリアドレス（dma_adc_value [50]など）に転送されます。スキャッターギャザーコレクタの設定方法が理解しにくく、ソースアドレス（ADC結果レジスタ）、デスティネーションアドレス、オフセット、マイナーループ、メジャーループの設定方法がわかりません。私はS32プラットフォーム3.5、RTD3.0.0、およびS32K344 MCU用のS32 Design Studioを使用しています。関連アプリケーションのリファレンスルーチンはありますか？ありがとう！ Re: S32K344-how to use DMA scatter gather get adc multi channel value こんにちは、@blue0432 さん。 MCTPTX1AK324 SWサンプルコードを参照してください： S32K324トリプル永久磁石同期モータ制御（PMSM）リファレンスデザインボード これは、PWM同期と位相依存型ADCリストのための散乱収集を設定します。 ただし、ADCの設定については、コミュニティ資料を参照することもできます。スキャッターギャザーの設定よりも、そちらの方が役に立つと思います。 例 S32K312 PIT BTCU パラレル ADC FIFO DMA DS3.5 RTD300 例 S32K344 PIT BTCU パラレル ADC FIFO DMA DS3.5 RTD300 ADCパラレル変換 一般的な解決策は、BCTUリスト/FIFOを使用してDMA結果配列にデータを供給することです。S32K3 ADCは、複数のADCインスタンスに対応するMPC（多重並列変換）もサポートしています。 最後に、 S32K3XX SAR-ADC、BCTU、TRGMUXのトレーニングプレゼンテーションをご参照ください。 よろしくお願いします、 ジュリアン

S32K344-how to use DMA scatter gather get adc multi channel value In my project, 50 ADC channels were used, distributed in ADC0/ADC1/ADC2 modules. The ADC channels in each module were randomly distributed, with some continuous and some discontinuous. The ADC module uses scanning mode and continuously performs ADC conversion after startup, without any interruption or MCU involvement. All ADC sampling values of channels are transferred to the associated memory address (such as dma_ adc_value [50]) through the DMA module. It is difficult to understand how to configure the scatter gather collector and do not know how to configure the source address (ADC result register), destination address, offset,  minor loop, and major loop. I am using S32 Design Studio for S32 Platform 3.5, RTD3.0.0, and S32K344 MCU. Do you have any reference routines for related applications? Thank you! Re: S32K344-how to use DMA scatter gather get adc multi channel value Hi @blue0432, You can refer to the MCTPTX1AK324 SW example code: S32K324 Triple Permanent Magnet Synchronous Motor Control (PMSM) Reference Design Board  It configures scatter gather for PWM synchronization and phase‑dependent ADC lists. However, you can refer to some community material for ADC configuration, which I think will serve you better than scatter gather configuration: Example S32K312 PIT BTCU parallel ADC FIFO DMA DS3.5 RTD300 Example S32K344 PIT BTCU parallel ADC FIFO DMA DS3.5 RTD300 ADC parallel conversion Usual solution is BCTU list/FIFO feeding a DMA result array. S32K3 ADC also supports MPC (Multiple Parallel Conversion) for more than 1 ADC instance: Lastly, you can refer to the S32K3XX SAR-ADC, BCTU AND TRGMUX Training presentation. Best regards, Julián

我能用 yocto 为 ls1028ardb 构建 6.12 内核版本的操作系统吗 我看到恩智浦已经发布了适用于 ls1028ardb 的电路板支持包，它在 6.6 之前支持内核版本，而且 yocto 对内核版本 6.12 不提供稳定的长期支持。需要知道，电路板支持包 是否支持 6.12 内核版本并且已经有人在 ls1028ardb 中使用这个版本了 Re: Can i build 6.12 kernel version of OS using yocto for ls1028ardb 你可以从以下链接下载最新的 yocto（walnascar）YP 5.2-lf-6.12.49 版本。 https://github.com/nxp-qoriq/yocto-sdk

MCXN947 ConfigTools Error Hello, when attempting to open the ConfigTools for a project I get the following error: "Processor 'MCXN947' is not supported or data for the processor is not available. Check the internet connection." I've already attempted uninstalling and reinstalling MCUXpressoIDE and the N947 SDK and have had no luck.  MCXN Re: MCXN947 ConfigTools Error Hello, Could you help us confirm your version of MCUXpresso IDE, MCUXpresso Config Tools and SDK? Probably you had an older version that does not contain MCXN947 and you need to update. Kindly follow the instructions in this post to enable the Config tools updates. Preferences>Install/Update>Available Software Sites>Enable MCUXpresso Config Tools Updating Config Tools in the MCUXpresso IDE, After this, probably some windows appear for available updates, select them and next, then accept terms of license agreement, Click on Accept>Finish>Select All>Trust Selected>Restart MCUXpresso IDE Let me know if that work for you, and if not, could you help us install the latest version of Config Tools (26.03) manually MCUXpresso Config Tools v26.03 and let me know your findings. Best Regards, Luis

Question about S32K3 Crypto version Hello Team May I ask about the  S32K3 Crypto version? Regarding the Crypto module, I have confirmed that it is not included in official releases such as S32K3 RTD 7.0.0 / 7.0.1, and that it exists only as Code Drop releases such as 7.0.0_P01 and 7.0.1_P02. Since Code Drops cannot be applied to mass production, I have a question from a customer regarding mass production use. Would it be acceptable to mix RTD 4.4.0 Crypto (or another existing version) with RTD 7.0.0 or 7.0.1 without issues? Thank you. RTD SECURITY_CRYPTO Source: Direct Customer Source: NXP Internal Re: Question about S32K3 Crypto version Hi @Luke_Chun  Would you mind taking 2 minutes to complete this feedback form? Software Support Case Feedback Survey – Prefilled form It would help us to have better support next time. Re: Question about S32K3 Crypto version Hi @Luke_Chun  If customer want to use in mass production, they have to wait until an official standard release (EAR, PRC or RFP) like mentioned in Release Notes. I see that RTD 7.0.0 or 7.0.1 supporting ASR 23-11, not 4.4. Furthermore, each Crypto release was tested on an RTD version, in this case is 7.0.0 and 7.0.1.  So, we cannot guarantee it works with RTD 4.4.0 Crypto.

Problems with NTAG DNA 424 - WriteData - Length Error Hello, I am trying to use the NTAG 424 chip for my anti-tamper application. For this I implemented the AES authentication and cryptographie for sending and receiving commands. However when I am trying to issue the writeData command with some dummy data, I get the error: 917E: "Length Error"". The data I am trying to send is the following cmd_header = 02000000040000 cmd_data = 00D1FF00 (before padding) cmd_data = 00D1FF00800000000000000000000000 (after padding) now the complete command which I send looks like this: cla cmd P1&2| Lc |ISO Header          | encrypted Data | 90 8D 00 00    1F 02 000000 040000 6688A4D75482FC972C2447A1A20F0AC9C073C1CF506B2BD3 00 I dont think that I made errors in the encryption, because I implemented a unit test which replicates the results of the example in the AN12196 application note (Table 17). Also, the PICC returns an Length error, which according to the Documentation means "Command size not allow". I do not understand this error, but I dont think it has something to do with my encryption. So does anyone know what I am doing wrong?  Best regards, Phil Update: So I can definitely say that the fault has nothing to do with my encryption, because I can correctly parse the response from the chips for commands like the GetTTStatus and the GetCardUID. Additionally I can correctly encrypt and send the SetConfiguration command, which tells me that I definitly send the correct command. Contact Smart Card Reader ICs Re: Problems with NTAG DNA 424 - WriteData - Length Error Dear @Jonathan_Iglesias ,  I am checking this post because I am having the same issue here. I followed the exact same steps in your post, but I keep getting 917E response. Do you think it might be due to my card reader? I am using an ACS ACR1251U. Also, you said: "check that you have changed the file settings so it supports encrypted communication and which keys are allowed to perform this actions." How do I check that? Regards, Re: Problems with NTAG DNA 424 - WriteData - Length Error Hi, I know this message was from a while ago, but I'm curious to know how you run the APDU commands on your NTAG424. I'm having issues with running commands. thanks. Re: Problems with NTAG DNA 424 - WriteData - Length Error Hi Philippe Petit,  Please let me know if my answer above was helpful. Looking forward to your answer. Have a great day ! BR Jonathan  Re: Problems with NTAG DNA 424 - WriteData - Length Error Hi  Please check the following : -----------ISO 14443-3 ACTIVATION------------------ phpalI14443p3a_ActivateCard--------ENTRY-------- Send to card: 26 Recv from card: 4403 Send to card: 9320 Recv from card: 88046F0FEC Send to card: 937088046F0FEC Recv from card: 04 Send to card: 9520 Recv from card: 2AAA618061 Send to card: 95702AAA618061 Recv from card: 20 phpalI14443p3a_ActivateCard--------LEAVE-------- pUidOut=046F0F2AAA6180 pSak=20 pMoreCardsAvailable=00 [STATUS = SUCCESS] --------------------ISO 14443-4--------------------------------- phpalI14443p4a_ActivateCard--------ENTRY-------- bFsdi=08 bCid=00 bDri=03 bDsi=03 Send to card: E080 Recv from card: 067777710280 Send to card: D0110F Recv from card: D0 phpalI14443p4a_ActivateCard--------LEAVE-------- pAts=067777710280 [STATUS = SUCCESS] -----------------ISO FILE SELECT------------------------------- phalMfNtag42XDna_IsoSelectFile--------ENTRY-------- bOption=0C bSelector=04 pFid=10E1 pFid=10E1 bDFnameLen=07 pDFname=D2760000850101 phpalI14443p4_Exchange--------ENTRY-------- wOption=8000 pTxBuffer=00A4040C07 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] phpalI14443p4_Exchange--------ENTRY-------- wOption=C000 pTxBuffer=D2760000850101 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] Send to card: 00A4040C07D276000085010100 phpalI14443p4_Exchange--------ENTRY-------- wOption=4000 pTxBuffer=00 phpalI14443p4_Exchange--------LEAVE-------- ppRxBuffer=9000 [STATUS = SUCCESS] Recv from card: 9000 phalMfNtag42XDna_IsoSelectFile--------LEAVE-------- [STATUS = SUCCESS] -------------------AUTHENTICATION TO KEY 00-------------------------- phalMfNtag42XDna_AuthenticatEv2--------ENTRY-------- bAuthOption=01 wOption=FFFF wKeyNo=0000 wKeyVer=0000 bKeyNoCard=00 phpalI14443p4_Exchange--------ENTRY-------- wOption=8000 pTxBuffer=9071000002 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] phpalI14443p4_Exchange--------ENTRY-------- wOption=C000 pTxBuffer=0000 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] Send to card: 9071000002000000 phpalI14443p4_Exchange--------ENTRY-------- wOption=4000 pTxBuffer=00 phpalI14443p4_Exchange--------LEAVE-------- ppRxBuffer=E21768618E1FDB9D93F596551CE06E6B91AF [STATUS = SUCCESS] Recv from card: E21768618E1FDB9D93F596551CE06E6B91AF PICC-to->PCD E(Kx, RNDB): E21768618E1FDB9D93F596551CE06E6B Plain RNDB = CE86E6E968F45458B6762D28D91764B8 Plain RNDA = D5D29FF822CD1A158E59A42AA74AA245 Encrypted (RndA || RndB') = 7B57022C027C5124E19AC54D5E38A10A732F64C98AA63F80F9536F4D889C257F phpalI14443p4_Exchange--------ENTRY-------- wOption=8000 pTxBuffer=90AF000020 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] phpalI14443p4_Exchange--------ENTRY-------- wOption=C000 pTxBuffer=7B57022C027C5124E19AC54D5E38A10A732F64C98AA63F80F9536F4D889C257F phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] Send to card: 90AF0000207B57022C027C5124E19AC54D5E38A10A732F64C98AA63F80F9536F4D889C257F00 phpalI14443p4_Exchange--------ENTRY-------- wOption=4000 pTxBuffer=00 phpalI14443p4_Exchange--------LEAVE-------- ppRxBuffer=1820F5BC0D050F4CAA73E388C86BE03188B85535D1B7682A9818ACEDA8D2A9E59100 [STATUS = SUCCESS] Recv from card: 1820F5BC0D050F4CAA73E388C86BE03188B85535D1B7682A9818ACEDA8D2A9E59100 PICC-to->PCD E(Kx, TI||RndA'||PDcap2||PCDcap2): 1820F5BC0D050F4CAA73E388C86BE03188B85535D1B7682A9818ACEDA8D2A9E5 MAC Input Data = Cmd||CmdCtr||TI||CmdHeader||E(CmdData) MAC Input Data = A55A00010080D5D2517EC42472E15458B6762D28D91764B88E59A42AA74AA245 MAC = 9E2BC594A132DD9FA2C236A7900BC709 MAC Input Data = Cmd||CmdCtr||TI||CmdHeader||E(CmdData) MAC Input Data = 5AA500010080D5D2517EC42472E15458B6762D28D91764B88E59A42AA74AA245 MAC = 13930ABCFB85B996262109D34C08726E Encrypted SessionKeyEnc KSesAuthENC = 9E2BC594A132DD9FA2C236A7900BC709 Session KeyType ENC = 0000 Encrypted SessionKeyMAC KSesAuthMAC = 13930ABCFB85B996262109D34C08726E Session KeyType MAC = 0000 Transaction Identifier = 9092A1C6 phalMfNtag42XDna_AuthenticatEv2--------LEAVE-------- bPcdCapsOut=000000000000 bPdCapsOut=000000000000 [STATUS = SUCCESS] AUTHENTICATED ----------------------WRITE DATA TO FILE---------------------------- phalMfNtag42XDna_WriteData--------ENTRY-------- bOption=30 bIns=01 bFileNo=02 pOffset=000000 pTxData=6688A4D75482FC972C2447A1A20F0AC9C073C1CF506B2BD3 pTxDataLen=180000 Encrypted (RndA || RndB') = 007D004AD1DF8F85B07D9CF17000DE2A Encrypted (RndA || RndB') = 75B2F5DDC646CA4C70B9A64F9D7888C2 Encrypted (RndA || RndB') = 3BA4362223091B1BFFE940229FA36A67 MAC Input Data = Cmd||CmdCtr||TI||CmdHeader||E(CmdData) MAC Input Data = 8D00009092A1C60200000018000075B2 MAC = 5B85393206D2041DEEF7AA344C0FAB66 MAC Input Data = Cmd||CmdCtr||TI||CmdHeader||E(CmdData) MAC Input Data = F5DDC646CA4C70B9A64F9D7888C23BA4362223091B1BFFE940229FA36A67 MAC = 43153DFF079B421A4A8E31AA92407AE5 phpalI14443p4_Exchange--------ENTRY-------- wOption=8000 pTxBuffer=908D00002F phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] phpalI14443p4_Exchange--------ENTRY-------- wOption=C000 pTxBuffer=02000000180000 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] phpalI14443p4_Exchange--------ENTRY-------- wOption=C000 pTxBuffer=75B2F5DDC646CA4C70B9A64F9D7888C2 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] phpalI14443p4_Exchange--------ENTRY-------- wOption=C000 pTxBuffer=3BA4362223091B1BFFE940229FA36A6715FF9B1A8EAA40E5 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] Send to card: 908D00002F0200000018000075B2F5DDC646CA4C70B9A64F9D7888C23BA4362223091B1BFFE940229FA36A6715FF9B1A8EAA40E500 phpalI14443p4_Exchange--------ENTRY-------- wOption=4000 pTxBuffer=00 phpalI14443p4_Exchange--------LEAVE-------- ppRxBuffer=87E6C1369D4C9F019100 [STATUS = SUCCESS] Recv from card: 87E6C1369D4C9F019100 MAC Input Data = Cmd||CmdCtr||TI||CmdHeader||E(CmdData) MAC Input Data = 0001009092A1C6 MAC = 568770E6F1C1E5362D9D844CCF9FA301 phalMfNtag42XDna_WriteData--------LEAVE-------- [STATUS = SUCCESS] Please check this process, this is the entire process I used, please check that you have changed the file settings so it supports encrypted communication and which keys are allowed to perform this actions. and check the LC of the APDU command. if you have more questions please let me know. Have a great day ! BR Jonathan Re: Problems with NTAG DNA 424 - WriteData - Length Error Hello Jonathan, thank you for your answer. you are right if we are in plain mode. If we are in plain mode, and I want to write the bytes (6688A4D75482FC972C2447A1A20F0AC9C073C1CF506B2BD3), then I have to have a length of 24 in my header.  If, however, I want to write the 4 bytes as specified in my question (in encrypted communication mode), then it does not work to put a length of 24 (18h) in the header. So my workaround for the moment is to write the 4 bytes in plain communciation mode (in which I dont have to perform the encryption) and then to lock the file with the desired key. However I would like to know how to write in encrypted mode? The Data-sheet is a bit unspecific in this term, and the application note is just plainly wrong (the application note has also a couple of other errors see for example) Thanks for  Re: Problems with NTAG DNA 424 - WriteData - Length Error Hope you are doing great,  I believe the problem is thar the lenght inside the CMD header is incorrectly please  check datasheet Figure 27  the number of bytes to be written  should be 24 bytes  (6688A4D75482FC972C2447A1A20F0AC9C073C1CF506B2BD3) BR Jonathan 

Bad GDFLIB user guide file in RTCESL page for DSP56800EX Hello NXP, I reopen my older project with MC56F84xxx and I want to use newest motor control libraries. I download latest RTCESL library set, version 4.8, from GitHub. But, when i downloaded the documentation files for each library I found bad content in file DSP56800EXGDFLIBUG. Inside this file is description for AMCLIB not for GDFLIB. Can you pls. send me a correct file with GDFLIB content for MC56F84xxx DSC family, or can you corect link on the RTCESL page? Link to the bad UG file. Link to the RTCESL page.  Thanks. Best regards Vladimír Re: Bad GDFLIB user guide file in RTCESL page for DSP56800EX Hello @VladkoV , Thank you for bringing this to our attention. I have reviewed the issue and can confirm that it matches what you described. This appears to be a web-related bug. I will escalate this to the web team for further investigation and resolution. I will make sure to keep you updated on any progress. Have a nice day. BR Celeste Re: Bad GDFLIB user guide file in RTCESL page for DSP56800EX Hello @VladkoV , Please see attached DSP56800EXGDFLIBUG,  Rev. 4, 05/2019. Hope it helps. BR Celeste Re: Bad GDFLIB user guide file in RTCESL page for DSP56800EX Hello @VladkoV , Thanks for your patience. I got the reply from the internal. The correct link will be restored as soon as possible. BR Celeste