What does it mean HSE_SWT_RST on S32K311!!! Hello all. Where can I found information about HSE_SWT_RST reset? With the following clock configuration: PLL_PHI0_CLK=120MHz CORE_CLK=PLL_PHI0_CLK/1=120MHz AIPS_PLAT_CLK=PLL_PHI0_CLK/2=60MHz AIPS_SLOW_CLK=PLL_PHI0_CLK/4=30MHz HSE_CLK=PLL_PHI0_CLK/1=120MHz DCM_CLK=PLL_PHI0_CLK/4=30MHz at power on I occasionally get the reset HSE_SWT_RST. What is the cause? I probably need to reduce the HSE clock to 60 MHz or change the value of HSE_CLK_MODE_AND_GSKT_CTRL to 10 of the dcf_client_utest_misc client. Where can I find documentation that explains this? Best regards E. Re: What does it mean HSE_SWT_RST on S32K311!!! Hi @enricoantonioli  The HSE_SWT_RST is usually caused by wrong clock configuration. It was found out that it is possible to configure 120MHz HSE_CLK only during reset by DCF record. It cannot be done later by software for some reasons. That means it is necessary to set PLL_ENABLE in BCW (Boot Configuration Word) in IVT, it is necessary to program crystal oscillator configuration flag in UTEST at 0x1B000050 (see section 32.4.3.2 Crystal oscillator configuration flag in the S32K3 RM), it is necessary to program the dcf_client_utest_misc - HSE_CLK_MODE_AND_GSKT_CTRL equal to 10 or 11. Re: What does it mean HSE_SWT_RST on S32K311!!! Hi, Thanks for the precious information, but I still don't understand why in my situation there is a HSE_SWT_RST reset. What is the cause? What's wrong with the HSE? Best regards E. Re: What does it mean HSE_SWT_RST on S32K311!!! Hi @enricoantonioli  What does HSE_SWT_RST mean? It stands for HSE Software Watchdog Timer Reset. Is it a reset due to an internal HSE watchdog or what? The HSE CPU is mainly composed of Arm Cortex-M0+, which one of its essential peripherals is the watchdog.  So yes, it is trigger by HSE SWT as the name implies. Why this reset occurs if no firmware is programmed into the HSE memory? The HSE CPU, even if the HSE firmware is not loaded, is active because it contains the SBAF code. Re: What does it mean HSE_SWT_RST on S32K311!!! HI Vane, first of all, thank you very much for your quick reply. At the moment I have reduced the HSE_CLOCK to 60 MHz because in the HSE there isn't programmed a firmware. I will activate HSE soon. What does HSE_SWT_RST mean? Is it a reset due to an internal HSE watchdog or what? What I don't understand is why this reset occurs if no firmware is programmed into the HSE memory? If I understand correctly, at power on the HSE processor executes the SBAF code and then stops in a WFI. So who triggers the HSE_SWT_RST reset? Best regards E. Re: What does it mean HSE_SWT_RST on S32K311!!! Hi @enricoantonioli  According to the information, it seems that the problem is due to incorrect clock configuration. The HSE_CLK_MODE_AND_GSKT_CTRL (bit 30-29) must be set to 1x if you want to use HSE_CLK equal to 120 MHZ. On the other hand, if HSE_CLK_MODE_AND_GSKT_CTRL was set to 00, it is necessary to change HSE_CLK to 60 MHZ. Refer to S32K3xx_DCF_clients file attached to the S32K3xx Reference Manual.  This must be done by writing to dcf in UTEST memory using Flash controller. You can check the following article, it might be a good reference.  [S32K3] Restrict the debug access with a password when HSE is not used BR,VaneB

mbdt simulink peripherals Can somebody clarify with this issue regarding port error. how can i restore it to defaults Re: mbdt simulink peripherals So sir within the range of port pin ids can we assign the portpin_id numbers randomly ? Re: mbdt simulink peripherals Hi, @paul_ephraim_13, The PortPin Id tab represents the ID of the port pin, as the name suggests, and can be seen more easily as the index of all the pins in the Port tab. The error you encounter is due to the fact that the mentioned Id is greater than the total number of pins. For example, if we have configured 2 PortContainers and each of them has 5 PortPins, then the PortPin Ids will be from 1 to 10. If you try to set PortPin Id 11 to one of the pins, then the error will show as in the image presented by you, because the number of pins is 10. In your case, I think that you most likely deleted one of the pins and the order of the IDs was altered. Make sure that the PortPin Id is not greater than the total number of pins and the error will disappear. Another recommendation would be not to modify the mex file that contains the default configuration, i.e. S32K312-Q172.mex, as I can see in your screenshot, but it is recommended to modify the mex file of the model you are trying to configure. When you open a model set on S32 Configuration Tools, or create a new one, the mex file with the default configuration from the devices folder is copied next to this model. After this copying, you can change the mex file next to the model by clicking on the Configure button from any block in the MBDT library, and you can make configuration changes without changing the default mex file. Thus, if you want to return to the default settings, by deleting the mex file next to the model and reopening it, the default mex file will be copied again next to the model. Hope this clears up your problem. Best regards,  Dragos

ISO-26262 ASIL-C compliant PIL testing with S32G-VNP-GLDBOX Hi, it there some ISO 26262 certification of S32G-VNP-GLDBOX used together with Matlab Simulink plugin for PIL testing, and some guidelines to prove the toolchain can be considered as qualified? I mean something like MathWorks have their ICE Certification kit?  Simulink plugin: Model-Based Design Toolbox | NXP Semiconductors Re: ISO-26262 ASIL-C compliant PIL testing with S32G-VNP-GLDBOX Hi @Jan_S,  Thanks for the questions. Unfortunately, we do not have the expertise with the MBDT software to give a support with that you can ask at: Model-Based Design Toolbox (MBDT) community, the Goldbox there is known as HCP.  Regarding to the ISO 26262 you can find the following on the S32G3 Reference Manual:   [Page 3660, S32G3 Reference Manual, Rev. 4, 02/2024] Also, at the Product details of the GoldBox 3 Vehicle Networking Development Platform site you could find the next:

LPUART データを受信できません S32K311のLPUARTを使用してデータを送受信しています。データを送信するのは正常ですが、チップはコンピューターから送信されたデータを受信できません。その理由は何ですか?ありがとうございます。 Re:LPUARTはデータを受信できません こんにちは、@Julián_AragónM、 ご返信ありがとうございます。問題を解決しましたが、接続に問題があります。再接続後は正常に通信ができます。 Re:LPUARTはデータを受信できません Hi.@Julian-アラゴンM、 ご返信ありがとうございます。シリアルからUSBへのコンバーターを使用し、あなたが私に与えた例に従ってコードを変更しましたが、私のチップはまだデータを受信できません。問題が何であるかを見つけるのを手伝ってもらえますか?

S32G3 ubuntu login in username & passwd Hi, I recently used yocyo to compile fsl-image-ubuntu, but after burning the generated image to the sd card, the login is not like fsl-image-auto, which can be used by using "root". Please tell me how to log in to ubuntu  S32G-VNP-RDB3  Re: S32G3 ubuntu login in username & passwd Hi, @carlos_o : Thanks for your suggestion,you are right! Re: S32G3 ubuntu login in username & passwd Hi @jiajun_cheng, Please refer to the BSP User Manual of the version you are using. There at the chapter 3.1.3 BSP Ubuntu Build you can find the user and password.   [page 13, Linux BSP 42.0 User Manual for S32G3 platforms] 

软件激活失败，服务器错误 我正在尝试激活 S32 Design Studio for Arm，但在线和离线激活均失败，并显示错误消息“ com.acresso.activation.handler.ServerException ” 激活服务器似乎出了问题？

ファイル .prmおよび .inc9S12XEA128用 コミュニティの皆さん、こんにちは。私は.prmを探しています9S12XEA128 のファイル、またはその更新 (Service Pack) があるかどうかを調べるため。どなたかお持ちですか?CW5.2を使用していますが、デバイスのリストにありません。 ありがとうございます。

S32K144 MCUを使用して同じFTMインスタンスのFTMチャネルで異なる周波数を使用する方法 私はS32K144 MCUを使用しており、FTMペリフェラルインスタンス0を使用しています。 FTM0_CH0とFTM0CH1で異なる周波数を生成したい。 しかし、私が観察したことは、APIによって1つのチャネルの周波数/周期を変更すると、 次のようになりますFtm_Pwm_Ip_UpdatePwmPeriodAndDuty(FTM_INSTANCE_0、channel0、35000、12000、TRUE); その後、他のチャンネルの周波数も変更されます。 すべてのチャンネルのMOD登録が同じであることがわかりました。したがって、周波数を変更するためにMOD値を変更すると、FTMインスタンス全体の周期が変更されます。 しかし、同じFTMインスタンスのチャネルで異なる周波数を使用したい場合はどうでしょうか。 どうすればそれを達成できますか?

文件 .prm和 .inc对于 9S12XEA128 社区里的大家好。我正在寻找 .prm9S12XEA128 的文件或查明是否有更新（服务包）。有人有嗎？我使用 CW5.2，但它不在设备列表中。 谢谢。

s32k312 can not debug Hi NXP,    my environment is  jlink v11  and s32DS. it  works until yesterday, when starting debug, it can stop at main entry,  then run step into, or any other operation, it goes to unknown state. the abnormal as attached. 1. debug can't  halt CPU. 2. read sram failed. but with the same hardware and elf file,  i use ozone , it works normally.  here my debug cofig. it's same compare to it's working time. 回复： s32k312 can not debug i dont know what cause this problem, after totally reinstall S32DS , solved.  but after few days use, S32DS debuger seems responses slower than normal. currently, use OZone to program and debugger instead. Re: s32k312 can not debug Hi, Senlent Ozone is software on PC, my board and jlink are the same. i just use it instead of S32DS debug function, all others are same. Re: s32k312 can not debug Hi@victory I don't find any problem with your configuration, and your other debuggers (ozone) can burn and debug your hardware normally, so the possible reason may be your J-LINK tool or the link problem.

[I.MX8M Plus][BSP L6.1.22]从Docker容器内部访问NPU的方法 我们的产品需要把AI推论应用方法Docker容器中运行，请问怎样做才能让Docker内的应用程序直接访问NPU呢？ 我搜索了论坛找到一篇相关的帖子，但是它的BSP版本太旧了。 https://community.nxp.com/t5/eIQ-Machine-Learning-Software/eIQ-Docker-8MP-L5-10-X-NPU/m-p/1348329/highlight/true?profile.language=ja 请帮助解决，谢谢。 回复： [I.MX8M Plus][BSP L6.1.22]从Docker容器内部访问NPU的方法 HI @linzhenggang1  请问解决了吗，可以分享一下步骤吗

ADC1 is not working on S32K148 Hello, I am using an S32K148 development board and I am trying to use ADC0 and ADC1. ADC0 is working properly but from some reason, I am not able to use ADC1, it seems like this is not enabled. The get_adc1_data() is printing any time value 0 Do you have any suggestion? I am using the following code #define INST_ADC_CONFIG_1 (0U) #define INST_ADC_CONFIG_2 (1U) const adc_converter_config_t adc_config_1_ConvConfig0 = {     .clockDivide = ADC_CLK_DIVIDE_2,     .sampleTime = 255U,     .resolution = ADC_RESOLUTION_8BIT,     .inputClock = ADC_CLK_ALT_1,     .trigger = ADC_TRIGGER_SOFTWARE,     .pretriggerSel = ADC_PRETRIGGER_SEL_PDB,     .triggerSel = ADC_TRIGGER_SEL_PDB,     .dmaEnable = false,     .voltageRef = ADC_VOLTAGEREF_VREF,     .continuousConvEnable = false,     .supplyMonitoringEnable = false }; const adc_chan_config_t adc_config_1_ChnConfig0 = {     .interruptEnable = true,     .channel = ADC_INPUTCHAN_EXT17 }; const adc_converter_config_t adc_config_2_ConvConfig0 = {     .clockDivide = ADC_CLK_DIVIDE_2,     .sampleTime = 255U,     .resolution = ADC_RESOLUTION_8BIT,     .inputClock = ADC_CLK_ALT_1,     .trigger = ADC_TRIGGER_SOFTWARE,     .pretriggerSel = ADC_PRETRIGGER_SEL_PDB,     .triggerSel = ADC_TRIGGER_SEL_PDB,     .dmaEnable = false,     .voltageRef = ADC_VOLTAGEREF_VREF,     .continuousConvEnable = false,     .supplyMonitoringEnable = false }; const adc_chan_config_t adc_config_2_ChnConfig0 = {     .interruptEnable = true,     .channel = ADC_INPUTCHAN_EXT13 }; void ADC_init() {     /* Initialize ADC */     ADC_DRV_ConfigConverter(INST_ADC_CONFIG_1, &adc_config_1_ConvConfig0);     ADC_DRV_AutoCalibration(INST_ADC_CONFIG_1);       /* Initialize ADC */     ADC_DRV_ConfigConverter(INST_ADC_CONFIG_2, &adc_config_2_ConvConfig0);     ADC_DRV_AutoCalibration(INST_ADC_CONFIG_2); }   void get_adc0_data() {       uint16_t adcRead;       (void) data;     (void) len;       ADC_DRV_ConfigChan(INST_ADC_CONFIG_1, 0U, &adc_config_1_ChnConfig0);     ADC_DRV_WaitConvDone(INST_ADC_CONFIG_1);       /* Store the channel result into a local variable adcRead*/     ADC_DRV_GetChanResult(INST_ADC_CONFIG_1, 0U, &adcRead);       printf("ADC0 data = %d\n\r>", adcRead); }   void get_adc1_data() {       uint16_t adcRead;       (void) data;     (void) len;       ADC_DRV_ConfigChan(INST_ADC_CONFIG_2, 1U, &adc_config_2_ChnConfig0);     ADC_DRV_WaitConvDone(INST_ADC_CONFIG_2);       /* Store the channel result into a local variable adcRead*/     ADC_DRV_GetChanResult(INST_ADC_CONFIG_2, 1U, &adcRead);       printf("water temp is = %d\n\r>", adcRead);  } Re: ADC1 is not working on S32K148 Thank you very much. It was working! Re: ADC1 is not working on S32K148 Hi@mcristian please change the below hightlight part to 0 Re: ADC1 is not working on S32K148 Hello, Thanks for reply. You can find the project attached Re: ADC1 is not working on S32K148 Hi@mcristian Can you provide me with a working project so that I can reproduce your problem?

[Harpoon Yocto][iMX8MN] Configure the CPU cores in the cell Dear Harpoon Experts, From the UG10170 - Harpoon User's Guide,  I learn that there's a possibility to configure the number of CPU core(s) allocated to the RTOS : For a multicore (SMP) cell, two cores can be used. For instance, on i.MX 8M: .cpus = { 0b1100, }, I would like to know if it is feasible to allocate up to 3 cores to the RTOS ? And what file(s) among the below should I modify in the case of iMX8M Nano EVK and FreeRTOS, please ? • configs/arm64/imx{8m*,93,95}-harpoon-freertos.c for the cell configuration of the FreeRTOS hello_world and rt_latency use case • configs/arm64/imx{8m*,93,95}-harpoon-zephyr.c for the cell configuration of the Zephyr hello_world and rt_latency use case • configs/arm64/imx{8m*,93}-harpoon-freertos-audio.c for the cell configuration of the FreeRTOS audio use case • configs/arm64/imx{8m*,93}-harpoon-zephyr-audio.c for the cell configuration of the Zephyr audio use case • configs/arm64/imx{8m*,93}-harpoon-freertos-avb.c for the cell configuration of the FreeRTOS audio (AVB) use case • configs/arm64/imx{8m*,93}-harpoon-zephyr-avb.c for the cell configuration of the Zephyr audio (AVB) use case • configs/arm64/imx{8m*,93}-harpoon-freertos-industrial.c for the cell configuration of the FreeRTOS industrial use case • configs/arm64/imx{8m*,93}-harpoon-zephyr-industrial.c for the cell configuration of the Zephyr industrial use case • configs/arm64/imx{8m*,93}-harpoon-freertos-virtio.c for the cell configuration of the FreeRTOS Virtio Networking use case Thanks in advance and best regards, Khang i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: [Harpoon Yocto][iMX8MN] Configure the CPU cores in the cell Hi @3517884267  I would suggest you check the Harpoon user's guider,  you can get the source code from github. Regards Daniel Re: [Harpoon Yocto][iMX8MN] Configure the CPU cores in the cell Where to download the source file configs/arm64/imx8mn-harpoon-freertos.c Re: [Harpoon Yocto][iMX8MN] Configure the CPU cores in the cell configs/arm64/imx{8m*,93,95}-harpoon-freertos.c 源文件在哪下载 Re: [Harpoon Yocto][iMX8MN] Configure the CPU cores in the cell Hi  khang: I would suggest you modify the CONFIG_INMATE_CORE_BITMAP in configs/arm64/imx8mn-harpoon-freertos.c   Regards Daniel Re: [Harpoon Yocto][iMX8MN] Configure the CPU cores in the cell Hi @danielchen, Thanks for your answer. Can you please tell which file should I apply the modification ? Searching within imx-jailhouse, I only found : $ ag ".cpus =" | grep imx8mn configs/arm64/imx8mn-lk.c:177: .cpus = { configs/arm64/imx8mn.c:65: .cpus = { configs/arm64/imx8mn-linux-demo.c:42: .cpus = { configs/arm64/imx8mn-inmate-demo.c:45: .cpus = { configs/arm64/imx8mn-root-lk.c:66: .cpus = { But nothing relevant to RTOS. Best Regards, K. Re: [Harpoon Yocto][iMX8MN] Configure the CPU cores in the cell Hi @khang_letruong  It is possible to configure the number of core to '3'  to allocate to the RTOS.    You need to change here 45     .cpus = { 46 #if defined(SINGLE_CORE) 47         0x1, 48 #elif defined(THREE_CORES) 49         0x7, 50 #else 51         0x3, 52 #endif 53     }, Since we don't test this scenario on our side before, you need to do more tests,  and let us know if you come across some issues. Regards Daniel

T2081：从 IFC NOR 启动 - 闪存（0xE000_0000 至 0xE7FF_FFFF） 大家好， 我有一块基于 T2081 的定制板，以 128Mbytes IFC NOR FLASH 地址作为启动介质。我们希望配置处理器从 0xE8000000 获取 RCW。但是当我们在 0xE800_0000 处刷新 RCW 时，我们没有看到 CS 上的任何活动，并且开机后 HRESET 保持低电平（电路板处于复位状态）。因此，我们将 RCW 刷新到 0xE000_0000，这样，我们就能看到 CS 多次切换，并且开机后 HRESET 处于高电平（主板已复位）。即使我们在 0xE7F4_0000 位置刷入了 u-boot，我们也没有在控制台上看到任何启动打印。 以下是我关于 IFC 和 boot 的疑问， 1. 处理器如何知道从 IFC NOR 闪存中获取 RCW 的地址？0xE000_0000 或 0xE800_0000 2. TRM中提到，复位后，核心将从0xFFFF_FFFFC开始执行，然后跳转到NOR闪存地址。这个配置是如何控制的？ 3. 在调试模式下，所有 LAW 寄存器和 DDR 配置均由 TCL 脚本完成（在我的情况下是 RAM TCL 脚本）。但是在闪存启动模式下，如何处理这些配置？ 谢谢！ 努法尔 回复：T2081：从 IFC NOR 启动 - 闪存（0xE000_0000 至 0xE7FF_FFFF） 如果您使用256M NOR闪存，请修改内存映射 从 0xE0000000 到 0xEFFFFFFF。 回复：T2081：从 IFC NOR 启动 - 闪存（0xE000_0000 至 0xE7FF_FFFF） 明白了。无论如何，如果我们想修改 NOR 闪存启动的默认 TLB 和 LAW 配置，我们该怎么做呢？ 例如 如果我想使用 256MB NOR 闪存，而不是使用 T2081 的 128MB NOR 闪存，我认为必须修改 TLB 和 LAW 配置。那么我该怎么做呢？ 谢谢！ 努法尔 回复：T2081：从 IFC NOR 启动 - 闪存（0xE000_0000 至 0xE7FF_FFFF） 是的，不需要修改T2081QDS_init.c，您可以使用默认的TLB和LAW配置。 回复：T2081：从 IFC NOR 启动 - 闪存（0xE000_0000 至 0xE7FF_FFFF） 请参阅T2081QDS_init.c中的“本地访问Windows设置”部分。 回复：T2081：从 IFC NOR 启动 - 闪存（0xE000_0000 至 0xE7FF_FFFF） 我明白了。 但是每个接口的 LAW 寄存器配置怎么样？ 在调试模式下，我们在 TCL 配置文件中执行所有操作。但我们不知道 NOR 闪存启动是否有相同的配置。假设如果必须根据我的接口列表修改任何 LAW 寄存器，我该如何进行 nor flash 启动的配置？ 回复：T2081：从 IFC NOR 启动 - 闪存（0xE000_0000 至 0xE7FF_FFFF） 好的， 那么在 NOR 闪存启动模式期间，如何进行配置（LAW/IFC 等） 例如就我而言，我的闪存只有 128MB，地址范围从 0xE8000000- 0xEFFFFFFF。这些案件是如何处理的？ 回复：T2081：从 IFC NOR 启动 - 闪存（0xE000_0000 至 0xE7FF_FFFF） T2081QDS_init_sram.tcl 仅用于调试模式或进行闪存编程。 回复：T2081：从 IFC NOR 启动 - 闪存（0xE000_0000 至 0xE7FF_FFFF） 知道了。 另一件令人困惑的事情是， 我们在“T2081QDS_init_sram.tcl”文件中添加的配置仅在调试模式下使用，或者来自 tcl 文件的配置将被写入处理器内部的内存（ROM 或任何）并在 NOR 闪存启动期间使用？ 谢谢， 努法尔 回复：T2081：从 IFC NOR 启动 - 闪存（0xE000_0000 至 0xE7FF_FFFF） 如果您有自定义的 DDR 控制器初始化参数，则可以使用 T2081QDS_init_core.tcl。 我们经常建议客户使用 T2081QDS_init_sram.tcl 来避免在闪存编程期间初始化 DDR 控制器。 回复：T2081：从 IFC NOR 启动 - 闪存（0xE000_0000 至 0xE7FF_FFFF） 感谢你的回复。 2. tcl CW初始化文件是指“T2081QDS_init_core.tcl “用于 DDR 负载？ 问候， 努法尔 回复：T2081：从 IFC NOR 启动 - 闪存（0xE000_0000 至 0xE7FF_FFFF） 1.系统将在NOR flash的开头获取RCW，并且u-boot应该部署在NOR flash的末尾。 2.这个是硬件控制的，处理器会从NOR flash的末尾取指令。 3. 请在 tcl CW 初始化文件中使用 NOR 闪存配置 0xE8000000- 0xEFFFFFFF。 NOR 闪存映射应该是 0xE8000000 到 0xEFFFFFFF， 0xE000_0000 根本不是有效的地址。

New installation of JCOP Tools gives class file format error I have a new installation of JCOP Tools which gives "unsupported class file format of version 66.0" error for a basic template applet. This is listed as a known issue in JCOP Tools Getting started app note "If both Eclipse and Java are not same (32 or 64), Following error will be displayed in problem view of Eclipse " however everything is 64-bit. Java version 22.0.1 (24-04-16) JDK version 22 Eclipse version 4.32.0 (2024-06) JCOP Tools version 6.9.0.12 Any suggestions much appreciated. Re: New installation of JCOP Tools gives class file format error I was eventually able to resolve this issue, which turned out to be incorrect installation instructions. When installing under Windows the documentation says install Visual C++ Redistributable 2012. This is to ensure critical Windows libraries (DLLs) that the package depends on are present. One of the library dependencies is MFC100.DLL. However Visual C++ Redistributable 2012 actually installs MFC110.DLL causing a missing library dependency. Installing Visual C++ Redistributable 2010 installs the required MFC100.DLL and JCOP Tools then runs correctly. Hope this is useful to someone else ;-).

imx9596 - is it possible to flash only M7 core with JLink ? Hello, I am currently working on an iMX9596 evaluation board and I am therefore trying to do multi-OS segregation. To flash the different cores, I am creating a flash.bin file and flashing it using the USB-C port, as explained in the datasheet and training documents. I can then obtain two OSes running: a Linux one on the A55 cores and a Zephyr one on the Zephyr core. I will often change the Zephyr OS but not the Linux one, which is why I am trying to be able to quickly change the Zephyr firmware using the JTAG port and a J-Link probe. I downloaded the latest J-Link software and found out that my device, iMX9596-M7, is listed in the J-Link library. However, when I tried to connect with J-Link, I got the following error, attached to this message. Furthermore, my SM on M33 causes my Zephyr and Linux systems to reboot as well. Is there a way to flash only the M7 using J-Link, or is this not supported? I would also like to be able to debug with it. Thank you in advance for your answers. Re: imx9596 - is it possible to flash only M7 core with JLink ? Thanks for sharing. Re: imx9596 - is it possible to flash only M7 core with JLink ? Hello, Ok thanks. Regards, Audrey. Re: imx9596 - is it possible to flash only M7 core with JLink ? I found that if you stop linux booting in uboot you can then flash the M7 core with jlink probe. Re: imx9596 - is it possible to flash only M7 core with JLink ? Hi @anicolle  sorry imx9596 is not launched yet.   I would suggest you contact the person who gave you this product for support. Regards Daniel

S32G3 bootconfig through serial EEPROM Hi experts, About S32G3 bootconfig through serial EEPROM how can I obtain current bootconfigwords and fix it. Thank you! Re: S32G3 bootconfig through serial EEPROM Hello @piaochunri, Sorry for the late response, once you select a correct answer the topic is marked as closed and I stop receiving notifications. Please create a new post with your new problem as it is not completely related to the original post so one of my teammates or myself can help you.  Sorry again for the late response Re: S32G3 bootconfig through serial EEPROM I'm glad to know you were able to solve the problem! Thanks for marking the answer as accepted. Re: S32G3 bootconfig through serial EEPROM I have sovled the problem after I set the host name of s32g debug probe and I can config the EEPROM now. Thank you! Re: S32G3 bootconfig through serial EEPROM Yes.We are debugging a self-developed board of S32G399A.The scheme of boot mode part is referred to S32-VNP-RDB3. I was debugging Acore and the version of bsp is 40.0.And I followed the link HOWTO: Program Serial RCON using S32 Debug Probe S32G2xx - NXP Community t o debug it. But when I runned the python script it could not pass the initialization whether I inserted the SD card or not.The result seems the same. What should I do?Thank you! Re: S32G3 bootconfig through serial EEPROM Thank you!Yes,I have read these documents.We are debugging a self-developed board of S32G399A. The designed scheme of boot mode is referred S32G-VNP-RDB3(RCON12 and RCON13).I also referred the link HOWTO: Program Serial RCON using S32 Debug Probe S32G2xx - NXP Community to debug the EEPROM.But it stopped during initialization.My A core bsp  version is 40.0. I used S32 debug probe.Is it necessary to connect the debugger to my laptop through ethernet or USB connection is ok?The info of probe is as follows. And I runned the python script.It resulted in error.What should I do?Thank you!   Re: S32G3 bootconfig through serial EEPROM Hello @piaochunri, To be able to boot from SerialRCON I recommend you check AN13456 [page 6, S32G3 Boot Process, Rev. 1, 02/2023] You can also get more information in the S32G3 reference manual [page 1319, S32G3 Reference Manual, Rev. 4, 02/202]: This means the 32bits used as boot configurations need to be already present in the EEPROM. If it's possible I can recommend using EEPROM AT24C01C-XPD-T, which is used in the EVB3-Board which supports S32G3 chips.  Let me know if this information solved your question Re: S32G3 bootconfig through serial EEPROM We are debugging a self-developed board with S32G399A. And our board only supports bootconfig through serial RCON not through parallel RCON. I want to known how can I set it.I have tried some commands during u-boot step.But I am not sure it is useful. Re: S32G3 bootconfig through serial EEPROM Hello @piaochunri , I’m assuming you are using the RDB3 board. Then the 32 bits (0 – 31) you see in the excel file represent the 4 dip switches present in your board: You can check the schematic to see the order of the bytes [page 32, S32G-VNP-RDB3, SPF-53060.pdf] available in deseing files section of the S32G-VNP-RDB3 product page: You can check the User Guide to learn more about the different switch configurations [Starting in page 3, Chapter 3, S32G-VNP-RDB3 Switch Setting, S32G-VNP-RDB3 User Guide, Rev. 1.0, 03/2023] available in de documentation section of the S32G-VNP-RDB3 product page: Let me know if this information solved your question.

Getting access to the GPIO ports on the iMX7ULP-EVK - how hard can it be? Hi I have tried to get access to the GPIO ports on the iMX7ULP-EVK, but it s causing me some troubles. It should be possible to either set a value or read a value from a port in the embedded Linux system by creating a node e.g.: echo 611 > /sys/class/gpio/export  Where 611 corresponds to PTF3? I'm a bit uncertain about this number, but it is coming from  cat /sys/kernel/debug/pinctrl/40ac0000.pinctrl/gpio-ranges which corresponds to the four groups of ports (PTC, PTD, PTE and PTF) and for the last one, PTF it says: 40b1000.gpio GPIOS [608-627] PINS [96 - 115] PTF3 is the fourth counting from zero, that means is should be 611 - is this right? At least I can create a node the command at the top, and if I try to make a node outside the ranges from the list, I get an error. When I have made a node, I get access to the features like "active-low", "direction" etc.. However I cannot change the direction from in to out for port 611 but I can for port 610. Could this be related to the Device Tree Source? If I read out the value of the port 611 it is zero and remains zero even if apply 3.3V to the PTF3 pin on the evaluation board (accessible on the connector for the Arduino - and yes, I have taken R155 into consideration, since the resistor needs to be mounted to enable the pin-header. I just applied the 3.3v on the pads for the resistor). Could the missing ability to read from the status of the pad be related to missing configuration of the Device Tree Source? Questions about GPIO in Device Tree Source I have managed to compile the Device Tree Source from the files embedded in the yocto project, and if I change the model name (IMX7ULP-EVK) to something else, I can see that is has changed in the .dtb file (by decompiling the file afterwards). The file is working afterwards since the processor can boot and use the MIPI interface. I then tried to add some code for the for the GPIO: In imx7ulp-evk.dts inside "&iomuxc1" &pinctrl { pinctrl_gpio_leds: gpio_leds_grp { fsl,pins = < IMX7ULP_PAD_PTF14__PTF14 0x22 /* Configure PTF14 as GPIO */ IMX7ULP_PAD_PTF15__PTF15 0x22 /* Configure PTF15 as GPIO */ >; }; };  In the imx7ulp-evkb.dts I place the following code: gpio_leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; led1 { label = "LED1"; gpios = <&gpio_ptf 14 GPIO_ACTIVE_HIGH>; /* PTF14 */ default-state = "off"; }; led2 { label = "LED2"; gpios = <&gpio_ptf 15 GPIO_ACTIVE_HIGH>; /* PTF15 */ default-state = "off"; }; }; I still have an error to fix before I manage to compile the additional code above, but it could be nice of there were an example how to get the GPIO ports to work from start to finish (I haven't been to find the information) just to confirm that I am on the right track? I how does this go together with the pin mux that is configured for the m4 processor? Hope some can bring some clarity to have to get the GPIOs working for an embedded linxux. i.MX7ULP Linux Yocto Project Re: Getting access to the GPIO ports on the iMX7ULP-EVK - how hard can it be? Hi Aldo Thanks for your response. I'm not sure what you mean with "peripherals being used on the M4 should be disabled on the Cortex-A" since my intention keep as many functions as possible working on the evk, and only change the functions needed to make some GPIOs free and available. I managed to compile a new .dtb file that enables the gpio pins. The definition of the leds remained the same as in the original post, but the pin-mux had to be changed slightly: &pinctrl { pinctrl_gpio_leds: gpio_leds_grp { fsl,pins = < IMX7ULP_PAD_PTF14__PTF14 0x14 /* Configure PTF14 as GPIO */ IMX7ULP_PAD_PTF15__PTF15 0x14 /* Configure PTF15 as GPIO */ >; }; }; If the GPIOs have been configured correctly, that will visible in the linux kernel cat /sys/kernel/debug/gpio providing a output similar to this:   Now the output of the pin can be changed by: echo 1 > /sys/class/leds/LED1/brightness /* turn on led */ echo 0 > /sys/class/leds/LED1/brightness /* turn off led */   This also answered the question in relation to the number of the GPIO ports, which were respectively 622 and 623. Also when a GPIO port has been defined as a an LED in the Device Tree Source, then it is not possible to access the GPIO as a node, but instead /sys/class/leds/LED1/ has to be used to access the properties. Re: Getting access to the GPIO ports on the iMX7ULP-EVK - how hard can it be? Hello, What error are you getting when trying to compile? PTA & PTB are used on the M4, and do remember that peripherals being used on the M4 should be disabled on the Cortex-A or it will crash when booting into Linux. Also, make sure to not use them on user space that can cuase the same as above, it is better to have everything configured on device tree to avoid this kind of issues. Best regards/Saludos, Aldo.

Support of Camera module Hello,  For our application, we have choosed IMX8M-plus processor and the camera sensor from the omnivision (OSO2H10),  we are interested to know, If IMX8M-plus supports the firmware for OSO2H10 camera sensor? OSO2H10 is a raw sensor without any ISP, we have chosen IMX8M-plus to use the ISP within the processor, do you support the tunning of ISP for this camera module? Kindly share the list of camera modules/sensor supported for IMX8M-plus. Thanks,  i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: Support of Camera module Thanks for the response and the links! Understood, using the reference of OV5640, I can develop the driver for OSO2H10. I can use available API for ISP tunning. Regards, Re: Support of Camera module Hello, The OSO2H10 is not support be default on MX8Mplus but it support the OV5640 and should be similar the driver for it you can migrate to your camera with the ISP usage please check: https://www.nxp.com/docs/en/user-guide/iMX8MP_CAMERA_DISPLAY_GUIDE.pdf https://www.mouser.com/datasheet/2/302/AN13736-3073771.pdf?srsltid=AfmBOoobASIHe4SOtrDvchLUQZebrqyxVnrzqtdGbq-ijvDr65FejhXf Regards

自己DC-DC昇圧電圧機能を使用しないMC33PT2000について NXPチーム各位:        3気筒インジェクションの場合、DC-DC Vboost電圧(65V)がこのチップの組み込み機能ではなく外部回路を使用して生成される場合、レジスタとコードはどのように設定する必要がありますか? ソレノイドコントローラー Re:自己DC-DC昇圧電圧機能を使用しないMC33PT2000について どうもありがとうございました!!