Enabling Data Cache Hi, I'm testing the inference time and performance of TFLite AI Models on the NXP FRDM-MCXN947 MCUs. While I'm getting good performance using the NPU, I'm getting comparably slow inference times when not using it. I have been able to reduce inference time for other MCUs by enabling the Data Cache. I would like to know how to enable D-Cache on the NXP MCUs. Any other performance boost strategies are also welcome. MCXN NPU|ML Re: Enabling Data Cache Enabling data cache can really speed up workflows and reduce repetitive processing. For those looking to plan effectively, the Persona fusion strategy offers a clear way to anticipate outcomes and optimize results. It’s fascinating how combining the right elements can lead to unexpected efficiencies. This approach definitely makes managing complex data much more approachable. Re: Enabling Data Cache Interesting! Have you experimented with compiler optimization flags? Often, bumping up optimization (e.g., -O3) can significantly speed up code when the NPU isn't active. Also, regarding D-Cache, check the SDK documentation for CACHE_Enable or similar functions, specifically for the MCXN947. Remember optimizing often comes down to a balancing act like in Slope Game, optimizing code versus hardware limitations for top performance. Good luck! Re: Enabling Data Cache Hi @ge0rgeth0mas
The CACHE64 module is used to cache FlexSPI accesses.
Based on your need, you just need to enable lpcache.
BR
Harry Re: Enabling Data Cache It's great to see you exploring TFLite AI Models on the NXP FRDM-MCXN947! Enabling D-Cache can indeed enhance performance significantly. You might also look into optimizing your model size or quantizing your models for better efficiency. Speaking of performance, have you tried integrating it with gaming applications like the Snow Rider 3D game? It could be a fun way to test the capabilities of your setup! Re: Enabling Data Cache Hi Harry, I was going through the reference manual and SDK drivers as you mentioned: I noticed theres is * fsl_cach_lpcac.h which contains L1CACHE_EnableCodeCache() and * fsl_cache.h which contains CACHE64_EnableCache(CACHE64_CTRL_Type *base) Could CACHE64 be data cache and LPCAC be Instruction cache? Re: Enabling Data Cache Hi Harry, Could CACHE64 be data cache and LPCAC be Instruction cache? Re: Enabling Data Cache Hi @ge0rgeth0mas
You can refer to the Chapter 5 in MCX Nx4x Reference Manual.
Regarding cache related APIs.
You can refer to the fsl_cache_lpcac.h in MCXN947 SDK.
BR
Harry
Re: Enabling Data Cache That's fascinating work! I've dabbled in similar optimization challenges before. Have you explored different quantization techniques for your TFLite models? Sometimes, even small tweaks there can make a difference when the NPU isn't engaged. Speaking of fast-paced action, it reminds me of playing Basketball Stars! It demands quick reflexes and strategy, just like optimizing AI. You might find it a fun distraction when you need a break from the coding. Re: Enabling Data Cache That's interesting work on the FRDM-MCXN947! It's great you're exploring different performance optimizations. I haven't worked with that specific MCU, but data cache enabling definitely makes a difference in many cases. You might find some helpful insights from communities focused on embedded development, or perhaps even those discussing similar optimization challenges within the context of games like, ironically enough, Suika Game! Sometimes the approaches to efficiency in game development translate unexpectedly well. Good luck with your project! Re: Enabling Data Cache Thanks for sharing this issue. Hardware acceleration gets a lot of attention, but CPU-side optimization is still very important for edge AI applications. Cache configuration, memory alignment, CMSIS-NN optimizations, and compiler flags are definitely areas worth exploring. It’s the same idea as improving skills step by step in games like Drift Boss — small adjustments can lead to much better results over time. Re: Enabling Data Cache Your NPU results sound promising, and the CPU gap may indeed point to cache or memory placement issues. Besides enabling D-Cache, check whether model tensors and weights are placed in fast SRAM, confirm compiler optimization flags, and profile individual operators to identify bottlenecks. It may also help to compare CMSIS-NN kernels against default TFLite implementations. Like optimizing Slope Unblocked, small changes in memory access can significantly improve responsiveness.
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