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Number of supported endpoints on the iMX8 The iMX8 uses the DWC3 for USB, which is an xHCI controller. When I read out the register from iMX8 i can figure out, that it may support up to 64 devices. But when I attach a few devices I much earlier on run in xHCI resource error. It seems there is some kind of a limitation on the number of endpoints, and it also seems that it depends on the type of transfer type (Bulk, Control, ...). On the type of devices I use (includsing the hubs) it seem I run after 80 endpoints into the problem. Could you please provide some exact numbers/formula how many endpoints are supported. Re: Number of supported endpoints on the iMX8 Hello,  The i.MX8 xHCI MaxSlots = 64 value specifies the maximum number of enabled USB device slots, not the total endpoint capacity. xHCI is up to 31 endpoint contexts per device, but the controller does not guarantee that all 64 slots can simultaneously use the maximum number of endpoints. The usable total depends mainly on periodic bandwidth, device speed, endpoint interval and packet size, hub topology, Transaction Translator allocation and DWC3 implementation resources.   Please refer xHCI specification for detailed information. Re: Number of supported endpoints on the iMX8 I checked the xHCI specification and could not find any indication. The only thing xHCI specifies that a controller can return resource error (the one I already mentioned above) E.g. Intel describes for one of their xHCI controller that they support up to 2048 Bulk/Control EPs or up to 128 Interrupt/Isochronous EPs. https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/servers/platforms... We have test setup (USB 2.0 only) which works well on Intel chips (several hundred EPs), but fails on a fraction on devices on the iMX8MP (the mentioned 80 EPs). But to know how many and what type of devices we can support we need to know what the limitation of the iMX8MP/DWC3 are. It would be very helpful if you can provide us some kind of formula or limitations, the same way Intel does.
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S32 Design Studio for S32 Platform 3.5 License I have one laptop and one desktop computer. Uninstalling and reinstalling on the laptop requires two licenses for S32 Design Studio for S32 Platform 3.5.
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s32k2018.R1没办法延期 麻烦帮我给这个激活码延下期,谢谢。 Activation Code D870-0066-E5E6-ACC7 Re: s32k2018.R1没办法延期 你好, 您的S322DS许可证已延期。请使用您之前的激活码重新激活S32DS。
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S32 Design Studio for S32 Platform 3.5 License 本人一个笔记本,一个台式机,笔记本卸载重装,需要2个S32 Design Studio for S32 Platform 3.5 的License
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The license for S32 Design Studio version 3.4 on the S32 platform has expired. My S32 Design Studio (for S32 platform) v.3.4 has expired. Could you please extend the validity period of my activation code? S32 Design Studio Version v.3.4 Order Number: S32DS-3-4_188376977 Purchase order number Total number of licenses: 101 Activation code: 7EEF-99B6-BDC8-8692 Re: S32平台S32 Design Studio 3.4版本的许可证已过期。 Hi,  your S32DS license has been extended. Please activate S32DS again with your old code. 
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Unable to open probe index1. Error: Probe not open Hello, I am trying to debug the LED Blinky example on the FRDM-MCXN947, but I am running into several errors and cannot establish a debug connection to the target. Note: Another FRDM board works correctly on the same laptop, and this FRDM-MCXN947 works on a different laptop. The issue only occurs with this specific board on this specific laptop (although I have only tested this with one other laptop and one other FRDM-MCXN947). I think I may have the same problem as described here: https://community.nxp.com/t5/MCX-Microcontrollers/unable-to-open-probe-index-1/td-p/2416776 So I tried using the MCUXpresso Secure Provisioning Tool to erase the device, but that did not work for me. Any ideas what could be causing this issue, or anything else I could try to fix it? FRDM-MCXN947 Re: Unable to open probe index1. Error: Probe not open Hello @JustinNL , Thanks for your post. Since the same FRDM-MCXN947 board works correctly on another laptop, and another FRDM board also works on this laptop, the board itself is likely OK. From the screenshots, one important error is: "Failed to communicate with debug probe." This suggests that the issue may be related to the communication between the laptop and the onboard MCU-Link debug probe, rather than the application or the MCXN947 device itself. As a first step, could you please try the following:   - Close MCUXpresso IDE and MCUXpresso Secure Provisioning Tool. - Open Windows Task Manager and check whether there are any LinkServer processes still running. If so, please end task. - Disconnect the FRDM-MCXN947 from USB, wait a few seconds, and reconnect it. - Open only MCUXpresso IDE and try debugging the LED Blinky example again. If the issue still occurs, please also try a different USB port, preferably connecting the board directly to the laptop rather than through a USB hub or docking station. If these steps do not help, we can then further check the MCU-Link firmware and Windows USB device/driver status. Could you please let me know the LinkServer version used by MCUXpresso IDE, as well as the MCU-Link firmware version on your FRDM-MCXN947 board?   Regards, Celeste Re: Unable to open probe index1. Error: Probe not open Thank you for your reply. I could not find any LinkServer processes still running after closing MCUXpresso. I tried two other USB ports (three in total), all connected directly to the laptop, but I still get the same errors as before. LinkServer version: v26.9.130 (Build 130) MCU-Link firmware version: CMSIS-DAP V3.174 (running on the MCU-LINK of the FRDM-MCXN947 board) MCUXpresso IDE v25.6.136 I have attached some screenshots/pictures and hope they will be helpful. Kind regards, Justin
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AraRT 3.0 x86:Lenovo Ara240 8GB構成とLinux 6.12ドライバの問題 ホスト:Lenovo ThinkCentre neo Ultra、12W2CTO1WW NPU FRU: 5C50W32071、Lenovoによる説明では8GB LPDDR4X PCI ID: 1e58:0002、リビジョン02 ランタイム:AraRT 3.0 Linux x86-64、Qubes/XenのDebian 13 HVM上で動作。 ゲスト:Debian 13、Linux 6.12.113、Qubes/Xen PCIパススルー PCIパススルーはデバイスを検出します。現在、どのNPUドライバもバインドされていません。 ドライバーソース:nxp-imx-support/uiodma-driver ドライバーコミット:962d11df1a9334e851f1f8a5b00f7e8960609e6a、Linux 6.12.113でコンパイルするためにコールバック署名の変更が必要でした コミュニティの皆様に、以下の件についてできるだけ早くご協力をお願いしたいと心からお願い申し上げます。 - カーネルと互換性のあるx86ドライバを管理し、IRQのクリーンアップとeventfd検証に対応しています。 - このFRUの正しいボード名、ランク、DDR構成ファイル、LPDDR4X設定、および周波数。 - AraRT 3.0が既存のファームウェアおよびXenパススルーを通じた動作をサポートしているかどうか。 Re: AraRT 3.0 x86: Lenovo Ara240 8GB configuration and Linux 6.12 driver issues 公式ウェブサイトでAra240 16GB M.2モジュール用のAraRT-x86 BSPリンクを試してみましたか? Re: AraRT 3.0 x86: Lenovo Ara240 8GB configuration and Linux 6.12 driver issues ありがとう。AraRT 3.0 x86-64ユーザー空間ツールを試してみました。私のカードはLenovo FRU 5C50W32071、8 GB LPDDR4X、PCI 1e58:0002 rev 02です。リンク先のBSPはこのFRUをサポートしていますか?もしそうなら、サポートされているリリース、Linux/カーネルバージョン、正確な8GBのボード構成、そして読み取り専用検出テストを共有してください。Qubes/Xenではデバイスが列挙を行いますが、ゲストは互換性のあるブリッジウィンドウがないためBAR0、2、4を請求できません。私は16GB構成を適用しておらず、カードの書き込みも行っていません。
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i.MX95 Android 15: 88W8987 Bluetooth UART timeout and shared clock-strap/UART RX pin issue Dear NXP Support Team, Following Weidong’s recommendation, we are opening a new ticket for Bluetooth bring-up on our i.MX95 platform. Wi-Fi is now working, but we need guidance on restoring Bluetooth UART communication while maintaining the correct reference-clock selection during reset. 1. Hardware and software configuration Host board: NXP i.MX95 19×19 EVK, B0 Wireless module: u-blox JODY-W263-00B, based on 88W8987, connected through M.2 Key-E BSP: Automotive Android 15.0.0_2.1.0 Kernel: 6.12.23 Wi-Fi interface: SDIO through uSDHC3 Bluetooth interface: LPUART5, exposed as /dev/ttyLP4 Wi-Fi driver: NXP mwifiex from automotive-15.0.0_2.1.0, release 537.p9 Firmware: sduart8987_combo.bin from the corresponding Android BSP firmware repository Firmware version: 16.92.21.p151.4 Firmware size: 628,200 bytes We intend to continue with the recommended SDIO + UART configuration. 2. Wi-Fi activation failure and switch observation Previously, the module was detected over SDIO and firmware transfer completed, but firmware activation failed with: Fail to poll firmware status: firmwarestat=0xf005 FW failed to be active in time! During investigation, NXP advised that 88W8987 GPIO[8]/UART_SOUT is sampled during reset to select the reference clock: LOW: 38.4 MHz HIGH: 26 MHz This signal also serves as the Bluetooth UART TX output during normal operation and connects to the host LPUART5 RX input. On our EVK, the relevant connection is: Module Bluetooth TX → M.2 J24 pin 22 → R607 → BT_UART5_RXD → R17 → SW1 contacts 7–8 → host LPUART5 RX Our repeatable observation is: SW1 contacts 7–8 ON during cold boot: Wi-Fi firmware activation fails with 0xf005. SW1 contacts 7–8 OFF during cold boot: Wi-Fi initializes successfully and is operational. We also tested the suggested host RX pad pull-down configuration: IMX95_PAD_DAP_TDI__LPUART5_RX 0x51e However, the earlier tests did not resolve the failure with SW1 contacts 7–8 ON. The running device tree we subsequently extracted showed RX pad configuration 0x31e, so we would appreciate guidance on the complete configuration and when it takes effect during boot/reset. 3. Bluetooth failure with the working Wi-Fi configuration Keeping SW1 contacts 7–8 OFF allows Wi-Fi to work, but it also disconnects the module Bluetooth TX from the host UART RX. We therefore expect Bluetooth initialization to fail because the host cannot receive controller responses. Bluetooth is tested through ADB because the board has no connected display. The installed vendor configuration is: mchar_port = /dev/ttyLP4 baudrate_fw_init = 3000000 The vendor library defaults baudrate_bt to 3000000. UART firmware download is disabled by default; the current configuration relies on the combo firmware loaded through the Wi-Fi driver. The Bluetooth vendor HAL reports version 009.030 and successfully opens the UART device: bt_vnd_init --- BT Vendor HAL Ver: 009.030 --- mchar_port set to /dev/ttyLP4 baudrate_fw_init is set to 3000000 open uart port successfully, fd=6, mchar_port=/dev/ttyLP4 However, the Bluetooth stack remains in BLE_TURNING_ON and eventually aborts: Can't start stack, last instance: starting HciHal During close/recovery, the vendor library also reports: Read hci complete event failed timed out Failed to read HCI RESET CMD response! The source configuration sequence begins with an HCI Reset command. Opening the UART device succeeds, but successful controller communication has not been established. 4. Guidance requested Could you please advise on the following? How should this shared clock-configuration/Bluetooth UART signal be handled on i.MX95? We need the module TX/host RX line LOW during reset for 38.4 MHz selection, followed by a connected, functional UART receive path during normal operation. What is the recommended configuration for SW1 contacts 7–8 and the LPUART5 RX pad? Should the switch remain ON with a specific pad configuration, or is an additional board-level change required? At which boot stage must the pull-down be applied? Is the Linux device-tree setting sufficient, or must U-Boot, System Manager/SCMI pin control, or another earlier initialization stage configure this pad before module reset is released? Please provide the recommended power/reset and pin-control sequence, including any required handling of W_DISABLE2#/Bluetooth enable, to ensure correct clock sampling and subsequent UART operation. Please confirm the Bluetooth configuration for the BSP-provided sduart8987_combo.bin: initial UART baud rate, operating baud rate, RTS/CTS flow control, and any required wake/sleep settings or vendor configuration entries. Is there a validated DTS/patch and Bluetooth vendor configuration for an 88W8987 module on this BSP? If available, please share the reference configuration and module part number used for validation. We investigated the SDIO-SDIO alternative, but understand from Weidong that those specialized packages are outdated and have not kept pace with kernel upgrades. We have not validated an SDSD firmware on this target and would like to resolve the issue using the standard SDIO + UART architecture. We can provide full Bluetooth logs, the running device tree, schematic excerpts, and oscilloscope measurements of the shared strap/UART line during reset and Bluetooth initialization. Please advise which measurement points and timing conditions would be most useful. Thank you for your continued support in enabling Wi-Fi. We would appreciate your guidance on completing Bluetooth bring-up while preserving the working Wi-Fi configuration. Best regards, Rakesh Kumar Thakur Re: i.MX95 Android 15: 88W8987 Bluetooth UART timeout and shared clock-strap/UART RX pin issue Dear @Rakesh_Kumar_Thakur , Please change  baudrate_fw_init = 3000000 to baudrate_fw_init = 115200 Then try. Thanks, Regards, weidong Re: i.MX95 Android 15: 88W8987 Bluetooth UART timeout and shared clock-strap/UART RX pin issue Dear @Rakesh_Kumar_Thakur , Please confirm if baud rate is fixed in your wifi/bt module with u-blox. if the fixed baud rate is 115200, try the configuration: mchar_port = /dev/ttyLP4 baudrate_fw_init = 115200 If the fixed baud rate is 3000000, use the configuration mchar_port = /dev/ttyLP4 baudrate_fw_init = 3000000 Then try it. I will have time to test it next week. you can try it first. BYW,I'm not quite sure I understand your operation. To turn Wi-Fi off and back on, you can simply do it through Android. There is no need to operate the SW1 switch on the board. Thanks, Best Regards, Weidong Re: i.MX95 Android 15: 88W8987 Bluetooth UART timeout and shared clock-strap/UART RX pin issue Subject: i.MX95 / JODY-W263: Baud-rate test results and request for a permanent solution without manual SW1 switching Dear Weidong, Thank you for your support. We tested your recommendation to change baudrate_fw_init from 3000000 to 115200. Below are the results and the remaining boot-time issue. We need a permanent solution for our next week’s integration activities, so your guidance on the required configuration or patch would be appreciated. Platform Board: NXP i.MX95 19×19 EVK, B0 Module: u-blox JODY-W263-00B / 88W8987, M.2 Key-E BSP: Automotive Android 15.0.0_2.1.0 Kernel: 6.12.23 Bluetooth Vendor HAL: 009.030 Wi-Fi interface: SDIO through uSDHC3 Bluetooth interface: UART5, /dev/ttyLP4 Firmware: sduart8987_combo.bin Switch under investigation: SW1, switch section 4, contacts 7–8, on the Bluetooth UART RX path toward the host. 1. Boot with SW1 contacts 7–8 ON Wi-Fi firmware activation fails: Fail to poll firmware status: firmwarestat=0xf005 FW failed to be active in time! WLAN: Fail download FW with nowwait: 0 Bluetooth also fails to reach the ON state. We have applied the recommended Linux RX pad configuration: IMX95_PAD_DAP_TDI__LPUART5_RX 0x51e We extracted the running device tree and verified that this value is present and referenced by the enabled UART5 node. However, the switch-ON boot issue remains. 2. Working sequence with initialization baud rate 3000000 The following sequence allows Wi-Fi and Bluetooth to operate: Keep SW1 contacts 7–8 OFF before power-on. Power on the board and allow firmware initialization to complete. Confirm: [12.738590] WLAN FW is active [12.954531] wlan: Driver loaded successfully Disable Bluetooth and confirm STATE_OFF. With the board running, physically turn SW1 contacts 7–8 ON. Enable Bluetooth. With: baudrate_fw_init = 3000000 baudrate_bt = 3000000 we obtained: wait-for-state:STATE_ON: Success enabled: true state: ON Wi-Fi remained connected to P3-Devices, with IP address 10.17.36.30, supplicant state COMPLETED, and network status VALIDATED. Bluetooth scanning and pairing had also worked previously using this manual switch sequence. In the latest 3M comparison run, Bluetooth ON and the Wi-Fi connection were confirmed. 3. Test of your recommended initialization baud rate 115200 We rebuilt and flashed the vendor/super images and matching board-specific AVB metadata with: mchar_port = /dev/ttyLP4 baudrate_dl_image = 115200 iSecondBaudrate = 3000000 baudrate_fw_init = 115200 baudrate_bt = 3000000 Both the deployed configuration and HAL logs confirmed that 115200 was used. We followed the same sequence: boot with contacts 7–8 OFF, confirm WLAN firmware active, disable Bluetooth, physically turn contacts 7–8 ON, and enable Bluetooth. Wi-Fi continued to operate, but Bluetooth initialization failed: baudrate_fw_init is set to 115200 open uart port successfully, fd=6, mchar_port=/dev/ttyLP4 Read hci complete event failed timed out. Total_duration = 1000 Failed to read HCI RESET CMD response! config_uart failed The adapter did not reach STATE_ON; repeated Bluetooth stack initialization failures occurred. After restoring only the initialization baud setting to 3000000 and rebuilding the images while retaining the same experimental bootloaders and kernel, Bluetooth reached ON using the same OFF-at-boot → ON-after-initialization sequence. 4. Additional boot-time experiments We also tested: Adding the RX 0x51e configuration to the U-Boot early pinctrl hog. An experimental SCMI pinctrl-driver change to include a mux request for the zero-offset DAP_TDI pin. The original driver condition, if (mux_ofs), skips the mux request for this pin because its mux offset is zero. These experiments did not resolve the switch-ON boot failure. We have not yet confirmed through early serial logs when the configuration is applied or whether the SCMI request succeeds. We therefore do not consider these changes proven fixes. Request for a permanent solution The manual switch sequence is useful for debugging, but it is not suitable for normal operation. We need Wi-Fi and Bluetooth to initialize reliably with SW1 contacts 7–8 left ON throughout power-on and runtime, without user intervention. Could you please review these results and provide: The correct initialization baud rate for JODY-W263 / 88W8987 with this combo firmware, given that 115200 failed and 3000000 succeeded in our comparison. The required pin configuration and module power/reset sequence to maintain the correct GPIO[8]/UART_SOUT strap state during initialization while preserving UART operation afterward. The appropriate implementation location—System Manager, SPL/U-Boot, Linux pinctrl/MMC power sequencing, or a hardware change. A specific patch or validated configuration for our board/BSP, including any required GPIO polarity, reset timing, or pin-ownership changes. Please also confirm whether the zero-offset mux handling in the SCMI pinctrl driver is intentional for i.MX95. We can provide the complete successful and failed logs, running device tree, source diffs, and SW1 photographs. Please let us know which additional early-boot traces you require. Thank you for helping us move from the working manual sequence to a reliable permanent solution. Best regards, Rakesh Kumar Thakur Re: i.MX95 Android 15: 88W8987 Bluetooth UART timeout and shared clock-strap/UART RX pin issue Dear Weidong, Thank you for your reply and for offering to test this next week. We checked the u-blox JODY-W2 System Integration Manual, UBX-18068879, revision R14: Page 17 documents the default UART baud rate as 3000000. Section 2.4.2, page 29, states that the baud rate after firmware loading is 3000000, and that other supported rates can be configured using the dedicated HCI baud-rate command. Therefore, the documented default is 3M; the UART is not described as permanently restricted to this rate. Our tests also support the following configuration: mchar_port = /dev/ttyLP4 baudrate_fw_init = 3000000 baudrate_bt = 3000000 With WLAN firmware active and the UART path connected, initialization at 115200 repeatedly timed out waiting for the HCI Reset response. Restoring 3000000 allowed Bluetooth to reach enabled: true, state: ON, while Wi-Fi remained connected. I would also like to clarify the physical switch operation. We are not operating SW1 to toggle Wi-Fi ON/OFF. According to the i.MX95 EVK baseboard schematic, SPF-87753-B, sheet 4, we operate SW1 section 4, contacts 7–8, on this path: Host JTAG_TDI / LPUART5_RX ↔ SW1 contacts 7–8 ↔ R17 (49.9 Ω) ↔ BT_UART5_RXD toward M.2. Here, R17 is the board resistor reference. It is separate from the u-blox document revision R14. Board resistor R14 belongs to the different CTS channel. Our observed behavior is: Contacts 7–8 ON before power-on: WLAN firmware activation fails with firmwarestat=0xf005. Contacts 7–8 OFF before power-on: WLAN firmware initializes successfully. After firmware initialization, contacts 7–8 turned ON: Bluetooth initializes at 3M, and Wi-Fi remains connected. The recommended Linux RX pull-down configuration is already applied: IMX95_PAD_DAP_TDI__LPUART5_RX 0x51e We verified this value and the enabled UART5 node’s reference in the running device tree. However, the manual switch sequence is still required. Android Wi-Fi toggling does not physically disconnect/reconnect this UART signal path. The remaining problem is therefore reliable initialization with SW1 contacts 7–8 left ON throughout boot and runtime. Could you please investigate the required early pin configuration and module power/reset sequence, and advise whether the permanent solution requires a System Manager, U-Boot, Linux, or hardware change? We can provide the schematic excerpt, switch photographs and early serial logs for your testing. Best regards, Rakesh Kumar Thakur Re: i.MX95 Android 15: 88W8987 Bluetooth UART timeout and shared clock-strap/UART RX pin issue Dear @Rakesh_Kumar_Thakur , OK, understood. Sorry , I ignored the switch. Yes, if you want to use LPUART5 on M.2,  need to enable all LPUART5 signals through SW1. Because LPUART5 signals are multiplexed through these JTAG PADs. But SW1 doesn't affect system boot.   The configuration ,  IMX95_PAD_DAP_TDI__LPUART5_RX 0x51e is only needed to be configured in linux device tree. Not needed in u-boot device tree. Thanks, Regards, weidong Re: i.MX95 Android 15: 88W8987 Bluetooth UART timeout and shared clock-strap/UART RX pin issue Dear Weidong, Thank you for clarifying the SW1 routing and that the RX pull-down configuration is required only in the Linux device tree. Could you please confirm whether this configuration alone is the complete fix for the 88W8987 initialization issue on both Linux and Automotive Android 15.0.0_2.1.0? IMX95_PAD_DAP_TDI__LPUART5_RX 0x51e This setting is already applied and verified in our running Android device tree. However, our observed behavior remains: SW1 contacts 7–8 ON before power-on: WLAN firmware activation fails with firmwarestat=0xf005. Contacts OFF before power-on: WLAN firmware activates successfully. Contacts turned ON after firmware activation: Bluetooth initializes at 3M, and Wi-Fi remains connected. To clarify, our issue concerns WLAN firmware activation, rather than the i.MX95 system boot itself. Have you verified Wi-Fi and Bluetooth initialization from a cold power-on with all required SW1 sections left ON throughout, on both Linux and Automotive Android? Please share the tested module part number, BSP versions, and any additional patches or power/reset sequencing changes required. Our goal is reliable initialization without manually operating SW1. Best regards, Rakesh Kumar Thakur
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imx95-evk: NETC on cortex M7 Hi list, According to AN15047 'i.MX 95 Dual-Ethernet on M7 and A55 - Rev. 1.0 — 19 May 2026', i'm trying to use NETC0 on cortex-m7. The chapter '5 Implementation' section 1.b describes how you can affect NETC2 to A55 non-secure cores and NETC0 to cortex-m7. I downloaded the repository https://github.com/nxp-imx/imx-sm.git (hash:eec2328, tag: lf-6.18.37-2.1.0) and take a to *configs/mx95evk.cfg* to update it according to the former chapter. But there are inconsistencies especially concerning the items 'NETC_ECAM0' and 'NETC_ECAM2' which are available in the documentation but *not* in the repository. The file's *configs/mx95evk.cfg* history doesn't provide any reference to NETC_ECAM0 or NETC_ECAM2 i.e 'git log -S NETC_ECAM2' or 'git log -S NETC_ECAM0' return nothin... Do you know where i can find consistent information to define NETC0 to A55 and NETC2 to cortex-m7 please? Can you provide a file *configs/mx95evk.cfg* which is correct for this configuration please? I'm supposed to include the generated build/mx95evk/m33_image.bin to a yocto build with the manifest imx-6.12.49-2.2.0.xml. Is the tag lf-6.18.37-2.1.0 the right one for imx-sm? Thanks.
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imx95-evk:皮层 M7 上的 NETC 大家好, 根据AN15047 “i.MX 95 双以太网在 M7 和 A55 上 - 修订版 1.0 — 2026 年 5 月 19 日”,我正在尝试在 cortex-m7 上使用 NETC0 。 “5 实现”章节 1.b 节描述了如何将 NETC2 应用于 A55 非安全内核,以及如何将 NETC0 应用于 cortex-m7。 我下载了仓库https://github.com/nxp-imx/imx-sm.git (hash:eec2328, tag: lf-6.18.37-2.1.0)然后打开*configs/mx95evk.cfg*文件,根据前一章的内容进行更新。 但存在一些不一致之处,特别是关于“NETC_ECAM0”和“NETC_ECAM2”这两个项目,它们在文档中可用,但在存储库中*不可用* 。 文件*configs/mx95evk.cfg*历史记录中没有提供任何关于 NETC_ECAM0 或 NETC_ECAM2 的引用,即“git log -S NETC_ECAM2”或“git log -S NETC_ECAM0”没有任何返回结果…… 请问您知道哪里可以找到关于NETC0对应A55以及NETC2对应cortex-m7的统一信息吗? 请提供文件 *configs/mx95evk.cfg*请问哪种配置才是正确的? 我应该将生成的 build/mx95evk/m33_image.bin 添加到带有清单 imx-6.12.49-2.2.0.xml的yocto 版本中。 标签lf-6.18.37-2.1.0哪个型号适合 imx-sm? 谢谢。
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S32プラットフォーム上のS32 Design Studioバージョン3.4のライセンスが期限切れになりました。 私のS32 Design Studio(S32プラットフォーム用)v.3.4の有効期限が切れました。 アクティベーションコードの有効期限を延長していただけますか? S32デザインスタジオ バージョンv.3.4 注文番号: S32DS-3-4_188376977 発注番号 ライセンス総数: 101 アクティベーションコード:7EEF-99B6-BDC8-8692 Re: S32平台S32 Design Studio 3.4版本的许可证已过期。 こんにちは、 お客様のS32DSライセンスが延長されました。以前のコードを使用して、S32DSを再度有効化してください。
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IMX95-EVK:Cortex M7上のNETC こんにちは、 AN15047『i.MX 95 Dual-イーサネット on M7 and A55 - Rev. 1.0 — 2026年5月19日』によると、Cortex-m7でNETC0を使おうとしています。 第5章「実装」セクション1.bでは、NETC2からA55非セキュアコア、NETC0からcortex-m7への影響方法が説明されています。 リポジトリhttps://github.com/nxp-imx/imx-sm.git (ハッシュ: eec2328、タグ: lf-6.18.37-2.1.0) をダウンロードしました。そして、 *configs/mx95evk.cfg*に移動して、前の章に従って更新します。 しかし、特にドキュメントにはあるもののリポジトリ には存在しない「NETC_ECAM0」と「NETC_ECAM2」という項目に関して矛盾があります。 ファイルの内容は*configs/mx95evk.cfg* です。履歴には NETC_ECAM0 または NETC_ECAM2 への参照が一切ありません。つまり、「git log -S NETC_ECAM2」または「git log -S NETC_ECAM0」を実行しても何も返されません。 NETC0からA55、NETC2からcortex-m7までを定義するための一貫した情報をどこで見つけられますか? ファイルを提供できますか *configs/mx95evk.cfg*この構成の場合、どちらが正しいでしょうか? 生成されたビルド/mx95evk/m33_image.binを 、マニフェストimx-6.12.49-2.2.0.xml付きのYoctoビルドに含めるべきです。 タグはlf-6.18.37-2.1.0ですか?imx-smに最適なのはどれですか? ありがとうございます。
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AraRT 3.0 x86: Lenovo Ara240 8GB configuration and Linux 6.12 driver issues Host: Lenovo ThinkCentre neo Ultra, 12W2CTO1WW NPU FRU: 5C50W32071, described by Lenovo as 8 GB LPDDR4X PCI ID: 1e58:0002, revision 02 Runtime: AraRT 3.0 Linux x86-64, running in a Debian 13 HVM under Qubes/Xen. Guest: Debian 13, Linux 6.12.113, Qubes/Xen PCI passthrough PCI passthrough detects the device; no NPU driver is currently bound. Driver source: nxp-imx-support/uiodma-driver Driver Commit: 962d11df1a9334e851f1f8a5b00f7e8960609e6a, required callback-signature changes to compile on Linux 6.12.113 My sincere request to the community to help me with the following as soon as, please: - A maintained x86 driver compatible with my kernel, addressing IRQ cleanup and eventfd validation. - The correct board name, rank, DDR configuration file, LPDDR4X settings, and frequency for this FRU. - Whether AraRT 3.0 supports its existing firmware and operation through Xen passthrough. Re: AraRT 3.0 x86: Lenovo Ara240 8GB configuration and Linux 6.12 driver issues have you try AraRT-x86 BSP link for Ara240 16GB M.2 Module at official website? Re: AraRT 3.0 x86: Lenovo Ara240 8GB configuration and Linux 6.12 driver issues Thanks. I have tried the AraRT 3.0 x86-64 userspace tools. My card is Lenovo FRU 5C50W32071, 8 GB LPDDR4X, PCI 1e58:0002 rev 02. Does the linked BSP support this exact FRU? If so, please share the supported release, Linux/kernel version, exact 8 GB board configuration and a read-only detection test. Under Qubes/Xen the device enumerates but the guest cannot claim BARs 0, 2 and 4 because there is no compatible bridge window. I have not applied the 16 GB configuration or flashed the card.
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AraRT 3.0 x86:联想 Ara240 8GB 配置和 Linux 6.12 驱动程序问题 主机:联想ThinkCentre neo Ultra,12W2CTO1WW NPU FRU:5C50W32071,联想将其描述为 8 GB LPDDR4X PCI ID:1e58:0002,版本 02 运行时:AraRT 3.0 Linux x86-64,运行于 Qubes/Xen 下的 Debian 13 HVM 中。 访客系统:Debian 13,Linux 6.12.113Qubes/Xen PCI 直通 PCI直通检测到设备;当前未绑定NPU驱动程序。 驱动程序来源:nxp-imx-support/uiodma-driver 驱动程序提交:962d11df1a9334e851f1f8a5b00f7e8960609e6a,需要修改回调签名才能在 Linux 6.12.113 上编译。 我恳请社区尽快帮助我解决以下问题: - 维护良好的 x86 驱动程序,与我的内核兼容,解决 IRQ 清理和 eventfd 验证问题。 - 此 FRU 的正确板名称、等级、DDR 配置文件、LPDDR4X 设置和频率。 - AraRT 3.0 是否支持其现有固件并通过 Xen 直通进行操作。 Re: AraRT 3.0 x86: Lenovo Ara240 8GB configuration and Linux 6.12 driver issues 您是否尝试过在官方网站上下载适用于 Ara240 16GB M.2 模块的 AraRT-x86 电路板支持包。 链接? Re: AraRT 3.0 x86: Lenovo Ara240 8GB configuration and Linux 6.12 driver issues 谢谢。我试用了 AraRT 3.0 x86-64 用户空间工具。我的显卡是 Lenovo FRU 5C50W32071,8 GB LPDDR4X,PCI 1e58:0002 rev 02。链接的 电路板支持包。 是否支持此 FRU?如果可以,请分享支持的版本、Linux/内核版本、确切的 8 GB 板配置以及只读检测测试。在 Qubes/Xen 下,设备可以枚举,但访客无法声明 BAR 0、2 和 4,因为没有兼容的桥接窗口。我还没有应用 16GB 配置,也没有刷写存储卡。
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imx95 CRA こんにちは、NXPさん EUのCRA(感染症証明書)を移植する必要があります。移植に関する公式文書はどこで入手できますか?(リンクを教えていただけますか?) Linux Re: imx95 CRA こんにちは、 @yrj さん CRAは直接移植可能なソフトウェアコンポーネントではなく、製品が遵守しなければならないサイバーセキュリティ規制です。 i.MXプラットフォーム上でCRA(カナダ歳入庁)の要件を実装する場合は、以下のリソースを優先的に活用することをお勧めします。 1. NXP公式CRA特別ページへのエントリー このページにある「ドキュメント」セクションには、アプリケーションノート、ホワイトペーパー、トレーニング資料が掲載されているほか、セキュアブート、セキュアアップデート、鍵管理などのセキュリティ機能と規制要件との関連性についても説明されています。   2. i.MXプラットフォーム アプリケーションノート このドキュメントでは、i.MX 93 を活用して OEM が CRA 要件を満たすことを支援する方法について説明します。 3.製品全体のコンプライアンス実施に関するホワイトペーパー このセクションでは、セキュリティ製品の設計とライフサイクルに関するコンプライアンス要件を紹介します。BSPや特定のセキュリティ機能だけに焦点を当てるのではなく、まず製品レベルの実装フレームワークを確立するのに適しています。 4. EU公式実施ガイドライン 規制発行機関による実施ガイドラインには、欧州委員会のガイダンス、よくある質問(FAQ)、製造業者の義務、適合性評価、脆弱性報告義務などが含まれます。製品が満たすべき要件を判断する際には、これらのEU公式文書に基づいて判断する必要があります。 よろしくお願いします、 志明 Re: imx95 CRA こんにちは@Zhiming_Liu おっしゃる通りです。私の説明は単純すぎました。 ドキュメントに従って、uboot、イメージ、およびimx95-xxx.dtbに署名と検証を行いました。 私の質問は、rootfsも署名する必要があるかどうかです。rootfsの署名に関する情報はまだ見つかっていません。これは、rootfsは署名する必要がないということでしょうか? Re: imx95 CRA こんにちは、 @yrj さん 以下のドキュメントを参照してください:10.5.5 CAAMハードウェアIPのないi.MXプラットフォームでのDM-Cryptの使用 https://www.nxp.com/docs/en/user-guide/UG10163.pdf よろしくお願いします、 志明 Re: imx95 CRA こんにちは、 @yrj さん ファイルシステムは通常、dm-verityを使用します。ファイルシステムの保護を有効にするには、次のドキュメントを参照してください。https ://www.nxp.com/docs/en/application-note/AN15078.pdf よろしくお願いします、 志明 Re: imx95 CRA こんにちは@Zhiming_Liu dm-verityは読み取り専用ですが、 dm-cryptのドキュメントはありますか?
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i.MX 93 – 预构建的 Ubuntu/Debian Linux 镜像和定制载板支持 您好,NXP支持团队, 我正在评估 i.MX 93 平台在 EVSE 应用方面的性能,并发现了EVSE-IMX93 开发套件。 我想澄清一下可用的 Linux 镜像及其与潜在的定制载板设计的兼容性。 我们的目标是使用 MCIMX93-SOM,并基于 NXP 原有的载板设计开发一款简化的定制载板。我们将保留相同的SOM连接器和引脚分配,同时移除未使用的外围设备和电路。 由于我对 i.MX 处理器平台和基于 Yocto 的开发还比较陌生,我正在寻找一个简单易用的 Linux 解决方案来入门,然后再进行自定义。 请问您能否澄清以下问题? 是否有适用于 i.MX 93 的现成 Ubuntu 或 Debian 13 (Trixie) 镜像?最好是通用服务器/最小 Linux 镜像。 这个镜像可以直接下载并刷入microSD卡来启动板,而无需Yocto构建吗? 提供的镜像是否支持标准的 Linux 功能,例如apt 、Python 3、SSH、systemd 和网络功能? 它是否支持CAN/CAN-FD (SocketCAN)、Wi-Fi、以太网和 MQTT ?是否可以使用apt安装 Mosquitto 等软件包? 在我们保留原有SOM连接器和相关硬件连接的前提下,能否将相同的预构建镜像用于我们提出的定制载板?是否只需要更改设备树或配置? 如果有这样的镜像文件,能否分享一下直接下载链接、支持的板信息和安装说明? 我们的目标是将 i.MX 93 用作运行 EVerest 框架和其他 EVSE 应用软件的通用 Linux 平台,同时避免最初维护 Yocto 构建的需要。 谢谢你的帮助。 此致敬礼 加内什·巴格瓦特
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DSP56F807PY80E: ADC reading differs from expected 2048 counts at 1.6 V input Hello NXP Community, I am troubleshooting an ADC offset issue on a board using the DSP56F807PY80E. The following voltages are measured at the device pins: Pins Function Measured voltage 102–109 ANA0–ANA7 inputs 1.60 V 99 and 110 VREF and VREF2 3.20 V 88, 100 and 111 VDDA 3.30 V For a single-ended conversion with no offset correction, I expect approximately 2048 counts, since the input voltage is half the reference voltage: ADC count = (1.60 / 3.20) × 4096 = 2048 However, the ADC readings differ from this expected value. Could someone please advise: Which ADC configuration and offset registers should I check? Could the difference be related to how the ADC result register is read or shifted? What is the recommended procedure to reset or reinitialize the ADC and verify its offset? Any guidance or example initialization code would be appreciated. Thank you for your support. Re: DSP56F807PY80E: ADC reading differs from expected 2048 counts at 1.6 V input Hello @Hari0369 , Thanks for the detailed information. Your calculation is correct for an ideal 12-bit conversion. With a 1.60 V input and a 3.20 V reference, the expected result is about 2048 counts. The first thing I suggest checking is how the ADC result is read. On the DSP56F807, the 12-bit ADC result is stored in ADRSLT bits 14–3. With no offset applied, 2048 counts would appear as about 0x4000 in the raw ADRSLT register. So please shift the raw result right by 3 bits before comparing it with 2048: ADC value = ADRSLTn >> 3 For your test condition, you should see approximately: Raw ADRSLT value : 0x4000 After >> 3       : 0x0800 = 2048 I also suggest checking the following ADC settings: - Check ADLST1/ADLST2 and make sure the correct analog input is selected. - Check ADCR1.CHNCFG and make sure single-ended operation is selected. - Check ADSDIS and make sure the sample slot you are using is enabled. - Check the corresponding ADOFS register. For this test, please set the offset to 0x0000. - Check ADCR2 and make sure the ADC clock and sampling configuration are correct. - Make sure the ADRSLT register you read matches the sample slot you configured.   For a clean test, I suggest using only one ADC channel. First, stop the ADC and wait until ADSTAT.CIP indicates that the ADC is idle. Then disable the unused sample slots and configure one known channel. Set the corresponding ADOFS register to 0x0000 and enable only the sample slot you want to test. After that, start one conversion and save the raw ADRSLT value. Then shift this value right by 3 bits and compare the result with the expected ADC count.   If the result is still different from expected, could you please send us the following values? - ADCR1 - ADCR2 - ADLST1/ADLST2 - ADSDIS - The corresponding ADOFS value - The raw ADRSLT value These values should help us determine whether the difference comes from the result format, ADC configuration, offset setting, or the analog input path. Hope it helps. BR Celeste Re: DSP56F807PY80E: ADC reading differs from expected 2048 counts at 1.6 V input Hi @Celeste_Liu, Thank you for sharing the details and troubleshooting suggestions. I have used the same firmware to program approximately 500 DSP controllers. Most units operate as expected, but around 10 units show ADC readings that differ from the expected count under the same test conditions. I understand that the datasheet specifies an ADC offset voltage range of −90 mV to +10 mV, with a typical value of −25 mV. Could you please clarify whether resetting or reinitializing the DSP or ADC could bring the reading closer to the expected 2048 counts at a 1.60 V input and 3.20 V reference? If so, could you please share the recommended procedure? Thank you for your support. Re: DSP56F807PY80E: ADC reading differs from expected 2048 counts at 1.6 V input Hello @Hari0369 , Thanks for the additional information. Reinitializing the ADC can help rule out an ADC configuration or state issue, but it normally will not change the inherent ADC offset of the device. The datasheet specifies an ADC offset voltage from -90 mV to +10 mV, with -25 mV typical. With VREF = 3.20 V, 1 LSB is approximately 0.781 mV, so some difference from the ideal 2048 counts may be expected. For the affected units, I suggest the following check: Stop the ADC and wait until ADSTAT.CIP indicates that the ADC is idle. Reinitialize the ADC with the same configuration used on the normal units. Make sure the corresponding ADOFS register is set to 0x0000. Perform several conversions and compare the averaged result before and after reinitialization. Repeat the test after a complete power cycle. If the same units consistently show the same offset, please send us the actual ADC counts from one normal unit and one affected unit at 1.60 V input and 3.20 V reference. We can then compare the difference with the ADC specification. BR Celeste
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S32K376NHT1MJBST:适用的功率估算器和单电源电流数据 你好, 请问您能否提供适用于 S32K376NHT1MJBST 的功率估算工具和供电电流数据? S32K-PET 是否支持这种特定衍生物?应该使用哪些工具和设备数据集版本?如果不支持,NXP 目前推荐的方法是什么? 对于采用外部 NMOS V11 稳压器配置的外部供电 V15,应如何将报告的需求分配给 V15、V11、VDD_HV_A/B 和其他模拟/偏置电源?请明确哪些项目包含在内,哪些项目不包含在内,特别是调节器损耗、共享核心/锁定步进需求、I/O 负载和外围电流,以免重复计算。 哪些适用的公共文件、数据或表征方法涵盖了最坏情况下的供电电流与电压/温度的关系,以及RESET、启动、唤醒和时钟/模式变化期间的峰值?请区分典型/平均估价和保证限额,并说明其适用条件。 已审核公开的PET页面和设置指南。他们的家族级支持清单和初始平均功率范围并未明确指出具体的衍生品或所有实物供应贡献。我们寻求的是适用的资源和方法,而不是没有明确操作规范的特定应用的当前结果。 如果这些信息不公开,请指出相应的公开资料或支持途径。 谢谢!
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Battery pack active balancing solution Hello, I couldn't find a solution for active battery pack balancing on the website, only a demonstration video of a battery energy storage solution. I also couldn't find any related articles on the forum. Do you have any recommendations? Thank you. Re: 电池包主动均衡方案 That's too outdated. Active balancing should be the future trend for new energy sources. Re: 电池包主动均衡方案 Hi Bob We don't manufacture active balancing ICs, and there's not much information available on this topic. The attached file is an older app note and hopefully will be helpful.
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i.MX95: neutron_perf.sh で NPU 負荷が 100% と誤って表示される (perf_counters 行はバイト単位で読み取られます) こんにちは、 i.MX95では、neutron_perf.sh(eiq-examples-npu-utils、UG10166セクション8.4.5.1)が、実際の負荷が約60%であるにもかかわらず、NPU負荷が100%と表示されることがあります。 環境 - 基板: IMX95LPD5EVK-19 - BSP: LF_6.18.20_2.0.0 (neutron_perf.sh は lf-6.18.37_2.1.0 と同じです) - eIQ Neutron SDK 3.2.3 繁殖のステップ 1. MobileNetモデルを、neutron-compilerでimx95用に変換します(TensorFlow Liteの例フォルダ内のTensorFlow Liteフォルダ内のmobilenet_v1_1.0_224_quant.tflite)。 2. ボード上で、変換したモデルと背景にNeutron Delegateをbenchmark_modelして同時にneutron_perf.shを実行します。 3. 実際の負荷は約60%ですが、60秒間に100%と表示されたことが11回ありました。 原因 1.debugfsのperf_countersファイルはシーク可能ではないため、bashの「read」コマンドは1バイトずつ読み込みます。ドライバ関数perf_counters_read()はすべての読み取り呼び出しで回線を再構築するため、1行が異なるモーメントの値を混ぜ、一部の値は切れます。私たちのテストでは、「read」がついた300件中52件が破損し、「cat」で300件中0件が壊れました。 2. 32ビットカウンターが最大値に達すると、ドライバはそれを0にリセットします。スクリプトは負の差の絶対値を取り、これが100%となります。 提案された修正案(テスト済み:同じテストで100%成功しなかった) 1. 行全体を一度に読み込み(例えば cat の場合)、それを変数に分割します。 2. NACTの差が負の場合は、絶対値を取る代わりに32乗の2を加えます。 必要ならパッチを共有できます。 ドライバ側では、perf_countersにseq_fileを使うことで原因1(未確認)も防げる可能性が高いです。 注:修正後も、NACTが最大値に達するたびに(負荷が60%の場合、約7秒ごと)、NPU負荷は1インターバル低下します。これは、次の読み取りでリセットされるまでNACTがそこで停止するためです。 質問 1.これは既知の問題ですか? 2. 修正はFUTUREのBSPリリースに含まれることはCANか? よろしくお願いします。 Re: i.MX95: neutron_perf.sh shows false 100% NPU Load (perf_counters line is read byte by byte) こんにちは、 2週間返信がなかったので、念のためご連絡いたしました。 レポートの確認を容易にするため、提案された修正案をパッチファイル(neutron_perf_fix.patch.txt)として添付しました。neutron_perf.sh の 2 行だけを変更します。最初の投稿で説明したとおりです。 1. cat コマンドで perf_counters の行全体を一度に読み込み、それを変数に分割します。 2. NACTの差が負の値の場合は、絶対値を取る代わりに2の32乗を加えます。 このパッチは、GitHub の nxp-imx/eiq-example リポジトリ (ブランチ lf-6.18.20_2.0.0) にある npu_utils/neutron_perf.sh を対象としています。これはUG10166(i.MX Machine Learning ユーザー's Guide)第8.4.5.1節で説明されているスクリプトです。 https://www.nxp.com/docs/en/user-guide/UG10166.pdf NXPの誰かが、私の最初の投稿の2つの質問を確認してもらえますか? 1.これは既知の問題ですか? 2. この問題はFUTUREのBSPリリースでCAN修正でしょうか?添付のパッチはあくまで提案です。例えばドライバ側の別の修理も問題ありません。 よろしくお願いします。
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