iMXR1176 SDK 25.09.00 Manifest 3.15.0
Goal
I am acquiring data from an LTC2164 16-bit ADC on an i.MX RT1176. The data path is:
LTC2164 (full-rate CMOS output) → FlexIO2 (parallel RX) → eDMA → external SDRAM
Hardware setup
- LTC2164 configured in full-rate CMOS output mode, clocked by an external 100 MHz oscillator (so 100 MSPS, 16-bit parallel).
- ADC data outputs D0–D15 connected to GPIO_AD_00 … GPIO_AD_15.
- ADC CLKOUT+ connected to GPIO_AD_30, used as the FlexIO timer clock (external pin clock source).
Software setup
- FlexIO2 configured as a parallel receiver, data latched into shifter 7; shifters 7->0 are chained so that 32 bytes are buffered before the DMA request is asserted.
- eDMA triggered by kDmaRequestMuxFlexIO2Request0Request1, using two TCDs in ping-pong (scatter/gather) mode. An interrupt is raised on each major loop completion, i.e. every 16384 samples.
- FlexIO2 functional clock: 120 MHz.
- Bus clock (eDMA / SEMC side): 240 MHz.
Problem
At 100 MSPS, 16384 samples should take 163.84 µs. Measuring the time between two consecutive DMA interrupts (GPIO toggle + scope), I consistently get 338 µs, i.e. a factor of ~2.06.
This corresponds to an effective sustained rate of about 48 MSPS, which suggests the bottleneck is on the FlexIO side rather than the ADC or the SDRAM.
Questions
- Is there a documented maximum shift clock frequency for FlexIO in parallel receive mode on the RT1176? I could not find any such figure in the RM or the datasheet.
- When the timer clock source is an external pin, what is the required ratio between the FlexIO functional clock and the external shift clock? My FlexIO clock (120 MHz) is only 1.2× the incoming 100 MHz clock — is that sufficient, or does the input synchronization logic require 2× or 4×?
- Given the almost exact ×2 ratio I observe, could this come from the FlexIO timer decrementing on both edges of the clock (TIMCMP convention), meaning my timer compare value effectively halves the throughput?
Any guidance on the maximum realistic sustained throughput of FlexIO + eDMA on this part would be very helpful, since this determines whether I need to move to a different peripheral or an external FIFO.
Thanks in advance.
Hello, thank you for your reply. I was indeed able to achieve the desired performance, but only by exceeding the maximum recommended clock frequency for the Flexio peripheral; specifically, instead of configuring the clock at 120 MHz, a clock speed greater than 200 MHz is required to achieve 100 MSps acquisition, whereas a 120 MHz configuration results in missed clock edges. The problem is that, even though it works at 200 MHz (despite the Reference Manual specifying a 120 MHz maximum), I have no guarantee of reliable operation under varying temperature conditions or across different production batches.
Hello @azed38,
Please keep in mind that when an external pin is used as the clock source, a small synchronization latency is introduced. According to Section 67.3.3.2 of the RM, this latency can range from 0.5 to 1.5 FlexIO clock cycles:
Regarding the maximum throughput achievable with FlexIO and DMA, there is not a performance test for the FlexIO and DMA. However, you may find the AN12686 useful, as it demonstrates a parallel communication implementation using FlexIO and DMA, this may provide guidance relevant to your use case.
BR
Habib
Hello @azed38,
I noticed that you are already receiving support through another channel regarding this topic, so the support will continue there to keep all communication centralized. I would only like to add that operating FlexIO beyond its maximum frequency specifications could cause unexpected behaviors affecting your end application. Based on the information provided in Table 15-4 "Clock Roots" of the RM, I recommend using a maximum frequency of 120 MHz.
BR
Habib