RT1170 NVCC_XXX power sequence and unsued IO banks Hello, 1 - Im asking whether is it safe to power down unused IO banks NVCC_XXX while the DCDC_IN and Pswitch are ON(cores also are ON), given that none of the unused IO bank pins are driven externally. 2 - Also whether is it ok to keep an IO bank ON to maintain IO state, while the other banks off? Thanks in advance Re: RT1170 NVCC_XXX power sequence and unsued IO banks Hello @Marwan, I understand that you are considering disconnecting the power supply of an unused power group. Is my understanding correct? The best practice is to keep the corresponding NVCC_xxx supply powered and leave the unused GPIOs floating. However, the RT1170 includes a flexible power architecture that allows certain domains to be powered down to reduce overall power consumption. I recommend consult the AN13148, which provides a detailed explanation of the RT1170 power architecture and the low-power architecture design. AN13104 is also a useful reference, as it provides useful information about the power domains and LP states.
Additionally, if you are developing a custom board, I highly recommend see the Hardware Development Guide for the MIMXRT1160/1170. This document provides information about board layout recommendations and design checklists to ensure first-pass success and avoid board bring-up issues. BR Habib Re: RT1170 NVCC_XXX power sequence and unsued IO banks Appreciate your reply and references, That's correct I would like to keep some IO bank off if not used, Although it is not clearly mentioned that it is not recommended, this is what I understand between the lines of the referred documents. Regarding the second question: What about making the IO bank always on (to maintain the IOs state and not to be driven externally) while the DCDC_IN and DCDC_PSWITCH are off(grounded), (all domains are off except SNVS and the IO banks), is it ok? The MCU is not the host, hence why I ask this is to prevent the IOs to be driven externally while the MCU in SNVS mode. Kind regards, Marwan Re: RT1170 NVCC_XXX power sequence and unsued IO banks Hello @Marwan,
Thank for the clarification.
To help me better understand your question, could you please clarify me what you referring when you mention "making the IO bank always on"? Are you referring to keeping the associated NVCC_xxx supply rail continuously powered for each I/O bank?
The best practice is to keep the corresponding NVCC_xxx supply powered and leave the unused GPIOs floating. I highly recommend use the Setpoint feature since it makes the power mode switch simpler and safer.
Regarding the possibility of keeping only the SNVS supply active while disabling the DCDC. If your application requires to use the M7 and does not use an external PMIC. Disabling the DCDC is not possible, since the M7 resides in the WAKEUPMIX domain, which is powered by VDD_SOC_IN and is directly supplied by the DCDC, as mentioned in the Chapter 2 "RT1170 Power Domains" of AN13104.
If your goal is to minimize power consumption, you may consider using Setpoints to transition the device into a low-power state while keeping only the SNVS domain powered, please refer to the table 4.1.5 "Typical power mode supply currents" of the datasheet to see different Setpoint configurations.
Additionally, AN13104 includes a practical example demonstrating how configure a Wakeup source. You may find the chapter 4.9 "Wakeup source configuration", useful as a reference for your implementation.
Finally, regarding to maintain the IO states, the SSARC could be useful. As default if the power mix which the peripheral belongs to is powered down, the peripheral configuration is lost and cannot be used directly until it is reinitialized. But with the SSARC you can save the registers of functional modules in memory before power-down and restores the registers from memory after the module is powered on, as mentioned the chapter 4.14 "Peripherals state after wakeup" of the AN13104. You can find an SDK example which shows the peripheral functionality called "ssarc_software_trigger_cm7" that you could take as reference.
BR Habib Re: RT1170 NVCC_XXX power sequence and unsued IO banks Hello @Marwan, I understand that you plan to use an external PMIC. Is my understanding correct?
In that case, please refer to the AN13213, which describes how to interface an external PMIC with the RT1170, specifically the PF5020, the PMIC recommended in the chapter 3.2 "Using External PMIC" of the Hardware Development Guide for the MIMXRT1160/1170. In this app note the recommended connections are the following:
Habib_MS_1-1784839522098.png
I would also recommend reviewing Tables 2 and 3 of the Hardware Development Guide, as they provide useful guidance on external PMIC usage as well as recommendations related to the SNVS domain.
Additionally, you may find the SDK example power_mode_switch_bm_pmic_rt1xxx_core0 helpful. This example demonstrates the use of an external PMIC together with setpoint configurations to transition between different low-power states. Please take a look at the README files for details about how the example works.
Finally, I recommend reviewing chapter 4.13 "Peripheral State in a Low-Power Mode" of AN13104, which explains the behavior of peripherals when the device is in low-power state.
BR Habib Re: RT1170 NVCC_XXX power sequence and unsued IO banks Thanks for further explanation, kindly check the attached diagram: power diagram.png My goal is to go for SNVS mode(everything after the switch is off), and keep NVCC_XX also on to maintain state of other circuitry, is this possible or it will cause damage to the RT1170 MCU? I know that by keeping NVCC_XX on, I need to properly configure the IOs to prevent extra leakage currents. Kind regards and appreciate your assistance. Re: RT1170 NVCC_XXX power sequence and unsued IO banks No I will not use external PMIC the shared block diagram is good for me, I just need to ensure that NVCC_XXX power can be ON while DCDC_IN and is off (grounded) in when MCU is in SNVS mode. is this possible? Kind regards Re: RT1170 NVCC_XXX power sequence and unsued IO banks Hello @Marwan, Yes, the NVCC_xxx rails can remain powered from an external supply, as shown in Figure 14-2, "Power Architecture" of the RM:
Habib_MS_1-1785189559143.png
However, please keep in mind that in this configuration the DCDC supply must also remain present, as it provides power to the WAKEUPMIX domain, where the CM7 resides. Additionally, please ensure that the power-up sequence described in Section 4.2.1 "Power Supplies Requirements and Restrictions" of the datasheet is correctly implemented to avoid any unexpected behavior.
Finally, I highly recommend see the Hardware Development Guide for the MIMXRT1160/1170. This document contains important design guidelines, layout recommendations, and hardware checklists that can help ensure a successful board design and avoid potential bring-up issues.
BR Habib Re: RT1170 NVCC_XXX power sequence and unsued IO banks So what I understand, is that it is not recommended to power some IO Banks ON and leave the Others OFF. Also, it is better to power everything down and keep SNVS bank on for better power consumption at sleep. Thanks for your effort
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