How to get MCLK with 11289600Hz on IMX8MP platform We are working IMX8MP with one Audio codec ES8388, I want to use MCLK with 11289600Hz to play 44.1Khz audio, I use the following setting in device tree (assigned-clock-rates = <11289600>;) sai3 { #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; assigned-clocks = <&clk IMX8MP_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; assigned-clock-rates = <11289600>; clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; fsl,sai-mclk-direction-output; status = "okay"; }; after compile and deploy it to target imx8mp board, i get mclk with 11234743Hz. cat /sys/kernel/debug/clk/clk_summary audio_pll1_ref_sel 1 1 0 24000000 0 0 50000 Y      audio_pll1 1 1 0 393216000 0 0 50000 Y           audio_pll1_bypass 1 1 0 393216000 0 0 50000 Y                audio_pll1_out 1 1 0 393216000 0 0 50000 Y                      sai3 1 1 0 11234743 0 0 50000 Y                             sai3_root 1 1 0 11234743 0 0 50000 Y                                       sai3_mclk1_sel 1 1 0 11234743 0 0 50000 Y                                               sai3_mclk1_clk 1 1 0 11234743 0 0 50000 Y the questions is how to get MCLK with 11289600Hz on IMX8MP platform? i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: How to get MCLK with 11289600Hz on IMX8MP platform glad to hear this, sorry for forgetting to tell you at first,  any other issues, pls contact us again Re: How to get MCLK with 11289600Hz on IMX8MP platform Hi @joanxie  Thank you for reply. I change  assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; it solved my problme. audio_pll2_ref_sel 1 1 0 24000000 0 0 50000 Y         audio_pll2 1 1 0 361267200 0 0 50000 Y                 audio_pll2_bypass 1 1 0 361267200 0 0 50000 Y                         audio_pll2_out 1 1 0 361267200 0 0 50000 Y                                 sai3 1 1 0 11289600 0 0 50000 Y                                         sai3_root 1 1 0 11289600 0 0 50000 Y                                                 sai3_mclk1_sel 1 1 0 11289600 0 0 50000 Y                                                         sai3_mclk1_clk 1 1 0 11289600 0 0 50000 Y Re: How to get MCLK with 11289600Hz on IMX8MP platform forgot to say, try to change the parent clock from pll1 to pll2, change assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; to assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; Re: How to get MCLK with 11289600Hz on IMX8MP platform cat /sys/kernel/debug/clk/clk_summary audio_pll1_ref_sel 1 1 0 24000000 0 0 50000 Y      audio_pll1 1 1 0 393216000 0 0 50000 Y           audio_pll1_bypass 1 1 0 393216000 0 0 50000 Y                audio_pll1_out 1 1 0 393216000 0 0 50000 Y                      sai3 1 1 0 11234743 0 0 50000 Y                             sai3_root 1 1 0 11234743 0 0 50000 Y                                       sai3_mclk1_sel 1 1 0 11234743 0 0 50000 Y                                               sai3_mclk1_clk 1 1 0 11234743 0 0 50000 Y it is same with before. I need the sai3_mclk1_clk to be 11289600. Re: How to get MCLK with 11289600Hz on IMX8MP platform after you change the clock driver, what's your dump clock? let me check it, is it the same? Re: How to get MCLK with 11289600Hz on IMX8MP platform Thank you for your reply. I noticed that your link is about the lvds, does it same with the audio clk? I do the following patch, drivers/clk/imx/clk-pll14xx.c @@ -64,6 +64,17 @@ static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = { PLL_1443X_RATE(650000000U, 325, 3, 2, 0), PLL_1443X_RATE(594000000U, 198, 2, 2, 0), PLL_1443X_RATE(519750000U, 173, 2, 2, 16384), +PLL_1443X_RATE(650000000U, 325, 3, 2, 0), +PLL_1443X_RATE(594000000U, 198, 2, 2, 0), +PLL_1443X_RATE(519750000U, 173, 2, 2, 16384), +PLL_1443X_RATE(393216000U, 262, 2, 3, 9437), +PLL_1443X_RATE(361267200U, 361, 3, 3, 17511), +PLL_1443X_RATE(245760000U, 328, 4, 3, 0xae15), +PLL_1443X_RATE(225792000U, 226, 3, 3, 0xcac1), +PLL_1443X_RATE(122880000U, 328, 4, 4, 0xae15), +PLL_1443X_RATE(112896000U, 226, 3, 4, 0xcac1), +PLL_1443X_RATE(61440000U, 328, 4, 5, 0xae15), +PLL_1443X_RATE(56448000U, 226, 3, 5, 0xcac1), +PLL_1443X_RATE(49152000U, 393, 3, 6, 0x374c), +PLL_1443X_RATE(45158400U, 241, 2, 6, 0xd845), +PLL_1443X_RATE(40960000U, 109, 1, 6, 0x3a07), }; the result is same, no change. I noticed that the above is 112896000, not 11289600, one is 112896+ three zero, my request clk is  112896+two zero, do i need to caculated one new rate with 11289600 and add it to imx_pll1443x_tbl? Re: How to get MCLK with 11289600Hz on IMX8MP platform I post the formula for pll and how to calculate in the document, maybe you can refer to that,  different lvds support on imx8mp - NXP Community after add new pll, you can dump the clock to check if it works or not, if still failed, pls post the patch and clock here Re: How to get MCLK with 11289600Hz on IMX8MP platform Thank you for your reply. I'm not good at that, can you guide me to know how to do that? I am using kernel 5.15 now,  linux-imx/drivers/clk/imx/clk-pll14xx.c at lf-5.15.y · nxp-imx/linux-imx · GitHub static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = { PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384), PLL_1443X_RATE(650000000U, 325, 3, 2, 0), PLL_1443X_RATE(594000000U, 198, 2, 2, 0), PLL_1443X_RATE(519750000U, 173, 2, 2, 16384), PLL_1443X_RATE(393216000U, 262, 2, 3, 9437), PLL_1443X_RATE(361267200U, 361, 3, 3, 17511), }; I checked the kernel 5.15 kernel and found there is no 11289600 which is in the kernel 6.6, just need to add the following line will be ok? PLL_1443X_RATE(112896000U, 226, 3, 4, 0xcac1), the struct in kernel 6.6 static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = { PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384), PLL_1443X_RATE(650000000U, 325, 3, 2, 0), PLL_1443X_RATE(594000000U, 198, 2, 2, 0), PLL_1443X_RATE(519750000U, 173, 2, 2, 16384), PLL_1443X_RATE(393216000U, 262, 2, 3, 9437), PLL_1443X_RATE(361267200U, 361, 3, 3, 17511), PLL_1443X_RATE(245760000U, 328, 4, 3, 0xae15), PLL_1443X_RATE(225792000U, 226, 3, 3, 0xcac1), PLL_1443X_RATE(122880000U, 328, 4, 4, 0xae15), PLL_1443X_RATE(112896000U, 226, 3, 4, 0xcac1), PLL_1443X_RATE(61440000U, 328, 4, 5, 0xae15), PLL_1443X_RATE(56448000U, 226, 3, 5, 0xcac1), PLL_1443X_RATE(49152000U, 393, 3, 6, 0x374c), PLL_1443X_RATE(45158400U, 241, 2, 6, 0xd845), PLL_1443X_RATE(40960000U, 109, 1, 6, 0x3a07), }; Re: How to get MCLK with 11289600Hz on IMX8MP platform you need add the clock in the table imx_pll1443x_tbl, currently the parent clock is 393216000U, so you only can get 11234743Hz https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/drivers/clk/imx/clk-pll14xx.c

Additional question for unused GPIO pins for SC16IS752 Would you please additionally confirm the existing post below? SC16IS752 - what to do with unused pins - NXP Community I would like to clarify the settings for unused GPIO0~GPIO7. The previous post states output pin: floating, input pin: external pull-up or pull-down. -Is this the same when used not only as GPIO0~GPIO7 but also as /DSRx, /DTRx, /CDx, and /RIx? -About input pin, which is recommended, pull-up or pull-down?   Is there a recommended resistance value? Re: Additional question for unused GPIO pins for SC16IS752 Hi Rong Sorry for my reply delay, My question was cleared. I appreciate that your answer. Best regards, Bata Re: Additional question for unused GPIO pins for SC16IS752 Hi, I suppose you are right. For the unused pins, if the pin is an output pin, just have it float. If the unused pin is an input pin, connect it to a pull-up or pull-down resistor, the pull up/down resistor can be 10K ohm. Either pull-up or pull-down is okay, there is not different. Hope it can help you BR XiangJun Rong

IW61x:802.11s のサポート NXPサポートの皆様へ 次の古い議論によると https://community.nxp.com/t5/Wi-Fi-Bluetooth-802-15-4/Firmware-of-88W8864-and-88W8964/m-p/1765732 https://community.nxp.com/t5/Wireless-Connectivity/Drivers-for-88W8964/m-p/997496 IW61x モジュールは、メッシュ ネットワーキングの IEEE 802.11s をサポートしていません。 これはまだ本当ですか? ありがとうございます よろしくお願いいたします。 埠頭

S32K312 uart的接收（Rx）问题 目前是初学，看到uart的example都是使用函数 Lpuart_Uart_Ip_StatusType Lpuart_Uart_Ip_AsyncReceive(const uint8 Instance, uint8 * RxBuff, const uint32 RxSize) 和函数 Lpuart_Uart_Ip_StatusType Lpuart_Uart_Ip_GetReceiveStatus(const uint8 Instance, uint32 * BytesRemaining) 来实现uart的Rx来获取或者读取数据，这里需要提前了解数据的长度并且需要等待，我们的真实场景是Rx获取的数据长度是不固定的，有没有检测Rx端有数据的中断或者函数，然后我们通过函数直接去读取，大家有这样的例子吗？

UUU and the i.MX RT1170 Evaluation Kit Is it possilbe to use use UUU (serial downloader) on the RT1170 Eval kit once the boot mode switches are set to serial download? If So what version of UUU was used?   Re: UUU and the i.MX RT1170 Evaluation Kit Hi @Snichols ,   You can use the MFG tool in your MIMXRT1170-EVK board, you can refer to this document: https://www.nxp.com/docs/en/application-note/AN12107.pdf   But, to RT, the serial download mode, I highly recommend you use the new tool, MCUXPresso secure provisional tool or the mcubootutility tool, which are more easy to use. 1. mcuxpresso secure provisional tool: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-secure-provisioning-tool:MCUXPRESSO-SECURE-PROVISIONING 2. mcubootutility tool: https://github.com/JayHeng/NXP-MCUBootUtility/releases/tag/v6.2.0 the related user manual is: https://github.com/JayHeng/NXP-MCUBootUtility Wish it helps you! If you still have question about it, please kindly let me know. Best Regards, Kerry Re: UUU and the i.MX RT1170 Evaluation Kit Apologies for not fully describing, the UUU is a serail download tool provided by NXP for its family of products I beleive. UUU (Universal Update Utility)  https://github.com/NXPmicro/mfgtools I have used the preceding tool version of this for years (sbLoader) with the imx6, it seems that tools has morphed into the UUU and I would like to use it with the RT1176 M7 core on the RT1170 Evaluation kit with its BOOTMODE pins set to serial download.  Re: UUU and the i.MX RT1170 Evaluation Kit Hi @Snichols ,    Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you.   What's the UUU full name you are meaning? UID?    Please share more information to us, thanks.    When you switch to the serial download mode, it normally will connect the PC blhost tools, and run the flashloader. flashloader is the RAM code. If you want to read some register, you also can write the code in the flashloader or the RAM code, then even the serial download mode, you still can do it. Wish it helps you! If you still have question about it, please kindly let me know. Best Regards, Kerry

i.MX93 EQoS RMIIモード、50MHzリファレンスクロック内蔵 EQoS を内部 50MHz 基準クロックで RMII モードに動作させるには何が必要ですか? u-bootのボードinit機能: static int setup_eqos_rmii(void) { struct blk_ctrl_wakeupmix_regs *bctrl = (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR; clrsetbits_le32(&bctrl->eqos_gpr, BCTRL_GPR_ENET_QOS_INTF_MODE_MASK, BCTRL_GPR_ENET_QOS_INTF_SEL_RMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN); return set_clk_eqos(ENET_50MHZ); } 関連する Linux dts パーツ imx93-14x14-evk-tja1103.dts は、この設定の基礎として使用されます。 &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos_rmii>; phy-mode = "rmii"; phy-handle = <&eqosphy>; phy-reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, <&clk IMX93_CLK_ENET>; assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; assigned-clock-rates = <100000000>, <50000000>; clk_csr = <5>; status = "okay"; mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; clock-frequency = <2500000>; eqosphy: ethernet-phy@0 { reg = <0>; compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22"; smsc,disable-energy-detect; }; }; }; ... &iomuxc { pinctrl_eqos_rmii: eqosrmiigrp { fsl,pins = < MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000057e MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e MX93_PAD_ENET2_TD2__GPIO4_IO17 0x31e >; }; ... 上記の設定では、ethernet init が imx-dwmac 428a0000 で失敗します。ethernet: dma のリセットに失敗しました 私が欠けているものについて何かヒントはありますか? Re:i.MX93 EQoS RMIIモード、内部50MHz基準クロック 小さなアップデート。DTS ファイルをこのように変更して、50MHz クロックを生成する必要があります。 assigned-clock-rates = <100000000>, <50000000>;

SJA1124 (SPI から LIN へ) こんにちは、nxpにはSPIからLINチップを提供するSJA1124があります。チップやドライバーコードなどに関する情報はありますか、もしあれば、私に提供していただけますか、ありがとうございます! 日時:SJA1124(SPIからLINへ) こんにちはトーマス、私は現在sja1124チップとの正常な通信を確立することができません。sja1124チップに適合したLinuxドライバーを開発したいのですが、Linuxドライバーが提供する機能インターフェースを介してデータを読み取ることができません、チップが正常に動作しているときに特定のピン状態があるかどうか知りたいのですが、助けてもらえますか? 日時:SJA1124(SPIからLINへ) こんにちはトーマス、あなたの返信をありがとう、私はあなたのプロンプトに従って情報の一部を得ました、それは私を大いに助けました!

SJA1124 (SPI to LIN) Hello, nxp has a SJA1124 that provides an SPI to LIN chip. Please do you have any information about the chip and driver code, etc., and if so, can you provide it to me, thank you very much! Re: SJA1124 (SPI to LIN) Hello Thomas, I am currently unable to establish normal communication with the sja1124 chip. I want to develop a Linux driver adapted to the sja1124 chip, but I can't read the data through the function interface provided by the Linux driver, I want to know if there is any specific pin state when the chip is working normally, can you help me? Re: SJA1124 (SPI to LIN) Hello Tomas, thank you for your reply, I got a part of the information according to your prompt, which helped me a lot! Re: SJA1124 (SPI to LIN) Hi, Thank you for your interest in the SJA1124 SPI-to-LIN bridge with four LIN commander channels. I believe you can find useful the following items which are available as Secure Files (requiring an NDA) on the SJA1124 website: https://www.nxp.com/products/interfaces/automotive-lin-solutions/quad-lin-commander-transceiver-with-lin-commander-controller:SJA1124 1. SJA1124 - Example software package including the example application and SJA1124 software driver. 2. AH1705 (AH504214 - SJA1124 / TJA1124 Application Hints (1.5)) PS: If your company has not signed the NDA with NXP yet, you can request it from: https://www.nxp.com/support/support:SUPPORTHOME Please make sure you are signed in to nxp.com. If you do not see these items, please click on "Request additional access" or edit your secure access rights by going to My NXP > Profile. For more information about secure access rights, please refer to this website: https://www.nxp.com/support/support/secure-access-rights:SEC-ACCESS BRs, Tomas

ASL2417 Limp home mode not working after short power interrupt Hello,  We are using an #ASL2417 in an aircraft environment to drive LEDs of the cabin lights. The IC was chosen because of its limp home capability that allows light functionality under circumstances where the CPU of the device is not available. Unfortunately, we have now discovered that the lights turn completely off after a power interrupt that is less than 20 ms and don't come back on again until a power cycle. This is happening both during normal mode and in limp home mode with the CPU not powered.  With longer power interrupts, the ASL2417 acts as expected: The lights flicker, but remain on after the interrupt. Only when the interrupt is less than 20 ms, the lights stay off.  Has anyone encountered this problem already and found a solution? The working theory at the moment is that VGG drops too far and the chip goes into the fail silent-mode from where it cannot wake up again. Even though the interrupted power supply should cause the chip to go into undervolt-mode from where it can return to operating mode (in Limp Home) after the interrupt has passed and power is applied again.  Could it be that Undervoltage requires more time to trigger than VGG_Error?  Best regards,  Thorsten Re: ASL2417 Limp home mode not working after short power interrupt Hi @T_Schroeder, Thank you for sharing your solution with the community! Re: ASL2417 Limp home mode not working after short power interrupt Thanks for the help. I have managed to trace the problem to the fact that the step down stages and VIN were separated by a diode that caused VIN to drop considerably slower in voltage than the actual supply-voltage for the step down-stages.  After I removed the diode, VIN now exactly tracks the voltage and the MOSFETs and the chip handles power interrupts from 2ms to 500 ms without problems. Re: ASL2417 Limp home mode not working after short power interrupt Hi @T_Schroeder,    Thank you for contacting NXP Support! According to the ASL2417 datasheet, the Fail Silent mode can be produced by exceeded junction temperature or a VGG error. Based on your description, the ASL2417 is entering to the fail silent mode by a VGG error, this error is set when the VGG can't be regulated and therefore, the output current is disabled. In this case, could you please share your schematic to verify these connections? Also, could you please share your selected value for Limp_timeout? Please share this information to continue with the support. Have a great day!

SJA1124（SPI至LIN） 你好，nxp有一个SJA1124，提供SPI到LIN的芯片。请问各位大侠有芯片和驱动代码等等的资料吗，如果有的话能否提供给我一下，非常感谢！ 回复：SJA1124（SPI 转 LIN） 你好，Thomas，我目前无法与 sja1124 芯片建立正常通信。我想开发一个适配sja1124芯片的Linux驱动程序，但是通过Linux驱动程序提供的函数接口无法读取数据，我想知道芯片正常工作时具体的引脚状态，能帮帮我吗？ 回复：SJA1124（SPI 转 LIN） 你好Tomas，谢谢你的回复，根据你的提示我得到了部分信息，对我帮助很大！

[LPC54S018]SPIFI Pin, Fault is generated when IOCON setting change. A fault is generated when I try to change a IOCON settings of following pins: PIO0_23 PIO0_24 PIO0_25 PIO0_26 PIO0_27 PIO0_28 Below you can see the part of the code that generate an error, or sometimes also a stuck. void main(void) { uint32_t regValue; /* Init board hardware. */ BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitBootPeripherals(); #ifndef BOARD_INIT_DEBUG_CONSOLE_PERIPHERAL /* Init FSL debug console. */ BOARD_InitDebugConsole(); #endif IOCON->PIO[0][23] = 256; IOCON->PIO[0][24] = 256; IOCON->PIO[0][25] = 256; IOCON->PIO[0][26] = 256; IOCON->PIO[0][27] = 256; IOCON->PIO[0][28] = 256; gpio_pin_config_t DUT_SYNCDAC_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PIO0_28 (pin M9) */ GPIO_PinInit(GPIO, 0U , 28U, &DUT_SYNCDAC_config); This error doesn't appear and all the FW works if select Link Applciation to RAM and run the code in debug mode. Why?   Re: [LPC54S018]SPIFI Pin, Fault is generated when IOCON setting change. Resolved! In this way! Plain load image is the solution to release the external FLASH. Re: [LPC54S018]SPIFI Pin, Fault is generated when IOCON setting change. Hi,  Thanks for the answer, I already know the architecture of LPC54S018. But It's still strange to me. The Flash is used to store the binary FW, but at the boot of MCU the binary should be loaded on the MCU RAM and at the end of the boot the microcontroller should release the FLASH Am I wrong? Thank you! Re: [LPC54S018]SPIFI Pin, Fault is generated when IOCON setting change. Hi, This is spifi flash hardware circuit. As you can see that P0_23, P0_24, P0_25, P0_26, P0_27, P0_28 pins function as SPIFI module pins, the LPC54018 does not have on-chip flash, for each instruction, it reads code from the spifi flash via above pins and execute. When you configure above pins in GPIO or whatever, the binary code reading from spifi flash is incorrect, when the wrong binary code is executed, a hardware fault will happen. In conclusion, you can not configure the P0_23, P0_24, P0_25, P0_26, P0_27, P0_28 pins in application code. Hope it can help you BR XiangJun Rong

具有内部 50MHz 参考时钟的 i.MX93 EQoS RMII 模式 要使 EQoS 在具有内部 50MHz 参考时钟的 RMII 模式下工作，需要做什么？ u-boot中的Board init函数： static int setup_eqos_rmii(void) { struct blk_ctrl_wakeupmix_regs *bctrl = (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR; clrsetbits_le32(&bctrl->eqos_gpr, BCTRL_GPR_ENET_QOS_INTF_MODE_MASK, BCTRL_GPR_ENET_QOS_INTF_SEL_RMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN); return set_clk_eqos(ENET_50MHZ); } 相关 Linux dts 部件，imx93-14x14-evk-tja1103.dts 用作此配置的基础。 &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos_rmii>; phy-mode = "rmii"; phy-handle = <&eqosphy>; phy-reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, <&clk IMX93_CLK_ENET>; assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; assigned-clock-rates = <100000000>, <50000000>; clk_csr = <5>; status = "okay"; mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; clock-frequency = <2500000>; eqosphy: ethernet-phy@0 { reg = <0>; compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22"; smsc,disable-energy-detect; }; }; }; ... &iomuxc { pinctrl_eqos_rmii: eqosrmiigrp { fsl,pins = < MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000057e MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e MX93_PAD_ENET2_TD2__GPIO4_IO17 0x31e >; }; ... 使用上述配置，以太网初始化失败，出现imx-dwmac 428a0000.ethernet: 无法重置 dma 关于我遗漏了什么有什么提示吗？ 回复：i.MX93 EQoS RMII 模式，带有内部 50MHz 参考时钟 小更新。必须像这样修改 DTS 文件才能产生 50MHz 时钟。 assigned-clock-rates = <100000000>, <50000000>;

i.MX93 EQoS RMII mode with internal 50MHz reference clock What is need to make EQoS work RMII mode with internal 50MHz reference clock? Board init function in u-boot: static int setup_eqos_rmii(void) { struct blk_ctrl_wakeupmix_regs *bctrl = (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR; clrsetbits_le32(&bctrl->eqos_gpr, BCTRL_GPR_ENET_QOS_INTF_MODE_MASK, BCTRL_GPR_ENET_QOS_INTF_SEL_RMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN); return set_clk_eqos(ENET_50MHZ); } Relevant Linux dts parts, imx93-14x14-evk-tja1103.dts used as a basis for this config. &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos_rmii>; phy-mode = "rmii"; phy-handle = <&eqosphy>; phy-reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, <&clk IMX93_CLK_ENET>; assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; assigned-clock-rates = <100000000>, <50000000>; clk_csr = <5>; status = "okay"; mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; clock-frequency = <2500000>; eqosphy: ethernet-phy@0 { reg = <0>; compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22"; smsc,disable-energy-detect; }; }; }; ... &iomuxc { pinctrl_eqos_rmii: eqosrmiigrp { fsl,pins = < MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000057e MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e MX93_PAD_ENET2_TD2__GPIO4_IO17 0x31e >; }; ... With the above configuration ethernet init fails with imx-dwmac 428a0000.ethernet: Failed to reset the dma Any hints on what am I missing? Re: i.MX93 EQoS RMII mode with internal 50MHz reference clock we also have the similar problem，no 50MHz clock output from CPU MAC，if somewhere wrong ? thanks Re: i.MX93 EQoS RMII mode with internal 50MHz reference clock Small update. The DTS file must be modified like this to produce a 50MHz clock. assigned-clock-rates = <100000000>, <50000000>; Re: i.MX93 EQoS RMII mode with internal 50MHz reference clock Hi, Thank you for your interest in NXP Semiconductor products, Please make these changes in your DTS. assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; assigned-clock-rates = <100000000>, <100000000>; Patch your BSP with the patch below and the net: stmmac: dwmac-imx: use platform specific reset for imx93 SoCs: diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c index 2fb3fbbab7e5..7e001126243f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c @@ -40,6 +40,8 @@ #define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1) #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) +#define MX93_ENET_CLK_ENET_QOS_TX_CLK_SEL_MASK GENMASK(0, 0) +#define MX93_ENET_CLK_ENET_QOS_TX_CLK_SEL (0x1 << 0) struct imx_dwmac_ops { u32 addr_width; bool mac_rgmii_txclk_auto_adj; @@ -54,7 +56,8 @@ struct imx_priv_data { struct regmap *intf_regmap; u32 intf_reg_off; bool rmii_refclk_ext; - + struct regmap *enet_clk_sel_regmap; + u32 enet_clk_sel_off; const struct imx_dwmac_ops *ops; struct plat_stmmacenet_data *plat_dat; }; @@ -133,7 +136,27 @@ imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) { struct imx_priv_data *dwmac = plat_dat->bsp_priv; - int val; + int val, err; + + struct device_node *np = dwmac->dev->of_node; + if (plat_dat->interface == PHY_INTERFACE_MODE_RMII) { + dwmac->enet_clk_sel_regmap = syscon_regmap_lookup_by_phandle(np, + "enet_clk_sel"); + if (IS_ERR(dwmac->enet_clk_sel_regmap)) + return PTR_ERR(dwmac->enet_clk_sel_regmap); + + err = of_property_read_u32_index(np, "enet_clk_sel", 1, + &dwmac->enet_clk_sel_off); + if (err) { + dev_err(dwmac->dev, + "Can't get enet_clk_sel register offset (%d)\n", + err); + return err; + } + val = MX93_ENET_CLK_ENET_QOS_TX_CLK_SEL; + regmap_update_bits(dwmac->enet_clk_sel_regmap, dwmac- >enet_clk_sel_off, + MX93_ENET_CLK_ENET_QOS_TX_CLK_SEL_MASK, val); + } diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/ freescale/imx93.dtsi index 1f25503d421c..a4f8f841e2a7 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -1079,6 +1079,8 @@ <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; assigned-clock-rates = <100000000>, <250000000>; intf_mode = <&wakeupmix_gpr 0x28>; + enet_clk_sel = <&wakeupmix_gpr 0x2C>; + clk_csr = <0>; status = "disabled"; }; Regards

IMX8MP micfil 记录数据丢失，使用 12.288Mhz 作为根时钟，速率为 48k，8 通道 你好，支持人员， 当我使用外部时钟（EXT3）作为micfil的根时钟，频率为12.288Mhz，ORS设置为8，时钟分频为4，分频后的时钟满足mic阵列传感器的要求时，在PDM采样率为48k，channel=8的情况下发现数据丢失。 但是 48k & channel=4 或 16K & channel=8 是可以的。 由于无法改变外部时钟频率，如何配置micfil进行48K&8通道音频采样？ 回复：IMX8MP micfil 记录数据丢失，当使用 12.288Mhz 作为根时钟时，速率为 48k 和 8 通道 你好@ZenJeams 对于 48k、8ch、div=4，div 无法满足 Minumum Required CLKDIV 的要求。 极低质量模式下所需的最小 CLKDIV 值为： 地板（K * CLKDIV）> = K *（10 + 43EC）/（8 * OSR）= 5.53。 我们认识到您实际上只需要 4 个通道而不是 8 个。但是您需要的通道数是 ch0、ch2、ch4 和 ch6，它们位于 8 个通道之中。 我已经制作了一个补丁来仅提取您需要的频道，请尝试一下并让我知道结果。

iMX93EVK failed to boot afte 6.1.22 Dear Sirs:   We bought a iMX93EVK from NXP. https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-93-evaluation-kit:i.MX93EVK   And for the Yocto system, I can boot the board for Linux 6.1.1_1.0.0/Linux 6.1.22_2.0.0​. However, when I try Linux 6.1.55_2.2.0 and every version later, we can not boot the imx93evk board by using the NXP pre-built firmware.   I ever try to tar the boot/root partition, and it can see the boot screen from UART, so it seems the problem is on the u-boot.   Do you know what and how we can boot it from 6.1.55? Regards, /ckhsu Re: iMX93EVK failed to boot afte 6.1.22 Hi, That is correct and to support for new BSP won't be provided. Suggest not to use old silicon revision. However, you can refer to the guide for migration. AN13997  Regards Harvey Re: iMX93EVK failed to boot afte 6.1.22 Hi Harvey:   To prevent the problem is only on eMMC, I also tru to use uuu in both 6.1.22/6.6.23 to test: In 6.1.22, I can do it without problem to flash a sd card: However, when using 6.6.23, I fail to do it with the command, and the error is same as doing in eMMC, therefore I think the problem is NOT solved even using uuu: Regards, /ckhsu Re: iMX93EVK failed to boot afte 6.1.22 Hi Harvey:   I don't think the uuu can solve the problem. I can use uuu to download the 6.1.22 but fail after this version.   This is how I can download thru uuu for 6.1.22. And for the same way for uuu test on 6.6.23 You can see the error still happen. And I found this link: https://community.nxp.com/t5/i-MX-Processors/uuu/m-p/1862107 The reporter use RevA1, and SCH RevB2. And our board is RevA and SCH RevB1 seems to be older than theirs. The support's answer is that the latest working release on that RevA silicon revision is Linux 6.1.22_2.0.0.   If this is correct, is there any way to fix the problem? Regards, /ckhsu Re: iMX93EVK failed to boot afte 6.1.22 Hi, Please use the tool uuu as reference: uuu_1.5.182  Regards Harvey Re: iMX93EVK failed to boot afte 6.1.22 Hi Harvey:   I try both linux command dd and the balenaEtcher from https://etcher.balena.io/ to fuse the NXP provided prebuilt image into the SD card.   The version of the balenaEtcher I used is 1.5.115/1.18.11 https://github.com/balena-io/etcher/releases/   The IMX93 image I used for example 6.6.23_2.0.0 are from below link https://www.nxp.com/webapp/Download?colCode=L6.6.23_2.0.0_MX93&appType=license   The IMX93 image I used for example 6.1.22_2.0.0 are from below link https://www.nxp.com/webapp/Download?colCode=L6.1.22_2.0.0_MX93-BETA&appType=license   After extract the downloaded prebuilt zip files. I use balenaEtcher to flash the file: 6.6.23_2.0.0 ==> imx-image-full-imx93evk.wic 6.1.22_2.0.0 ==> imx-image-full-imx93evk.wic Or the linux dd command where /dev/sda is my sd card device: cat imx-image-full-imx93evk.wic | sudo dd of=/dev/sda bs=1M conv=fsync status=progress Where the iMX9EVK boot switch is set to SD as SW1301 described in the quick start guide. Both dd or balenaEtcher can create the SD card and boot the 6.1.22 image for my iMX93EVK without problem.  But fail to boot for 6.1.36/6.1.55/6.6.3/6.6.23. When failing, there are NOTHING output from the console. By the way, I also try the same thing on my iMX8MP/iMX8MM boards with related prebuilt images of the version, and there is no similar problems on it. Regards. /ckhsu Re: iMX93EVK failed to boot afte 6.1.22 Hi, Please share how you flash the prebuild image and download link. and error message. Regards Harvey Re: iMX93EVK failed to boot afte 6.1.22 Dear Sirs:   I also try the 6.1.36-2.1.0 prebuilt image which also can not boot my imx93evk. Regards, /ckhsu

Code Readout protection on MKE04Z8 Dear all I have an MKE04Z8 and use Keil to program it. The MKE04Z4_DFP Package have Version 14.0.0. How can I turn on the code readout protection in the device? Here is what I tried: When I try to set the read out protection the MCU does not start anymore. I tried the following: In "startup_MKE04K4.S" I altered the flash config from /* Flash Configuration */ .section .FlashConfig, "a" .long 0xFFFFFFFF .long 0xFFFFFFFF .long 0xFFFFFFFF .long 0xFFFEFFFF .text .thumb to /* Flash Configuration */ .section .FlashConfig, "a" .long 0xFFFFFFFF .long 0xFFFFFFFF .long 0xFFFFFFFF .long 0xFFFDFFFF .text .thumb Where's my mistake?  Any help appreciated. Kind regards Christian Re: Code Readout protection on MKE04Z8 Ok, I found it... I download the code with KEIL. When I activate the Reaout Protection, Keil cannot start the debug session. It's very peculiar, but Keil then erases the code without special notice. Having done so, the CPU does not have any code to start. Probably there's some higher sense behind that behaviour. Since I usually work with Crosswoks, I did not expect that at all. Hope that helps  Chris Re: Code Readout protection on MKE04Z8 Hi, Case 1: After you download the SDK package, pls try to load/run the example code without any change, the chip is in unsecurity mode. then run a uart terminal, and check if the terminal can echo the input character. Then you can power off and connect for example  J-Link device and tools, and check if you can read code or data with J-link via SWD port case2: You can change the security to __attribute__ ((used,section(".FlashConfig"))) const struct { unsigned int word1; unsigned int word2; unsigned int word3; unsigned int word4; } Flash_Config = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFDFFFF};   then run a uart terminal, and check if the terminal can echo the input character. Then you can power off and connect for example  J-Link device and tools, and check if you can read code or data with J-link via SWD port. In the case, because the SWD is blocked, the J-Link device can not be read. Hope it can help you BR Xiangjun Rong Re: Code Readout protection on MKE04Z8 Hi XiangJun Rong I followed you advice, but I could not find an example using the Read-Out protection. Could you point me to the one you're talking about? Kind regards Chris Re: Code Readout protection on MKE04Z8 Hi, Pls download SDK from the website for FRDM-KE04 board, there is a lot of examples. Hope it can help you BR XiangJun Rong Re: Code Readout protection on MKE04Z8 Hi XiangJun Rong Thank you for your answer. When I do this, the code does not start anymore. Do you have a smple project, where it works? Kind regards Chris Re: Code Readout protection on MKE04Z8 Hi, As you change the flash configure from .long 0xFFFEFFFF to .long 0xFFFDFFFF, it means that only the FTMRE_FSEC register has chnanged, especially, SEC bits change from 10 in binary(unsecure mode) to 01 in binary(secure mode). After reset, the chip is in secure mode, the SWD port is blocked, you can not read code/data from SWD port. But the secure or unsecure mode does NOT take effect on the chip running. As a test, after you restore to unsecure mode after mass erasing and redownloading, can the KE04 run fine again? Hope it can help you BR XiangJun Rong Re: Code Readout protection on MKE04Z8 Dear XuZhang Thank you for working on the question.  As to my understanding, this is something every Product in the market needs to have. I tried different flags but I was not successful. Maybe you could ask the designer of the startup file. Just to add.. It worked in previous versions of the library. Kind regards Chris Re: Code Readout protection on MKE04Z8 hi,Chrigolat Sorry for replying to your email so late. I have received your question and will deal with it as soon as possible. BR Xu Zhang

UUU 和 i.MX RT1170 评估套件 一旦将启动模式开关设置为串行下载，是否可以在 RT1170 评估套件上使用 UUU（串行下载器）？如果是的话，使用了哪个版本的 UUU？ 回复：UUU和i.MX RT1170评估套件 抱歉没有完整描述，我相信 UUU 是 NXP 为其产品系列提供的串行下载工具。 UUU（通用更新实用程序） https://github.com/NXPmicro/mfgtools 多年来，我一直将此工具的先前版本（sbLoader）与 imx6 一起使用，看来该工具已演变为 UUU，我想将它与 RT1170 评估套件上的 RT1176 M7 核心一起使用，并将其 BOOTMODE 引脚设置为串行下载。

UUUと i.MX RT1170評価キット RT1170 Eval キットでブート モード スイッチをシリアル ダウンロードに設定した後、UUU (シリアル ダウンローダー) を使用することは可能ですか?もしそうなら、どのバージョンのUUUが使用されましたか? 日時:UUUと i.MX RT1170評価キット 完全に説明できなくて申し訳ありませんが、UUUはNXPが製品ファミリーに提供するセレイルダウンロードツールだと思います。 UUU(ユニバーサルアップデートユーティリティ) https://github.com/NXPmicro/mfgtools 私はこれの先行ツールバージョン(sbLoader)をimx6で何年も使用してきましたが、ツールがUUUに変身したようで、RT1170評価キットのRT1176 M7コアでBOOTMODEピンをシリアルダウンロードに設定したいと考えています。

Mismatch between TIMING_CFG_2 and MR2 Hello, I generated lpddr4x_timing.c file with configtool for imx93evk. I found the RD_TO_PRE of TIMING_CFG_2 is not matched with the nRTP of lpddr4x MR2. RD_TO_PRE is 15 and nRTP of MR2 is 14. What's the reason of this mismatch made by the configtool?  If the RD_TO_PRE is longer than the actual memory nRTP(auto precharge timing), do following commands also have the delay of one cycle? Does RD_TO_PRE parameter have the same effect on both lpddr4x and lpddr4? Thanks. Re: Mismatch between TIMING_CFG_2 and MR2 hi @jekim  Can I expect the future Configtool will match RD_TO_PRE with MR2 nRTP like the earlier v15?  >>>Sure, i will contact our internal Config Tool talk about this request, Maybe they will fix it on the next version. also thanks for your feedback abou this. B.R Re: Mismatch between TIMING_CFG_2 and MR2 Hi @pengyong_zhang , Engineering sample is not from the standard manufacturing process. So, it could have better or worse performance per its experiment content.  Can I expect the future Configtool will match RD_TO_PRE with MR2 nRTP like the earlier v15?  Thanks. Re: Mismatch between TIMING_CFG_2 and MR2 HI @jekim  What do you mean the engineering sample? I see, So i can not reproduce your error, also we have never meet this qquestion on our i.MX93 EVK board before. So i think its hard to find the root cause because i do not clear about your test. B.R Re: Mismatch between TIMING_CFG_2 and MR2 Hi @pengyong_zhang , As I mentioned before, it is an engineering sample. It's not easy to see it from your side. Thanks. Re: Mismatch between TIMING_CFG_2 and MR2 Hi @jekim  Actually, I still do not understand your testing process, Could you tell me more details the each test and the test result? Because, in my site, I can not reproduce your error on my i.MX93 EVK board. B.R Re: Mismatch between TIMING_CFG_2 and MR2 Hi @pengyong_zhang , The latest V16.1 also shows mismatch between RD_TO_PRE(15) and MR2 nRTP(14). The old V15 showed matched value between RD_TO_PRE(14) and MR2 nRTP(14). Thanks. Re: Mismatch between TIMING_CFG_2 and MR2 Hi @jekim  Please use our latest Config Tool v16.1 and test again. https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX B.R Re: Mismatch between TIMING_CFG_2 and MR2 Hi @pengyong_zhang , I saw the failure from an engineering sample. So, it wouldn't be seen easily from everywhere. The failure log showed different single bits every time. btw, the mismatch happens from the configtool v16. where can I  see the change history? Thanks. Re: Mismatch between TIMING_CFG_2 and MR2 HI @jekim  What is your mem test code? And what is your failed log ? Because, in our i.MX93 EVK board we have not found any error when we run the memtester.  B.R Re: Mismatch between TIMING_CFG_2 and MR2 Hi @pengyong_zhang , Yes. I'm using the NXP iMX93 EVK with the public memtester software. memtester version 4 Thanks. Re: Mismatch between TIMING_CFG_2 and MR2 HI @jekim  You are right. So it is strange at RD_TO_PRE 15, your memtester is failed. Could you please tell me more details about your test？Include test command and each test steps, maybe i can try reproduce your case on my site. PS : you are using our NXP i.mx93 EVK board?  B.R Re: Mismatch between TIMING_CFG_2 and MR2 Hi @pengyong_zhang , If every following memory accesses were delayed evenly from the expected precharge, it has no reason to make the sample failed at RD_TO_PRE 15 while pass at RD_TO_PRE 14. I assume the following active command is delayed but the following read command is not delayed. Thanks. Re: Mismatch between TIMING_CFG_2 and MR2 Hi @jekim  When RD_TO_PRE changes from 14 to 15, the DDRC will be delayed by one or two clock cycles after the DRAM is precharge. B.R Re: Mismatch between TIMING_CFG_2 and MR2 Hi @pengyong_zhang , Thank you for the clarification. The ConfigTool sets MR2 nRTP 12 and RD_TO_PRE 15 at the slower speed 1600MHz. The lpddr4x sample is not failing at the slower speed. I want to know what happens when RD_TO_PRE is 15 at 1866MHz. Could you let me know how the memory access is changed when the RD_TO_PRE is changed from 14 to 15? Thanks. Re: Mismatch between TIMING_CFG_2 and MR2 HI @jekim  There is no different about RD_TO_PRE definition between LPDDR4 and LPDDR4X, It is the RM error, i have told the DDR internal team, I think they will fix it in the next RM version. B.R Re: Mismatch between TIMING_CFG_2 and MR2 Hi @pengyong_zhang , I will try it but could you please answer about the different RD_TO_PRE definition between LPDDR4 and LPDDR4X? Thanks. Re: Mismatch between TIMING_CFG_2 and MR2 HI @jekim  Please lower the DDR frequency and try RD_TO_PRE 15  again. B.R Re: Mismatch between TIMING_CFG_2 and MR2 Hi @pengyong_zhang , As I mentioned before, I saw one failing lpddr4x sample with RD_TO_PRE 15 >>> Could you please tell more about this fail LPDDR4X sample? What test did you run or anything other situation? <<< the lpddr4x sample was failed with memtester. Does same RD_TO_PRE setting make the different effect on LPDDR4 and LPDDR4X? >>> As i know, LPDDR4 and LPDDR4X only the VDDQ is different, So i think same RD_TO_PRE setting make no different effect on LPDDR4 and LPDDR4X. <<< then, what's the reason of the imx93 reference manual shows different definition between LPDDR4 and LPDDR4x? Thanks. Re: Mismatch between TIMING_CFG_2 and MR2 HI @jekim  As I mentioned before, I saw one failing lpddr4x sample with RD_TO_PRE 15 >>> Could you please tell more about this fail LPDDR4X sample? What test did you run or anything other situation? Does same RD_TO_PRE setting make the different effect on LPDDR4 and LPDDR4X? >>> As i know, LPDDR4 and LPDDR4X only the VDDQ is different, So i think same RD_TO_PRE setting make no different effect on LPDDR4 and LPDDR4X. B.R Re: Mismatch between TIMING_CFG_2 and MR2 Hi @pengyong_zhang , As I mentioned before, I saw one failing lpddr4x sample with RD_TO_PRE 15. It becomes PASS when I change RD_TO_PRE from 15 to 14. I need to the exact meaning. I found the latest manual changed the definition as below. nRTP is read auto-precharge related while tRTP is not. Does same RD_TO_PRE setting make the different effect on LPDDR4 and LPDDR4X? Thanks. Re: Mismatch between TIMING_CFG_2 and MR2 Hi @jekim  Thanks for your picture, i have talked with our DRAM internal team, This is because our DDRC IP error, it can not be set 14, So we use the 15 value, Although it does not match the value of the MR2 register, it does not significantly affect the performance of DDR. B.R Re: Mismatch between TIMING_CFG_2 and MR2 Hi @pengyong_zhang , Please refer to the below image. Thanks. Re: Mismatch between TIMING_CFG_2 and MR2 HI @jekim  Sorry about misunderstand your question, But i have not found the nRTP of MR2. MR2 only have RL WL WLS and WR LEV, Do not have nRTP. Could you put the picture about it? B.R Re: Mismatch between TIMING_CFG_2 and MR2 Hi @pengyong_zhang , Is the any reason to use longer 15 for RD_TO_PRE while MR2 nRTP is 14?  I saw a lpddr4x sample which is failing with the mismatch while pass with the aligned 14. What does this result imply? Thanks. Re: Mismatch between TIMING_CFG_2 and MR2 Hi @jekim  There are two different timing parameters,TIMING_CFG_2 is from SOM to DDRC, MR2 is from DDRC to DDR Phy. B.R

Feed Emios PWM with DMA not working Hi, I'm trying to use Emios PWM (OPWMB mode) and feed them with DMA. I have set up a test application that has two DMA buffers configured in scatter gather mode. When the first one is finished playing, the second one is being played. Right now, I don't update the buffers but in the final application, while a buffer is being played, the other one will get updated and buffers will be played in loop. I'm using S32 Design Studio 3.5 and S32K3XX Real-Time Drivers AUTOSAR R21-11 Version 5.0.0. I've set up the DMA channel 0 in scatter gather mode with 2 elements (2 buffers of 128 elements each). The source is a buffer of int16 therefore the "source signed offset" is set to 2 and "transfer size" is also set to 2. The destination is an Emios register (IP_EMIOS_0->CH.UC[1].B) therefore, the "destination signed offset" is set to 0 and "transfer size" is set to 2. Since the source buffers have 128 elements, the "source last address adjustment" is set to -256 (128 * sizeof(int16)). The PWM is set to trigger a DMA request (Flag Event response -> EMIOS_PWM_IP_DMA_REQUEST). I've attached my test application which runs on a S32K312EVB-Q172 board. Right now, the buffers don't play in a loop, they should be played only once but they are not being played at all. I check with an oscilloscope and I don't see the PWM duty cycle changing My question is how to configure the DMAMUX to link Emios PWM with DMA channel 0? I don't see where I can configure this. Is it even possible what I'm trying to do? If not, do you have another solution to propose? Thanks for your help! Hugo Re: Feed Emios PWM with DMA not working Hi Senlent, After some tests, I figured that the ISR is called only when both buffers are played (every ~8.72 ms) on my side unlike on your oscilloscope screenshot. It seems normal to me because the "Enable Major Interrupt" check box is not set for scatter/gather channel 0. When I set it, it now works fine and the buffer is played properly. Here is the modification I made for scatter/gather configuration on both channels: I've attached the final version of my test application if someone needs to do the same thing. Thanks a lot for your help!!! It is really appreciated! Regards, Hugo Re: Feed Emios PWM with DMA not working Hi Senlent, Thank you for your answer. I want to do that to avoid having to have an interrupt at PWM frequency to write P_EMIOS_0->CH.UC[1].B. By having two buffers of 128 samples each allows me to play one buffer while updating the second. When one buffer is played, I get the ISR and then I can fill the other one with new PWM values. At the next ISR, the new values are played and then I can update the other buffer. In the sample application I provided, the PWM duty cycle values are constants but this was just for a test. I'm working from home now so I don't have an oscilloscope to test but will test tomorrow. Thanks again for your help so far! Regards, Hugo Re: Feed Emios PWM with DMA not working Hi@h_bouchard I don't know why you want to do this, I changed your configuration according to your idea And I added a PWM output as a reference comparison Re: Feed Emios PWM with DMA not working Hi Senlent, Thank you for your answer. However, that doesn't do what it should. I should get an interrupt when minor loop has done all its DMA transfers, which is set to 128 (at major loop iteration). Therefore, with a PWM period of (1 / 29296.875 KHz) * 128 transfers = 4.369067 ms. I can see on your screenshot that the period is ~3.413 us. Also, the DMA is not reading from the buffer, only the first element is read and played. I don't see the TCDx_SADDR being incremented. Any idea why? Regards, Hugo Re: Feed Emios PWM with DMA not working Hi@h_bouchard Could you please modified it like below shows. Re: Feed Emios PWM with DMA not working Hi Senlent, Thanks for your help. However, the DMA doesn't seem to work properly. The first element of the buffer is written in the B register of the eMIOS channel but the source address is not incremented and I get an interrupt twice within the PWM period while I should get one every 128 PWM period (the minor loop size is set to 256 for a 2 bytes transfer). To see that, I've added a pin toggle in the DMA ISR function. Here is a screenshot of the TCD registers and eMIOS settings: And here is a screenshot of the oscilloscope: As you can see, I get two interrupts within a few microseconds when I should get only one every 0.00436907 seconds (1 / 29296.875 KHz (PWM frenquency) * 128). Do you have any idea why? Regards, Hugo Re: Feed Emios PWM with DMA not working Hi@h_bouchard Sorry for the later reply cause we're in overload. please disable this option enable emios0_ch1->FEN otherwise it won't generate a DMA request. IP_EMIOS_0->CH.UC[1].C = (IP_EMIOS_0->CH.UC[1].C & ~(eMIOS_C_FEN_MASK)) | eMIOS_C_FEN(1); (it should be have api to enable FEN bit but i don't fimilar with MCAL API) Re: Feed Emios PWM with DMA not working Hi Senlent, Sorry, here it is. Regards, Hugo Re: Feed Emios PWM with DMA not working Hi@h_bouchard "I've updated the test firmware with the latest changes (see firmware_test2.zip)." Could you please double check it, because i did not see "firmware_test2.zip" Re: Feed Emios PWM with DMA not working Hi Senlent, Thank you for your answer. I did add the RM and set it up as you suggested: However, I'm still not able to generate DMA request from EMIOS0 CH 1. Here is my setting of the DMA channel. Both elements ID are set up the same except that Element ID 0 links to Element ID 1 and Element ID 1 links to Element ID 0 to create a double buffering which never stops. The "Enable Start" option is set for both Element ID. The DMA interrupt is triggered right after the DMA channel is configured (call to Mcl_SetDmaChannelScatterGatherConfig()). The PWM is initialized after that. Even if I comment out the PWM_Init function, the DMA interrupt is triggered which tells me that something else is triggering the DMA instead of EMIOS0 CH 1 as it is set up in "RM". Do you have any idea what else can trigger the DMA? I've updated the test firmware with the latest changes (see firmware_test2.zip). Thanks, Regards, Hugo Re: Feed Emios PWM with DMA not working Hi@h_bouchard My question is how to configure the DMAMUX to link Emios PWM with DMA channel 0?  this can be done in "RM"