Hi, I ported the FS8x_S32K144_WatchdogExample this demo in the part about SPI read and write FS85 registers, now the cycle read register M_FLAG, deviceStatus = 0xF0,readData = 0xF014. the specific errors are
Wrong number of clock cycles ( <32 or >32) and Error detected in the SPI CRC
The CRC8 uses the same function provided by DEMO, why is there an error? How to solve these two errors?
Reading register FS_STATES, readData = 0x2003, the state machine corresponding to 03 was not found.
Hello Osker
The FS_STATE =5 indicates that RSTB is not released to high, can customer check the RSTB pin level ? The OV/UV related flag registers are not active at this moment.
Any other questions, please let me know.
Brs
CIndy Wen
Hi xuxin
User should clear FS_OVUVREG_STATUS by writing all bits to '1'，if the faults are triggered again, that is real OV UV fault.
As in FS8510D3 OTP ，ABIST1 is assigned to all the monitors. So if VCOREMON or VMON1~4 reported UV, the state machine is stuck at ABIST1 state, and can not go to INIT_FS state.
VCOREMON should be connected to BUCK1， VMON1~4 should used to monitor regulators in your schematic. Please refer to the FS85 DEMO board.
Please contact local DISTI FAE for more help if debugging support is needed.
Brs
Cindy Wen
Hi Xuxin
Please read the FS_OVUVREG_STATUS register. Please check if VCOREMON is connected to BUCK1 output. Check whether the VDDIO voltage is the level defined by OTP. Check whether VMON1~4 are 0.8V.
Which part number are you using? If you are using specific OTP defined by your company , please share the OTP file to me .
Brs
Cindy Wen
I just asked my hardware engineer to measure the PGOOD and RSTB pins and both are low, the hardware engineer said that pull-up resistors have been added but did not succeed in pulling them high. Do I need to configure any registers in software next? Or is it simply a hardware issue?
Hi Xuxin
If FS state can not enter INIT_FS，I think the PGOOD/RSTB are not released due to some faults.
Please check whether the PGOOD/RSTB are released to high or not?
If they are low, please check if there is OV/UV faults on board.
Brs
Cindy Wen
Hello Cindy.
I followed your suggestion and read the following registers after writing 1 to the corresponding bit of M_FLAG, and MISO returned the data as shown, and FS_STATS is still 0x2003.
Hello Xuxin
Could you clear these below bits by writing ‘1’ to these bits and see if the faults will be triggered again. If these faults were triggered only when power on reset, we can ignore them, as they will not happen during the normal operation.
Brs
Cindy Wen
Hello, Tomas.
Here is the SPI waveform I read from the SPI waveform from FS_STATES register. 1 is CLK, 2 is CS, 3 is MOSI, 4 is MISO. the MOSI I parsed from the waveform is 0xAC,00,00,F4, and the MISO is 0x70,20,03,14. it's really not 0x2006. does it have something to do with the fact that I'm in debug mode all the time?
Hello Xuxin,
Good to know that the original error disappeared. I am not aware of the fail-safe state machine state code of 0x03. It should be indeed 0x06. Could you please share a scope shot illustrating the read of the FS_STATES register?
BRs. Tomas
After I replaced a new FS85 chip, the Wrong number of clock cycles ( <32 or >32) and Error detected in the SPI CRC disappeared. I wrote DBG_EXIT in the FS_STATES register, but when I read the FS_STATES register, readData = 0x2003, not 0x2006, what does this 03 stand for? How to enter INIT_FS state?
As shown, 1 is MOSI, 2 is CLK, 3 is CS, 4 is MISO. i read the FS_DIAG_SAFETY register, and the MOSI is 0xA8,0x00,0x00,0xF2. the MISO values are 0xF0,0x04,0x29,0xD9. 0xF2 and 0xD9 are the CRC values, which are the same as the ones i calculated with the CRC8 tool! the same as the values I calculated with the CRC8 tool.
Also, I don't know how to confirm the values in table100.
Hello Xuxin,
If you have an oscilloscope or a logic analyzer, could you please share screenshots illustrating both SPI write and read transactions? Also please double check that all SPI timing requirements as shown in Table 100 of the datasheet are met.
BRs, Tomas