2040486_en-US

[#1]

Question about LLCE clock in S32G

Hi NXP，

I am using hardware as S32G274rdb2 and have implemented bootloader to drive 3 M cores + A core according to AN13750 with the following versions of each module:
LLCE:1.0.8, RTD:4.0.2, Linux_BSP:BSP42 (kernel:5.15.158)
I initialized LLCE in the M0 core and configured the llce_pe clock to 40M (FXOSC_CLK) and configured the baud rate of LLCE_can to 250k, but the LLCE_can output clock that I captured through the oscilloscope is incorrect, what could be the reason?
Using clk dump in u-boot to get llce_can_pe clock as 0,as follows:
0                     0   |-- llce_can_pe
200000000   0   |-- llce_sys
80000000     0   |-- llce_per

thanks，

Re: Question about LLCE clock in S32G

hi，youke

Thank you for sharing your experience, and I am glad to help you, welcome to ask new ticket when you have other question.

BR

Joey

Re: Question about LLCE clock in S32G

Hi joey，

I found that in tf-a, I did not modify the clock source in the device tree. After modifying it, the LLCE clock is correct. Thank you for your support;

thanks，

Re: Question about LLCE clock in S32G

Hi joey，

I found through testing that I configured the clock source for McuCGm0ClockMux7 in the bootloader to be FXOSC_CLK 40M. After booting to the M0 core, LLCE.can output correctly;

If the output frequency of M0 core LLCEcan changes after the Linux startup of A core is completed, it is found through calculation that CAN-PE-CLK should be changed to 48M;

I have already commented out all llce clocks in TF-A (see attachment for TF-A modifications). Do you still need to modify u-boot or kernel? How to modify?

thanks

Re: Question about LLCE clock in S32G

hi,youke

Have you configured the PLL as shown in the following picture?

If you have done, and the tf-a did not start successfully after turning on the PLL clock in McuLockSettings Disable PLL, I thank it is not suitable for you. You can try unchecking the MCU control in Mux7.

In addition,  you can try turning off the clock operations for llce in tf-a, u-boot, and kernel, using the values configured in bootloader, It's a suggested way for you.

BR

Joey

Re: Question about LLCE clock in S32G

Hi joey，

1. I have followed your instructions and configured the CANP_PE-CLK of M7-0 core to 80M, and configured the MCU ->McuLockSettingDnfig.0 CANP_PE-CLK of bootloader to 80M, The CANP_PE-CLK in McuLockSettings Disable PLL is not configured because I found that tf-a did not start successfully after turning on the PLL clock in McuLockSettings Disable PLL;
After this configuration, my llce clock output still doesn't work;
2. I tried to shut down the operation of tf-a, but now the bootloader only starts M7-0/1/2 cores. However, the clock output of LLCE.can in M7-0 is still incorrect. Do you have any other troubleshooting ideas?

thanks，

Re: Question about LLCE clock in S32G

hi,youke

Thank you for your reply.

There should be an incompatibility for the llce_can_pe between the M-core and A-core, you can turn off the clock operations for llce in tf-a, u-boot, and kernel, using the values configured in bootloader.

In addition, in order to find the problem, you can try to configure CAN_PE_CLK as 40MHz in TF-A/u-boot, or set M core CAN_PE_CLK as 80Mhz as shown in the following picture.

BR

Joey

Re: Question about LLCE clock in S32G

Hi joey,

1.   I am currently using bootloader to pull up multi-core, and the initial program for M-core is IPCF. I have ported the LLCE code;
2.  I have tried to test the LLCE project of M core separately and it is available.
3.  I saw that the bootloader's sysdal module's powerUp ->SystemPowerUpConfiguration-0->DeinitList has the initialization of Mcu_initClock McuLockSetDisable PLL. I configured McuLockSetDisable PLL for Mcu ->McuLockSettingConfi and modified McuCGm0ClockMux7 as follows
4.  I followed the command in the bootloader you provided and used clk dump. I can see that llce_can_pe is 80000000. After entering the system, I tested that llce_can did not output, and the log showed that it was stuck in the Llce_fFirmware_Load function
5.  I am considering using bootloader to initialize all clocks for llce, and turning off clock operations for llce in tf-a, u-boot, and kernel, using the values configured in bootloader. Is this approach correct?

thanks，

Re: Question about LLCE clock in S32G

Hi,youke

Thank you for contacting us.

Do you have a test  that only start M Core to capture the LLCE_can output clock? Please make sure you correctly configure the mux7 of MC_CGM _0 in MCU clock setting. 

In addition, you can try to enable all LLCE clocks by referring to the attached picture.

Hope it can help you.

BR

Joey