Can I get the S32K3XX Driver? Hello, @Robin_Shen  I am currently developing firmware for the S32K314 series without using the RTD. While searching for clock drivers, I came across a response you posted and checked the project. It seems that there is a driver folder in the project, which leads me to believe that there might be drivers available for the non-RTD version. Is there any way I can get access to the drivers for each module? Re: Can I get the S32K3XX Driver? thank you for answer! Re: Can I get the S32K3XX Driver? Hi The Baremetal Example Codes used to be available for download from docstore.nxp.com. But this was before the release of S32K3 RTD and is no longer available for download and is not recommended.  Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

PCAN GUIでのFlexCANメッセージフレームS32K358 こんにちは@PetrS、 S32K358ボードからラップトップに接続されたCANバスにCANフレームを送信しようとしています。私は提供されたFlexCan_Ip_Example_S32K358を利用しました。 私は最初にループバックモードでプログラムを実行し、それが本来あるべきように機能していることがわかりました。次に、CANインスタンスのモードをノーマル/アクティブモードに変更し、フレームを送信してPCANソフトウェアで確認するという考えで変更しました。S32DSプロジェクトで行った構成に従ってCAN接続設定を設定しようとしましたが、フレームは取得されませんでした。次に、PCANソフトウェアによって提案された設定に従って、S32DSプロジェクトのCAN構成を設定しようとしましたが、DS32側からエラーが発生していました。 私は私のプロジェクトを添付しました、あなたはここで私を助けてもらえますか。CAN Tx フレームを取得できるように、FlexCAN ビットレート プロパティをどのように設定すればよいか教えてください。 Re: PCAN GUI での FlexCAN メッセージ フレームのS32K358 こんにちは @PetrS あなたが言ったように、私はPCAN GUIで送信されたデータフレームを取得しています!感謝 Re: PCAN GUI での FlexCAN メッセージ フレームのS32K358 他の利用可能なピンを構成してみましたが、それらからも何も得られません。 Re: PCAN GUI での FlexCAN メッセージ フレームのS32K358 これらのピンは、TJA1443トランシーバーを接続するため、アプリケーションに使用する必要があります。ここで何をする必要があるのか教えてください。

U-Boot がロードされる前にデバイスツリーを動的にロード 私は、工場テスト中にU-Bootのデバイスツリーを動的に選択する任務を負っています。NXP i.MX8xをベースにしたさまざまな製品バリエーションをテストし、それぞれに異なるGPIOと周辺機器があります。PCBバリアントはプロセッサに認識されていませんが、U-Bootをロード する前に 正しいデバイスツリーを選択する必要があります。 私は3つのデバイスツリーのバリエーションを持っています。 1.一般的な製品の起動とLinuxブートの基本バリアント。 2.工場テスト:バリアント1(DTS 1から継承)。 3.工場テスト:バリアント2(DTS 1からも継承)。 私はU-Bootのデバイスツリーを動的に選択する方法を探しましたが、Linux(fdt_file / fdt_config)の方法しか見つかりませんでした。U-Bootのデバイスツリーはバイナリで固定されているようです。 これを解決するためのアイデア、好みでリストされています。 1.すべてのPCBで8つのディップスイッチを使用して、正しいデバイスツリーを決定し、U-Bootコンソールを起動します。 2. U-Boot コンソールでデバイス ツリーを手動で選択し、新しいデバイス ツリーを選択した状態で U-Boot コンソールを再読み込みします。 3. UUUを使用して、テスト中に正しいdtbファイルをロードします。 NXPのAHABセキュアブートを使用していますが、何かを見落としていて、AHABのどこかでU-Bootの正しいデバイスツリーをロードできるかもしれませんか? 助けてくれてありがとう、 テイラー Re: U-Boot がロードされる前にデバイスツリーを動的にロードする これらは非常に興味深いもので、将来これを再検討する時間があれば、おそらく非常に役立つでしょう。両方のリンクをブックマークしました。助けてくれてありがとう! Re: U-Boot がロードされる前にデバイスツリーを動的にロードする それは私が期待していたことです。確認していただきありがとうございます。

S32K358 FlexCAN Message Frames in PCAN GUI Hello @PetrS, I am trying to transmit CAN frames from my S32K358 Board to a CAN bus connected to my Laptop. I have made use of the FlexCan_Ip_Example_S32K358 provided. I first ran the program in Loop-back mode and found it was working as it should be. Next, i changed the mode of the CAN instance to Normal/Active mode with the idea of just transmiting Frames and seeing it the PCAN software. I have tried setting the CAN connection settings as per the configuration i have made in my S32DS project, i did not get any frames. Then i tried setting the CAN configuration in my S32DS project as per the setting suggested by the PCAN software, i was getting errors from the DS32 side. I have attached my project, can you please help me out here. Can you please tell me how should i set the FlexCAN Bitrate properties so that i can get the CAN Tx Frames. Re: S32K358 FlexCAN Message Frames in PCAN GUI Hi @PetrS like you said, i am getting the The Transmitted dataframes in the PCAN GUI ! Thanks Re: S32K358 FlexCAN Message Frames in PCAN GUI Hi, ok, so then call port init function, install module interrupt handler properly for not pooling calls BR, Petr Re: S32K358 FlexCAN Message Frames in PCAN GUI I have tried configuring the other available pins, i am not getting anything from them as well. Re: S32K358 FlexCAN Message Frames in PCAN GUI I need to use these pins for my application as i will be connecting the TJA1443 transceiver to them. Can you tell me what needs to be done here. Re: S32K358 FlexCAN Message Frames in PCAN GUI Hi, is there a reason why you have selected FlexCAN_2 with PTC6/PTC7 pins? Do you have external CAN transceiver connected to those pins? PTC6/PTC7 are connected to I2C devices on S32K3X8EVB board so it will probably not working properly. If you need to use FlexCAN2 then select different pins to be connected with your external transceiver. Or use available one, TJA1153, connected to CAN0 or CAN1. But this transceiver needs initial configuration. BR, Petr

PFEng ドライバーを 3 つのインターフェイスで使用する LinuxのNXP PFEngドライバーで3つのSGMIIインターフェイスを使用しています。そのうちの 2 つ (PFE1 + PFE2) をロードして動作させることはできますが、3 つ目 (PFE0) はドライバーに認識されません。 「HIF0が設定されていない、スキップされました」と表示されていますが、私が知る限り、PFE0にバインドされ、他の部分と同じように設定されています。 これがデバイスツリーです。 // SPDX-License-Identifier: GPL-2.0 /* * Copyright 2022-2023 NXP * */ #include #include #include #include #include / { aliases { ethernet0 = &pfe_netif0; ethernet1 = &pfe_netif1; ethernet2 = &pfe_netif2; }; soc { pfe: pfe@46000000 { compatible = "nxp,s32g-pfe"; reg = <0x0 0x46000000 0x0 0x1000000>, <0x0 0x4007ca00 0x0 0x100>; reg-names = "pfe-cbus", "s32g-main-gpr"; #address-cells = <1>; #size-cells = <0>; interrupt-parent = <&gic>; interrupts = , , , , , ; interrupt-names = "hif0", "hif1", "hif2", "bmu", "upegpt", "safety"; resets = <&reset S32CC_SCMI_RST_PART2>; reset-names = "pfe_part"; clocks = <&clks S32G_SCMI_CLK_PFE_AXI>, <&clks S32G_SCMI_CLK_PFE_PE>, <&clks S32G_SCMI_CLK_PFE_TS>; clock-names = "pfe_sys", "pfe_pe", "pfe_ts"; nvmem-cells = <&pfe_emacs_intf_sel>, <&pfe_coh_en>, <&pfe_pwr_ctrl>, <&pfe_genctrl3>; nvmem-cell-names = "pfe_emacs_intf_sel", "pfe_coh_en", "pfe_pwr_ctrl", "pfe_genctrl3"; // serdes, phy type, instance, lane phys = <&serdes1 PHY_TYPE_XPCS 0 0>, // pfe0 connected to sgmii1, lane 0 <&serdes1 PHY_TYPE_XPCS 1 1>, // pfe1 connected to sgmii1, lane 1 <&serdes0 PHY_TYPE_XPCS 1 1>; // pfe2 connected to sgmii0, lane 1 phy-names = "emac0_xpcs", "emac1_xpcs", "emac2_xpcs"; dma-coherent; memory-region = <&pfe_reserved_bmu2>, <&pfe_reserved_rt>, <&pfe_reserved>, <&pfe_reserved_bdr>; memory-region-names = "pfe-bmu2-pool", "pfe-rt-pool", "pfe-shared-pool", "pfe-bdr-pool"; nxp,fw-class-name = "s32g_pfe_class.fw"; nxp,fw-util-name = "s32g_pfe_util.fw"; nxp,pfeng-ihc-channel = ; status = "okay"; /* MDIO on PFE0 */ pfe_mdio0: mdio@0 { compatible = "nxp,s32g-pfe-mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0>; status = "okay"; pfe_mdiob_phy0: ethernet-phy@0 { reg = <0>; ti,op-mode = ; }; }; /* MDIO on PFE1 */ pfe_mdio1: mdio@1 { compatible = "nxp,s32g-pfe-mdio"; #address-cells = <1>; #size-cells = <0>; reg = <1>; status = "okay"; pfe_mdiob_phy1: ethernet-phy@0 { reg = <0>; ti,op-mode = ; }; }; /* MDIO on PFE2 */ pfe_mdio2: mdio@2 { compatible = "nxp,s32g-pfe-mdio"; #address-cells = <1>; #size-cells = <0>; reg = <2>; status = "okay"; pfe_mdiob_phy2: ethernet-phy@0 { reg = <0>; ti,op-mode = ; }; }; /* Network interface 'pfe0' */ pfe_netif0: ethernet@10 { compatible = "nxp,s32g-pfe-netif"; status = "okay"; reg = <10>; local-mac-address = [ 00 04 9F BE EF 00 ]; nxp,pfeng-if-name = "pfe0"; nxp,pfeng-hif-channels = ; nxp,pfeng-linked-phyif = ; clocks = <&clks S32G_SCMI_CLK_PFE0_TX_SGMII>, <&clks S32G_SCMI_CLK_PFE0_TX_RGMII>, <&clks S32G_SCMI_CLK_PFE0_TX_RMII>, <&clks S32G_SCMI_CLK_PFE0_TX_MII>, <&clks S32G_SCMI_CLK_PFE0_RX_SGMII>, <&clks S32G_SCMI_CLK_PFE0_RX_RGMII>, <&clks S32G_SCMI_CLK_PFE0_RX_RMII>, <&clks S32G_SCMI_CLK_PFE0_RX_MII>; clock-names = "tx_sgmii", "tx_rgmii", "tx_rmii", "tx_mii", "rx_sgmii", "rx_rgmii", "rx_rmii", "rx_mii"; phy-mode = "sgmii"; managed = "in-band-status"; }; /* Network interface 'pfe1' */ pfe_netif1: ethernet@11 { compatible = "nxp,s32g-pfe-netif"; status = "okay"; reg = <11>; local-mac-address = [ 00 04 9F BE EF 01 ]; nxp,pfeng-if-name = "pfe1"; nxp,pfeng-hif-channels = ; nxp,pfeng-linked-phyif = ; clocks = <&clks S32G_SCMI_CLK_PFE1_TX_SGMII>, <&clks S32G_SCMI_CLK_PFE1_TX_RGMII>, <&clks S32G_SCMI_CLK_PFE1_TX_RMII>, <&clks S32G_SCMI_CLK_PFE1_TX_MII>, <&clks S32G_SCMI_CLK_PFE1_RX_SGMII>, <&clks S32G_SCMI_CLK_PFE1_RX_RGMII>, <&clks S32G_SCMI_CLK_PFE1_RX_RMII>, <&clks S32G_SCMI_CLK_PFE1_RX_MII>; clock-names = "tx_sgmii", "tx_rgmii", "tx_rmii", "tx_mii", "rx_sgmii", "rx_rgmii", "rx_rmii", "rx_mii"; phy-mode = "sgmii"; managed = "in-band-status"; }; /* Network interface 'pfe2' */ pfe_netif2: ethernet@12 { compatible = "nxp,s32g-pfe-netif"; status = "okay"; reg = <12>; local-mac-address = [ 00 04 9F BE EF 02 ]; nxp,pfeng-if-name = "pfe2"; nxp,pfeng-hif-channels = ; nxp,pfeng-linked-phyif = ; clocks = <&clks S32G_SCMI_CLK_PFE2_TX_SGMII>, <&clks S32G_SCMI_CLK_PFE2_TX_RGMII>, <&clks S32G_SCMI_CLK_PFE2_TX_RMII>, <&clks S32G_SCMI_CLK_PFE2_TX_MII>, <&clks S32G_SCMI_CLK_PFE2_RX_SGMII>, <&clks S32G_SCMI_CLK_PFE2_RX_RGMII>, <&clks S32G_SCMI_CLK_PFE2_RX_RMII>, <&clks S32G_SCMI_CLK_PFE2_RX_MII>; clock-names = "tx_sgmii", "tx_rgmii", "tx_rmii", "tx_mii", "rx_sgmii", "rx_rgmii", "rx_rmii", "rx_mii"; phy-mode = "sgmii"; managed = "in-band-status"; }; }; }; }; ドライバーがロードされたときにLinuxが出力するものは次のとおりです。 [ 1.139965] phy-s32cc-serdes 40480000.serdes: Using mode 2 for SerDes subsystem [ 1.150978] phy-s32cc-serdes 40480000.serdes: Unstable RX detected on XPCS1 [ 1.151314] phy-s32cc-serdes 44180000.serdes: Using mode 3 for SerDes subsystem [ 1.157428] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS1 [ 1.157446] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS0 ... [ 15.457853] pfeng: loading out-of-tree module taints kernel. [ 15.469032] pfeng 46000000.pfe: PFEng ethernet driver loading ... [ 15.469046] pfeng 46000000.pfe: Version: 1.3.0 [ 15.469050] pfeng 46000000.pfe: Driver commit hash: M4_DRIVER_COMMIT_HASH [ 15.469054] pfeng 46000000.pfe: Multi instance support: disabled (standalone) [ 15.469058] pfeng 46000000.pfe: Compiled by: 12.3.0 [ 15.469085] pfeng 46000000.pfe: Cbus addr 0x46000000 size 0x1000000 [ 15.469093] pfeng 46000000.pfe: nxp,fw-class-name: s32g_pfe_class.fw [ 15.469098] pfeng 46000000.pfe: nxp,fw-util-name: s32g_pfe_util.fw [ 15.469151] pfeng 46000000.pfe: netif name: pfe1 [ 15.469158] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:01 [ 15.469166] pfeng 46000000.pfe: netif(pfe1) linked phyif: 1 [ 15.469171] pfeng 46000000.pfe: netif(pfe1) mode: std [ 15.469184] pfeng 46000000.pfe: netif(pfe1) HIFs: count 1 map 02 [ 15.469192] pfeng 46000000.pfe: SGMII AN enabled on EMAC1 [ 15.469196] pfeng 46000000.pfe: EMAC1 PHY less SGMII [ 15.469204] pfeng 46000000.pfe: EMAC1 interface mode: 4 [ 15.469345] pfeng 46000000.pfe: netif name: pfe2 [ 15.469351] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:02 [[ 15.469356] pfeng 46000000.pfe: netif(pfe2) linked phyif: 2 15.469361] pfeng 46000000.pfe: netif(pfe2) mode: std [[ 15.469373] pfeng 46000000.pfe: netif(pfe2) HIFs: count 1 map 04 0[ 15.469380] pfeng 46000000.pfe: SGMII AN enabled on EMAC2 ;[ 15.469384] pfeng 46000000.pfe: EMAC2 PHY less SGMII 3[ 15.469389] pfeng 46000000.pfe: EMAC2 interface mode: 4 2[ 15.469459] pfeng 46000000.pfe: HIF channels mask: 0x0006 m[ 15.469502] pfeng 46000000.pfe: PFE port coherency enabled, mask 0x1e [ 15.469760] pfeng 46000000.pfe: Clocks: sys=300MHz pe=600MHz [ 15.469775] pfeng 46000000.pfe: Interface selected: EMAC0: 0xffffffff EMAC1: 0x4 EMAC2: 0x4 O[ 15.470473] pfeng 46000000.pfe: PFE controller reset done K[ 15.470543] pfeng 46000000.pfe: TX clock on EMAC1 for interface sgmii installed [ 15.470577] pfeng 46000000.pfe: RX clock on EMAC1 for interface sgmii installed [ 15.470629] pfeng 46000000.pfe: TX clock on EMAC2 for interface sgmii installed 15.470662] pfeng 46000000.pfe: RX clock on EMAC2 for interface sgmii installed [[ 15.470842] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34000000 0[ 15.470898] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34080000 m[ 15.470955] pfeng 46000000.pfe: assigned reserved memory node pfebufs@83200000 ][ 15.470982] pfeng 46000000.pfe: assigned reserved memory node pfebufs@835e0000 [ 15.476294] pfeng 46000000.pfe: Firmware: CLASS s32g_pfe_class.fw [45040 bytes] F[ 15.476304] pfeng 46000000.pfe: Firmware: UTIL s32g_pfe_util.fw [23252 bytes] i[ 15.476316] pfeng 46000000.pfe: [pfe_platform_master.c:3629] PFE CBUS p0x46000000 mapped @ v0xffffffc00c000000 (0x1000000 bytes) n[ 15.476324] pfeng 46000000.pfe: [pfe_platform_master.c:3634] HW version 0x101 i[ 15.476332] pfeng 46000000.pfe: [pfe_hw_feature.c:93] Silicon S32G3 s[ 15.476340] pfeng 46000000.pfe: [pfe_platform_master.c:3646] Fail-Stop mode disabled h[ 15.479186] pfeng 46000000.pfe: [pfe_platform_master.c:2783] PFE_ERRORS:Parity instance created e[ 15.479197] pfeng 46000000.pfe: [pfe_platform_master.c:2798] PFE_ERRORS:Watchdog instance created d[ 15.479203] pfeng 46000000.pfe: [pfe_platform_master.c:2814] PFE_ERRORS:Bus Error instance created [ 15.479208] pfeng 46000000.pfe: [pfe_platform_master.c:2827] PFE_ERRORS:FW Fail Stop instance created 15.479214] pfeng 46000000.pfe: [pfe_platform_master.c:2840] PFE_ERRORS:Host Fail Stop instance created [ 15.457853] pfeng: loading out-of-tree module taints kernel. [ 15.469032] pfeng 46000000.pfe: PFEng ethernet driver loading ... [ 15.469046] pfeng 46000000.pfe: Version: 1.3.0 [ 15.469050] pfeng 46000000.pfe: Driver commit hash: M4_DRIVER_COMMIT_HASH [ 15.469054] pfeng 46000000.pfe: Multi instance support: disabled (standalone) [ 15.469058] pfeng 46000000.pfe: Compiled by: 12.3.0 [ 15.469085] pfeng 46000000.pfe: Cbus addr 0x46000000 size 0x1000000 [ 15.469093] pfeng 46000000.pfe: nxp,fw-class-name: s32g_pfe_class.fw [ 15.469098] pfeng 46000000.pfe: nxp,fw-util-name: s32g_pfe_util.fw [ 15.469151] pfeng 46000000.pfe: netif name: pfe1 [ 15.469158] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:01 [ 15.469166] pfeng 46000000.pfe: netif(pfe1) linked phyif: 1 [ 15.469171] pfeng 46000000.pfe: netif(pfe1) mode: std [ 15.469184] pfeng 46000000.pfe: netif(pfe1) HIFs: count 1 map 02 [ 15.469192] pfeng 46000000.pfe: SGMII AN enabled on EMAC1 [ 15.469196] pfeng 46000000.pfe: EMAC1 PHY less SGMII [ 15.469204] pfeng 46000000.pfe: EMAC1 interface mode: 4 [ 15.469345] pfeng 46000000.pfe: netif name: pfe2 [ 15.469351] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:02 [[ 15.469356] pfeng 46000000.pfe: netif(pfe2) linked phyif: 2 15.469361] pfeng 46000000.pfe: netif(pfe2) mode: std [[ 15.469373] pfeng 46000000.pfe: netif(pfe2) HIFs: count 1 map 04 0[ 15.469380] pfeng 46000000.pfe: SGMII AN enabled on EMAC2 ;[ 15.469384] pfeng 46000000.pfe: EMAC2 PHY less SGMII 3[ 15.469389] pfeng 46000000.pfe: EMAC2 interface mode: 4 2[ 15.469459] pfeng 46000000.pfe: HIF channels mask: 0x0006 m[ 15.469502] pfeng 46000000.pfe: PFE port coherency enabled, mask 0x1e [ 15.469760] pfeng 46000000.pfe: Clocks: sys=300MHz pe=600MHz [ 15.469775] pfeng 46000000.pfe: Interface selected: EMAC0: 0xffffffff EMAC1: 0x4 EMAC2: 0x4 O[ 15.470473] pfeng 46000000.pfe: PFE controller reset done K[ 15.470543] pfeng 46000000.pfe: TX clock on EMAC1 for interface sgmii installed [ 15.470577] pfeng 46000000.pfe: RX clock on EMAC1 for interface sgmii installed [ 15.470629] pfeng 46000000.pfe: TX clock on EMAC2 for interface sgmii installed 15.470662] pfeng 46000000.pfe: RX clock on EMAC2 for interface sgmii installed [[ 15.470842] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34000000 0[ 15.470898] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34080000 m[ 15.470955] pfeng 46000000.pfe: assigned reserved memory node pfebufs@83200000 ][ 15.470982] pfeng 46000000.pfe: assigned reserved memory node pfebufs@835e0000 [ 15.476294] pfeng 46000000.pfe: Firmware: CLASS s32g_pfe_class.fw [45040 bytes] F[ 15.476304] pfeng 46000000.pfe: Firmware: UTIL s32g_pfe_util.fw [23252 bytes] i[ 15.476316] pfeng 46000000.pfe: [pfe_platform_master.c:3629] PFE CBUS p0x46000000 mapped @ v0xffffffc00c000000 (0x1000000 bytes) n[ 15.476324] pfeng 46000000.pfe: [pfe_platform_master.c:3634] HW version 0x101 i[ 15.476332] pfeng 46000000.pfe: [pfe_hw_feature.c:93] Silicon S32G3 s[ 15.476340] pfeng 46000000.pfe: [pfe_platform_master.c:3646] Fail-Stop mode disabled h[ 15.479186] pfeng 46000000.pfe: [pfe_platform_master.c:2783] PFE_ERRORS:Parity instance created e[ 15.479197] pfeng 46000000.pfe: [pfe_platform_master.c:2798] PFE_ERRORS:Watchdog instance created d[ 15.479203] pfeng 46000000.pfe: [pfe_platform_master.c:2814] PFE_ERRORS:Bus Error instance created [ 15.479208] pfeng 46000000.pfe: [pfe_platform_master.c:2827] PFE_ERRORS:FW Fail Stop instance created 15.479214] pfeng 46000000.pfe: [pfe_platform_master.c:2840] PFE_ERRORS:Host Fail Stop instance created 19.535286] pfeng 46000000.pfe: PFE_ERRORS:Fail Stop instance created [0[ 19.535290] pfeng 46000000.pfe: PFE_ERRORS:ECC Err instance created ;[ 19.535300] pfeng 46000000.pfe: BMU1 buffer base: p0xc0000000 1[ 19.535388] pfeng 46000000.pfe: BMU2 buffer base: p0x34000000 (0x80000 bytes) ;[ 19.536682] pfeng 46000000.pfe: register IRQ 76 by name 'PFE BMU IRQ' 3[ 19.536851] pfeng 46000000.pfe: Firmware .elf detected 9[ 19.536853] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x000000002bafc76d). Pool ready. m[ 19.536857] pfeng 46000000.pfe: Uploading CLASS firmware V[ 19.536865] pfeng 46000000.pfe: Selected FW loading OPs to load 8 PEs in parallel A[ 19.536866] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x00000000a2386541). Pool ready. S[ 19.556236] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" T[ 19.571482] pfeng 46000000.pfe: [FW VERSION] 1.8.0, Build: Nov 16 2023, 07:46:11 (nogitaaa), ID: 0x30 [ 19.571773] pfeng 46000000.pfe: EMAC timestamp external mode bitmap: 0 :[ 19.571814] pfeng 46000000.pfe: Uploading UTIL firmware [ 19.571819] pfeng 46000000.pfe: Selected FW loading OPs to load 1 PEs in parallel I[ 19.574246] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" n[ 19.575323] pfeng 46000000.pfe: FW feature: drv_run_on_g3 i[ 19.575328] pfeng 46000000.pfe: FW feature: jumbo_frames t[ 19.575333] pfeng 46000000.pfe: FW feature: software_vlan_table i[ 19.575337] pfeng 46000000.pfe: FW feature: timestamping a[ 19.575340] pfeng 46000000.pfe: FW feature: qos_mapping l[ 19.575344] pfeng 46000000.pfe: FW feature: core_functionality i[ 19.575348] pfeng 46000000.pfe: FW feature: extended_features z[ 19.575353] pfeng 46000000.pfe: FW feature: flexible_router e[ 19.575357] pfeng 46000000.pfe: FW feature: validate_hif_csum [ 19.575361] pfeng 46000000.pfe: FW feature: err051211_workaround P[ 19.575365] pfeng 46000000.pfe: FW feature: IPsec F[ 19.575368] pfeng 46000000.pfe: FW feature: l2_bridge_aging E[ 19.575373] pfeng 46000000.pfe: FW feature: receive_malformed s[ 19.575379] pfeng 46000000.pfe: FW feature: ptp_conf_check 19.575384] pfeng 46000000.pfe: FW feature: vlan_conf_check [[ 19.575389] pfeng 46000000.pfe: FW feature: hash_load_spread 0[ 19.575395] pfeng 46000000.pfe: FW feature: ingress_vlan m[ 19.575398] pfeng 46000000.pfe: FW feature: safety .[ 19.577825] pfeng 46000000.pfe: VLAN ID incorrect or not set. Using default VLAN ID = 0x01. [ 19.577830] pfeng 46000000.pfe: VLAN stats size incorrect or not set. Using default VLAN stats size =. [ 19.577916] pfeng 46000000.pfe: Software vlan hash table @ p0x20001278 [ 19.578088] pfeng 46000000.pfe: Fall-back bridge domain @ 0x20000a80 (class) [ 19.578092] pfeng 46000000.pfe: Default bridge domain @ 0x20000a78 (class) [ 19.579076] pfeng 46000000.pfe: Routing table created, Hash Table @ p0xc00e0000, Pool @ p0xc00e8000 () [ 19.579290] pfeng 46000000.pfe: Feature err051211_workaround: DISABLED [ 19.587357] pfeng 46000000.pfe: MDIO bus 0 enabled [ 19.593821] pfeng 46000000.pfe: MDIO bus 1 enabled [ 19.599713] pfeng 46000000.pfe: MDIO bus 2 enabled [ 19.599725] pfeng 46000000.pfe: HIF0 not configured, skipped [ 19.600089] pfeng 46000000.pfe: HIF1 enabled [ 19.600319] pfeng 46000000.pfe: HIF2 enabled [ 19.600325] pfeng 46000000.pfe: HIF3 not configured, skipped [ 19.600400] pfeng 46000000.pfe pfe1 (uninitialized): Subscribe to HIF1 [ 19.600407] pfeng 46000000.pfe pfe1 (uninitialized): Host LLTX disabled [ 19.600833] pfeng 46000000.pfe pfe1 (uninitialized): Enable HIF1 [ 19.600994] pfeng 46000000.pfe pfe1 (uninitialized): setting MAC addr: 00:04:9f:be:ef:01 [ 19.601022] pfeng 46000000.pfe pfe1 (uninitialized): PTP HW addend 0x80000000, max_adj configured to b [ 19.601031] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10s 19.535286] pfeng 46000000.pfe: PFE_ERRORS:Fail Stop instance created [0[ 19.535290] pfeng 46000000.pfe: PFE_ERRORS:ECC Err instance created ;[ 19.535300] pfeng 46000000.pfe: BMU1 buffer base: p0xc0000000 1[ 19.535388] pfeng 46000000.pfe: BMU2 buffer base: p0x34000000 (0x80000 bytes) ;[ 19.536682] pfeng 46000000.pfe: register IRQ 76 by name 'PFE BMU IRQ' 3[ 19.536851] pfeng 46000000.pfe: Firmware .elf detected 9[ 19.536853] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x000000002bafc76d). Pool ready. m[ 19.536857] pfeng 46000000.pfe: Uploading CLASS firmware V[ 19.536865] pfeng 46000000.pfe: Selected FW loading OPs to load 8 PEs in parallel A[ 19.536866] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x00000000a2386541). Pool ready. S[ 19.556236] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" T[ 19.571482] pfeng 46000000.pfe: [FW VERSION] 1.8.0, Build: Nov 16 2023, 07:46:11 (nogitaaa), ID: 0x30 [ 19.571773] pfeng 46000000.pfe: EMAC timestamp external mode bitmap: 0 :[ 19.571814] pfeng 46000000.pfe: Uploading UTIL firmware [ 19.571819] pfeng 46000000.pfe: Selected FW loading OPs to load 1 PEs in parallel I[ 19.574246] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" n[ 19.575323] pfeng 46000000.pfe: FW feature: drv_run_on_g3 i[ 19.575328] pfeng 46000000.pfe: FW feature: jumbo_frames t[ 19.575333] pfeng 46000000.pfe: FW feature: software_vlan_table i[ 19.575337] pfeng 46000000.pfe: FW feature: timestamping a[ 19.575340] pfeng 46000000.pfe: FW feature: qos_mapping l[ 19.575344] pfeng 46000000.pfe: FW feature: core_functionality i[ 19.575348] pfeng 46000000.pfe: FW feature: extended_features z[ 19.575353] pfeng 46000000.pfe: FW feature: flexible_router e[ 19.575357] pfeng 46000000.pfe: FW feature: validate_hif_csum [ 19.575361] pfeng 46000000.pfe: FW feature: err051211_workaround P[ 19.575365] pfeng 46000000.pfe: FW feature: IPsec F[ 19.575368] pfeng 46000000.pfe: FW feature: l2_bridge_aging E[ 19.575373] pfeng 46000000.pfe: FW feature: receive_malformed s[ 19.575379] pfeng 46000000.pfe: FW feature: ptp_conf_check 19.575384] pfeng 46000000.pfe: FW feature: vlan_conf_check [[ 19.575389] pfeng 46000000.pfe: FW feature: hash_load_spread 0[ 19.575395] pfeng 46000000.pfe: FW feature: ingress_vlan m[ 19.575398] pfeng 46000000.pfe: FW feature: safety .[ 19.577825] pfeng 46000000.pfe: VLAN ID incorrect or not set. Using default VLAN ID = 0x01. [ 19.577830] pfeng 46000000.pfe: VLAN stats size incorrect or not set. Using default VLAN stats size =. [ 19.577916] pfeng 46000000.pfe: Software vlan hash table @ p0x20001278 [ 19.578088] pfeng 46000000.pfe: Fall-back bridge domain @ 0x20000a80 (class) [ 19.578092] pfeng 46000000.pfe: Default bridge domain @ 0x20000a78 (class) [ 19.579076] pfeng 46000000.pfe: Routing table created, Hash Table @ p0xc00e0000, Pool @ p0xc00e8000 () [ 19.579290] pfeng 46000000.pfe: Feature err051211_workaround: DISABLED [ 19.587357] pfeng 46000000.pfe: MDIO bus 0 enabled [ 19.593821] pfeng 46000000.pfe: MDIO bus 1 enabled [ 19.599713] pfeng 46000000.pfe: MDIO bus 2 enabled [ 19.599725] pfeng 46000000.pfe: HIF0 not configured, skipped [ 19.600089] pfeng 46000000.pfe: HIF1 enabled [ 19.600319] pfeng 46000000.pfe: HIF2 enabled [ 19.600325] pfeng 46000000.pfe: HIF3 not configured, skipped [ 19.600400] pfeng 46000000.pfe pfe1 (uninitialized): Subscribe to HIF1 [ 19.600407] pfeng 46000000.pfe pfe1 (uninitialized): Host LLTX disabled [ 19.600833] pfeng 46000000.pfe pfe1 (uninitialized): Enable HIF1 [ 19.600994] pfeng 46000000.pfe pfe1 (uninitialized): setting MAC addr: 00:04:9f:be:ef:01 [ 19.601022] pfeng 46000000.pfe pfe1 (uninitialized): PTP HW addend 0x80000000, max_adj configured to b [ 19.601031] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10s Re: PFEng ドライバーを 3 つのインターフェイスで使用する @XDこのガイドは、3 つの PFE を SGMII 接続することを物理的に許可しない RDB3 のハードウェアに固有のものだと思います。私が取り組んでいるハードウェアには、チップ自体が構成をサポートしている限り、そのような物理的な制限はありません。 Re: PFEng ドライバーを 3 つのインターフェイスで使用する U-Bootには何の改造もありません。このメッセージングはU-Boot内のNXPコードから来ているため、この構成を使用できることを確認できますか? Serdes0 Lane0 : PCIe Serdes0レーン1:PFE Serdes1レーン0:PFE Serdes1レーン1:PFE Re: PFEng ドライバーを 3 つのインターフェイスで使用する ねえ@chenyin_h  はい、カスタムボードです。 私が使っているのは、 リナックス - bsp40.0-5.15.145-rt ATF - BSP40.0-2.5 Uブート - bsp40.0-2022.04 U-Boot hwconfigは、 serdes0:mode=pcie&xpcs1,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=1G,an=1;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=100;xpcs1_0:speed=1G,an=1;xpcs1_1:speed=1G,an=1 また、この設定では、u-bootが次のメッセージを表示します。 Failed to configure XPCS0_1 Failed to update XPCS1 for SerDes0 xpcs0_1 and xpcs 1_0 can't be both SGMII SerDes1 configuration will be ignored as it's invalid s32cc_serdes_phy serdes@40480000: Using mode 2 for SerDes subsystem s32cc_serdes_phy serdes@40480000: Unstable RX detected on XPCS1

在 U-Boot 加载之前动态加载设备树 我的任务是在工厂测试期间动态选择 U-Boot 的设备树。我们测试了基于 NXP i.MX8x 的各种产品变体，每种产品都有不同的 GPIO 和外围设备。处理器不知道 PCB 变体，但我需要在 U-Boot 加载之前选择正确的设备树。 我有 3 种设备树变体： 1. 一般产品启动和Linux引导的基本变体。 2. 工厂测试：变体 1（继承自 DTS 1）。 3. 工厂测试：变体 2（也继承自 DTS 1）。 我一直在寻找为 U-Boot 动态选择设备树的方法，但只找到了适用于 Linux 的方法（fdt_file/fdt_config）。U-Boot 的设备树似乎在二进制文件中固定。 解决此问题的想法（按优先顺序列出）： 1. 使用所有 PCB 上的 8 个 dip 开关来确定正确的设备树并启动到 U-Boot 控制台。 2. 在 U-Boot 控制台中手动选择设备树，然后使用选定的新设备树重新加载 U-Boot 控制台。 3.测试时使用UUU加载正确的dtb文件。 我们使用 NXP 的 AHAB 安全启动，也许我忽略了一些东西，可以在 AHAB 的某个地方为 U-Boot 加载正确的设备树吗？ 感谢您的帮助， 泰勒 回复：在 U-Boot 加载之前动态加载设备树 这些都非常有趣，如果我们将来有时间重新讨论这个问题，可能会非常有帮助。我已将这两个链接加入书签。谢谢您的帮助！ 回复：在 U-Boot 加载之前动态加载设备树 这正是我所期待的。感谢您的验证。

CLRC663 set error flag in IRQ register when writing data to NTAG210 Setup: I use the Murata Tag LXMS33HCNK-171, which uses the NTAG210_NTAG212 (NTAG210)             The reader IC is the CLRC663 .             I don't use the software library and communicate to the tag without library based on                    application note AN12657.  I am able to read the tag UID and all memory content from the tag without any errors. But when I want to write to the tag and check the IRQ register whether transmission and receive complete flag are set, the error flag is set as well. Also the data register still contains the data which should be written to the tag and not a ACK or NAK.  Between transmission start and reading the data register I have a timeout ~5 ms (I know the maximum timeout is 10 ms) but I stop waiting as soon as IRQ register reports an error.  My time delay loop is almost the same as the anticollision example from Vogtberg, Date 11.12.2019. Did I forget any additional timeouts or protocol specific details? For example in ISO15693 I have to send an EOF after a certain time delay after the the actual write command.  Because the write command is not mandatory in ISO14443-3 protocol, I can't find any further details except the timings given in the NTAG210_NTAG212  datasheet.  Kind regards  Sascha  NFC Frontend Solutions NFC Reader Library Re: CLRC663 set error flag in IRQ register when writing data to NTAG210 I was able to solve the problem above, which was caused due to wrong crc settings (I forgot to deactive crc appended to data on rx side setting for write command) which causes an crc error. Re: CLRC663 set error flag in IRQ register when writing data to NTAG210 Hello @SasWin Hope you are doing well. According to CLRC663 plus Data Sheet, Section 8.1, the bit ErrIRQ in register IRQ0 indicates an error detected by the contactless UART during receive. This is indicated by any bit set to logic 1 in register Error (refer to Section 9.6.1). Please consider that our support scope is limited to the usage of our recommended NFC Reader Library and supported MCUs from our portfolio. Implementation on third-party platforms is out of our support scope, and must be done by the user based on the information provided in CLRC663 plus family and NTAG 210/NTAG 212 product pages. Regards, Eduardo.

Using the PFEng driver with 3 interfaces I'm using three SGMII interfaces with the NXP PFEng driver in Linux. I can get two of them to load and operate (PFE1 + PFE2) but the third one (PFE0) is not being recognized by the driver. It is saying "HIF0 not configured, skipped" but it is bound to PFE0 and configured the same as the rest from as far as I can tell.  Here is the device tree, // SPDX-License-Identifier: GPL-2.0 /* * Copyright 2022-2023 NXP * */ #include #include #include #include #include / { aliases { ethernet0 = &pfe_netif0; ethernet1 = &pfe_netif1; ethernet2 = &pfe_netif2; }; soc { pfe: pfe@46000000 { compatible = "nxp,s32g-pfe"; reg = <0x0 0x46000000 0x0 0x1000000>, <0x0 0x4007ca00 0x0 0x100>; reg-names = "pfe-cbus", "s32g-main-gpr"; #address-cells = <1>; #size-cells = <0>; interrupt-parent = <&gic>; interrupts = , , , , , ; interrupt-names = "hif0", "hif1", "hif2", "bmu", "upegpt", "safety"; resets = <&reset S32CC_SCMI_RST_PART2>; reset-names = "pfe_part"; clocks = <&clks S32G_SCMI_CLK_PFE_AXI>, <&clks S32G_SCMI_CLK_PFE_PE>, <&clks S32G_SCMI_CLK_PFE_TS>; clock-names = "pfe_sys", "pfe_pe", "pfe_ts"; nvmem-cells = <&pfe_emacs_intf_sel>, <&pfe_coh_en>, <&pfe_pwr_ctrl>, <&pfe_genctrl3>; nvmem-cell-names = "pfe_emacs_intf_sel", "pfe_coh_en", "pfe_pwr_ctrl", "pfe_genctrl3"; // serdes, phy type, instance, lane phys = <&serdes1 PHY_TYPE_XPCS 0 0>, // pfe0 connected to sgmii1, lane 0 <&serdes1 PHY_TYPE_XPCS 1 1>, // pfe1 connected to sgmii1, lane 1 <&serdes0 PHY_TYPE_XPCS 1 1>; // pfe2 connected to sgmii0, lane 1 phy-names = "emac0_xpcs", "emac1_xpcs", "emac2_xpcs"; dma-coherent; memory-region = <&pfe_reserved_bmu2>, <&pfe_reserved_rt>, <&pfe_reserved>, <&pfe_reserved_bdr>; memory-region-names = "pfe-bmu2-pool", "pfe-rt-pool", "pfe-shared-pool", "pfe-bdr-pool"; nxp,fw-class-name = "s32g_pfe_class.fw"; nxp,fw-util-name = "s32g_pfe_util.fw"; nxp,pfeng-ihc-channel = ; status = "okay"; /* MDIO on PFE0 */ pfe_mdio0: mdio@0 { compatible = "nxp,s32g-pfe-mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0>; status = "okay"; pfe_mdiob_phy0: ethernet-phy@0 { reg = <0>; ti,op-mode = ; }; }; /* MDIO on PFE1 */ pfe_mdio1: mdio@1 { compatible = "nxp,s32g-pfe-mdio"; #address-cells = <1>; #size-cells = <0>; reg = <1>; status = "okay"; pfe_mdiob_phy1: ethernet-phy@0 { reg = <0>; ti,op-mode = ; }; }; /* MDIO on PFE2 */ pfe_mdio2: mdio@2 { compatible = "nxp,s32g-pfe-mdio"; #address-cells = <1>; #size-cells = <0>; reg = <2>; status = "okay"; pfe_mdiob_phy2: ethernet-phy@0 { reg = <0>; ti,op-mode = ; }; }; /* Network interface 'pfe0' */ pfe_netif0: ethernet@10 { compatible = "nxp,s32g-pfe-netif"; status = "okay"; reg = <10>; local-mac-address = [ 00 04 9F BE EF 00 ]; nxp,pfeng-if-name = "pfe0"; nxp,pfeng-hif-channels = ; nxp,pfeng-linked-phyif = ; clocks = <&clks S32G_SCMI_CLK_PFE0_TX_SGMII>, <&clks S32G_SCMI_CLK_PFE0_TX_RGMII>, <&clks S32G_SCMI_CLK_PFE0_TX_RMII>, <&clks S32G_SCMI_CLK_PFE0_TX_MII>, <&clks S32G_SCMI_CLK_PFE0_RX_SGMII>, <&clks S32G_SCMI_CLK_PFE0_RX_RGMII>, <&clks S32G_SCMI_CLK_PFE0_RX_RMII>, <&clks S32G_SCMI_CLK_PFE0_RX_MII>; clock-names = "tx_sgmii", "tx_rgmii", "tx_rmii", "tx_mii", "rx_sgmii", "rx_rgmii", "rx_rmii", "rx_mii"; phy-mode = "sgmii"; managed = "in-band-status"; }; /* Network interface 'pfe1' */ pfe_netif1: ethernet@11 { compatible = "nxp,s32g-pfe-netif"; status = "okay"; reg = <11>; local-mac-address = [ 00 04 9F BE EF 01 ]; nxp,pfeng-if-name = "pfe1"; nxp,pfeng-hif-channels = ; nxp,pfeng-linked-phyif = ; clocks = <&clks S32G_SCMI_CLK_PFE1_TX_SGMII>, <&clks S32G_SCMI_CLK_PFE1_TX_RGMII>, <&clks S32G_SCMI_CLK_PFE1_TX_RMII>, <&clks S32G_SCMI_CLK_PFE1_TX_MII>, <&clks S32G_SCMI_CLK_PFE1_RX_SGMII>, <&clks S32G_SCMI_CLK_PFE1_RX_RGMII>, <&clks S32G_SCMI_CLK_PFE1_RX_RMII>, <&clks S32G_SCMI_CLK_PFE1_RX_MII>; clock-names = "tx_sgmii", "tx_rgmii", "tx_rmii", "tx_mii", "rx_sgmii", "rx_rgmii", "rx_rmii", "rx_mii"; phy-mode = "sgmii"; managed = "in-band-status"; }; /* Network interface 'pfe2' */ pfe_netif2: ethernet@12 { compatible = "nxp,s32g-pfe-netif"; status = "okay"; reg = <12>; local-mac-address = [ 00 04 9F BE EF 02 ]; nxp,pfeng-if-name = "pfe2"; nxp,pfeng-hif-channels = ; nxp,pfeng-linked-phyif = ; clocks = <&clks S32G_SCMI_CLK_PFE2_TX_SGMII>, <&clks S32G_SCMI_CLK_PFE2_TX_RGMII>, <&clks S32G_SCMI_CLK_PFE2_TX_RMII>, <&clks S32G_SCMI_CLK_PFE2_TX_MII>, <&clks S32G_SCMI_CLK_PFE2_RX_SGMII>, <&clks S32G_SCMI_CLK_PFE2_RX_RGMII>, <&clks S32G_SCMI_CLK_PFE2_RX_RMII>, <&clks S32G_SCMI_CLK_PFE2_RX_MII>; clock-names = "tx_sgmii", "tx_rgmii", "tx_rmii", "tx_mii", "rx_sgmii", "rx_rgmii", "rx_rmii", "rx_mii"; phy-mode = "sgmii"; managed = "in-band-status"; }; }; }; }; Here is what Linux prints when the driver loads, [ 1.139965] phy-s32cc-serdes 40480000.serdes: Using mode 2 for SerDes subsystem [ 1.150978] phy-s32cc-serdes 40480000.serdes: Unstable RX detected on XPCS1 [ 1.151314] phy-s32cc-serdes 44180000.serdes: Using mode 3 for SerDes subsystem [ 1.157428] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS1 [ 1.157446] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS0 ... [ 15.457853] pfeng: loading out-of-tree module taints kernel. [ 15.469032] pfeng 46000000.pfe: PFEng ethernet driver loading ... [ 15.469046] pfeng 46000000.pfe: Version: 1.3.0 [ 15.469050] pfeng 46000000.pfe: Driver commit hash: M4_DRIVER_COMMIT_HASH [ 15.469054] pfeng 46000000.pfe: Multi instance support: disabled (standalone) [ 15.469058] pfeng 46000000.pfe: Compiled by: 12.3.0 [ 15.469085] pfeng 46000000.pfe: Cbus addr 0x46000000 size 0x1000000 [ 15.469093] pfeng 46000000.pfe: nxp,fw-class-name: s32g_pfe_class.fw [ 15.469098] pfeng 46000000.pfe: nxp,fw-util-name: s32g_pfe_util.fw [ 15.469151] pfeng 46000000.pfe: netif name: pfe1 [ 15.469158] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:01 [ 15.469166] pfeng 46000000.pfe: netif(pfe1) linked phyif: 1 [ 15.469171] pfeng 46000000.pfe: netif(pfe1) mode: std [ 15.469184] pfeng 46000000.pfe: netif(pfe1) HIFs: count 1 map 02 [ 15.469192] pfeng 46000000.pfe: SGMII AN enabled on EMAC1 [ 15.469196] pfeng 46000000.pfe: EMAC1 PHY less SGMII [ 15.469204] pfeng 46000000.pfe: EMAC1 interface mode: 4 [ 15.469345] pfeng 46000000.pfe: netif name: pfe2 [ 15.469351] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:02 [[ 15.469356] pfeng 46000000.pfe: netif(pfe2) linked phyif: 2 15.469361] pfeng 46000000.pfe: netif(pfe2) mode: std [[ 15.469373] pfeng 46000000.pfe: netif(pfe2) HIFs: count 1 map 04 0[ 15.469380] pfeng 46000000.pfe: SGMII AN enabled on EMAC2 ;[ 15.469384] pfeng 46000000.pfe: EMAC2 PHY less SGMII 3[ 15.469389] pfeng 46000000.pfe: EMAC2 interface mode: 4 2[ 15.469459] pfeng 46000000.pfe: HIF channels mask: 0x0006 m[ 15.469502] pfeng 46000000.pfe: PFE port coherency enabled, mask 0x1e [ 15.469760] pfeng 46000000.pfe: Clocks: sys=300MHz pe=600MHz [ 15.469775] pfeng 46000000.pfe: Interface selected: EMAC0: 0xffffffff EMAC1: 0x4 EMAC2: 0x4 O[ 15.470473] pfeng 46000000.pfe: PFE controller reset done K[ 15.470543] pfeng 46000000.pfe: TX clock on EMAC1 for interface sgmii installed [ 15.470577] pfeng 46000000.pfe: RX clock on EMAC1 for interface sgmii installed [ 15.470629] pfeng 46000000.pfe: TX clock on EMAC2 for interface sgmii installed 15.470662] pfeng 46000000.pfe: RX clock on EMAC2 for interface sgmii installed [[ 15.470842] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34000000 0[ 15.470898] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34080000 m[ 15.470955] pfeng 46000000.pfe: assigned reserved memory node pfebufs@83200000 ][ 15.470982] pfeng 46000000.pfe: assigned reserved memory node pfebufs@835e0000 [ 15.476294] pfeng 46000000.pfe: Firmware: CLASS s32g_pfe_class.fw [45040 bytes] F[ 15.476304] pfeng 46000000.pfe: Firmware: UTIL s32g_pfe_util.fw [23252 bytes] i[ 15.476316] pfeng 46000000.pfe: [pfe_platform_master.c:3629] PFE CBUS p0x46000000 mapped @ v0xffffffc00c000000 (0x1000000 bytes) n[ 15.476324] pfeng 46000000.pfe: [pfe_platform_master.c:3634] HW version 0x101 i[ 15.476332] pfeng 46000000.pfe: [pfe_hw_feature.c:93] Silicon S32G3 s[ 15.476340] pfeng 46000000.pfe: [pfe_platform_master.c:3646] Fail-Stop mode disabled h[ 15.479186] pfeng 46000000.pfe: [pfe_platform_master.c:2783] PFE_ERRORS:Parity instance created e[ 15.479197] pfeng 46000000.pfe: [pfe_platform_master.c:2798] PFE_ERRORS:Watchdog instance created d[ 15.479203] pfeng 46000000.pfe: [pfe_platform_master.c:2814] PFE_ERRORS:Bus Error instance created [ 15.479208] pfeng 46000000.pfe: [pfe_platform_master.c:2827] PFE_ERRORS:FW Fail Stop instance created 15.479214] pfeng 46000000.pfe: [pfe_platform_master.c:2840] PFE_ERRORS:Host Fail Stop instance created [ 15.457853] pfeng: loading out-of-tree module taints kernel. [ 15.469032] pfeng 46000000.pfe: PFEng ethernet driver loading ... [ 15.469046] pfeng 46000000.pfe: Version: 1.3.0 [ 15.469050] pfeng 46000000.pfe: Driver commit hash: M4_DRIVER_COMMIT_HASH [ 15.469054] pfeng 46000000.pfe: Multi instance support: disabled (standalone) [ 15.469058] pfeng 46000000.pfe: Compiled by: 12.3.0 [ 15.469085] pfeng 46000000.pfe: Cbus addr 0x46000000 size 0x1000000 [ 15.469093] pfeng 46000000.pfe: nxp,fw-class-name: s32g_pfe_class.fw [ 15.469098] pfeng 46000000.pfe: nxp,fw-util-name: s32g_pfe_util.fw [ 15.469151] pfeng 46000000.pfe: netif name: pfe1 [ 15.469158] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:01 [ 15.469166] pfeng 46000000.pfe: netif(pfe1) linked phyif: 1 [ 15.469171] pfeng 46000000.pfe: netif(pfe1) mode: std [ 15.469184] pfeng 46000000.pfe: netif(pfe1) HIFs: count 1 map 02 [ 15.469192] pfeng 46000000.pfe: SGMII AN enabled on EMAC1 [ 15.469196] pfeng 46000000.pfe: EMAC1 PHY less SGMII [ 15.469204] pfeng 46000000.pfe: EMAC1 interface mode: 4 [ 15.469345] pfeng 46000000.pfe: netif name: pfe2 [ 15.469351] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:02 [[ 15.469356] pfeng 46000000.pfe: netif(pfe2) linked phyif: 2 15.469361] pfeng 46000000.pfe: netif(pfe2) mode: std [[ 15.469373] pfeng 46000000.pfe: netif(pfe2) HIFs: count 1 map 04 0[ 15.469380] pfeng 46000000.pfe: SGMII AN enabled on EMAC2 ;[ 15.469384] pfeng 46000000.pfe: EMAC2 PHY less SGMII 3[ 15.469389] pfeng 46000000.pfe: EMAC2 interface mode: 4 2[ 15.469459] pfeng 46000000.pfe: HIF channels mask: 0x0006 m[ 15.469502] pfeng 46000000.pfe: PFE port coherency enabled, mask 0x1e [ 15.469760] pfeng 46000000.pfe: Clocks: sys=300MHz pe=600MHz [ 15.469775] pfeng 46000000.pfe: Interface selected: EMAC0: 0xffffffff EMAC1: 0x4 EMAC2: 0x4 O[ 15.470473] pfeng 46000000.pfe: PFE controller reset done K[ 15.470543] pfeng 46000000.pfe: TX clock on EMAC1 for interface sgmii installed [ 15.470577] pfeng 46000000.pfe: RX clock on EMAC1 for interface sgmii installed [ 15.470629] pfeng 46000000.pfe: TX clock on EMAC2 for interface sgmii installed 15.470662] pfeng 46000000.pfe: RX clock on EMAC2 for interface sgmii installed [[ 15.470842] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34000000 0[ 15.470898] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34080000 m[ 15.470955] pfeng 46000000.pfe: assigned reserved memory node pfebufs@83200000 ][ 15.470982] pfeng 46000000.pfe: assigned reserved memory node pfebufs@835e0000 [ 15.476294] pfeng 46000000.pfe: Firmware: CLASS s32g_pfe_class.fw [45040 bytes] F[ 15.476304] pfeng 46000000.pfe: Firmware: UTIL s32g_pfe_util.fw [23252 bytes] i[ 15.476316] pfeng 46000000.pfe: [pfe_platform_master.c:3629] PFE CBUS p0x46000000 mapped @ v0xffffffc00c000000 (0x1000000 bytes) n[ 15.476324] pfeng 46000000.pfe: [pfe_platform_master.c:3634] HW version 0x101 i[ 15.476332] pfeng 46000000.pfe: [pfe_hw_feature.c:93] Silicon S32G3 s[ 15.476340] pfeng 46000000.pfe: [pfe_platform_master.c:3646] Fail-Stop mode disabled h[ 15.479186] pfeng 46000000.pfe: [pfe_platform_master.c:2783] PFE_ERRORS:Parity instance created e[ 15.479197] pfeng 46000000.pfe: [pfe_platform_master.c:2798] PFE_ERRORS:Watchdog instance created d[ 15.479203] pfeng 46000000.pfe: [pfe_platform_master.c:2814] PFE_ERRORS:Bus Error instance created [ 15.479208] pfeng 46000000.pfe: [pfe_platform_master.c:2827] PFE_ERRORS:FW Fail Stop instance created 15.479214] pfeng 46000000.pfe: [pfe_platform_master.c:2840] PFE_ERRORS:Host Fail Stop instance created 19.535286] pfeng 46000000.pfe: PFE_ERRORS:Fail Stop instance created [0[ 19.535290] pfeng 46000000.pfe: PFE_ERRORS:ECC Err instance created ;[ 19.535300] pfeng 46000000.pfe: BMU1 buffer base: p0xc0000000 1[ 19.535388] pfeng 46000000.pfe: BMU2 buffer base: p0x34000000 (0x80000 bytes) ;[ 19.536682] pfeng 46000000.pfe: register IRQ 76 by name 'PFE BMU IRQ' 3[ 19.536851] pfeng 46000000.pfe: Firmware .elf detected 9[ 19.536853] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x000000002bafc76d). Pool ready. m[ 19.536857] pfeng 46000000.pfe: Uploading CLASS firmware V[ 19.536865] pfeng 46000000.pfe: Selected FW loading OPs to load 8 PEs in parallel A[ 19.536866] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x00000000a2386541). Pool ready. S[ 19.556236] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" T[ 19.571482] pfeng 46000000.pfe: [FW VERSION] 1.8.0, Build: Nov 16 2023, 07:46:11 (nogitaaa), ID: 0x30 [ 19.571773] pfeng 46000000.pfe: EMAC timestamp external mode bitmap: 0 :[ 19.571814] pfeng 46000000.pfe: Uploading UTIL firmware [ 19.571819] pfeng 46000000.pfe: Selected FW loading OPs to load 1 PEs in parallel I[ 19.574246] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" n[ 19.575323] pfeng 46000000.pfe: FW feature: drv_run_on_g3 i[ 19.575328] pfeng 46000000.pfe: FW feature: jumbo_frames t[ 19.575333] pfeng 46000000.pfe: FW feature: software_vlan_table i[ 19.575337] pfeng 46000000.pfe: FW feature: timestamping a[ 19.575340] pfeng 46000000.pfe: FW feature: qos_mapping l[ 19.575344] pfeng 46000000.pfe: FW feature: core_functionality i[ 19.575348] pfeng 46000000.pfe: FW feature: extended_features z[ 19.575353] pfeng 46000000.pfe: FW feature: flexible_router e[ 19.575357] pfeng 46000000.pfe: FW feature: validate_hif_csum [ 19.575361] pfeng 46000000.pfe: FW feature: err051211_workaround P[ 19.575365] pfeng 46000000.pfe: FW feature: IPsec F[ 19.575368] pfeng 46000000.pfe: FW feature: l2_bridge_aging E[ 19.575373] pfeng 46000000.pfe: FW feature: receive_malformed s[ 19.575379] pfeng 46000000.pfe: FW feature: ptp_conf_check 19.575384] pfeng 46000000.pfe: FW feature: vlan_conf_check [[ 19.575389] pfeng 46000000.pfe: FW feature: hash_load_spread 0[ 19.575395] pfeng 46000000.pfe: FW feature: ingress_vlan m[ 19.575398] pfeng 46000000.pfe: FW feature: safety .[ 19.577825] pfeng 46000000.pfe: VLAN ID incorrect or not set. Using default VLAN ID = 0x01. [ 19.577830] pfeng 46000000.pfe: VLAN stats size incorrect or not set. Using default VLAN stats size =. [ 19.577916] pfeng 46000000.pfe: Software vlan hash table @ p0x20001278 [ 19.578088] pfeng 46000000.pfe: Fall-back bridge domain @ 0x20000a80 (class) [ 19.578092] pfeng 46000000.pfe: Default bridge domain @ 0x20000a78 (class) [ 19.579076] pfeng 46000000.pfe: Routing table created, Hash Table @ p0xc00e0000, Pool @ p0xc00e8000 () [ 19.579290] pfeng 46000000.pfe: Feature err051211_workaround: DISABLED [ 19.587357] pfeng 46000000.pfe: MDIO bus 0 enabled [ 19.593821] pfeng 46000000.pfe: MDIO bus 1 enabled [ 19.599713] pfeng 46000000.pfe: MDIO bus 2 enabled [ 19.599725] pfeng 46000000.pfe: HIF0 not configured, skipped [ 19.600089] pfeng 46000000.pfe: HIF1 enabled [ 19.600319] pfeng 46000000.pfe: HIF2 enabled [ 19.600325] pfeng 46000000.pfe: HIF3 not configured, skipped [ 19.600400] pfeng 46000000.pfe pfe1 (uninitialized): Subscribe to HIF1 [ 19.600407] pfeng 46000000.pfe pfe1 (uninitialized): Host LLTX disabled [ 19.600833] pfeng 46000000.pfe pfe1 (uninitialized): Enable HIF1 [ 19.600994] pfeng 46000000.pfe pfe1 (uninitialized): setting MAC addr: 00:04:9f:be:ef:01 [ 19.601022] pfeng 46000000.pfe pfe1 (uninitialized): PTP HW addend 0x80000000, max_adj configured to b [ 19.601031] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10s 19.535286] pfeng 46000000.pfe: PFE_ERRORS:Fail Stop instance created [0[ 19.535290] pfeng 46000000.pfe: PFE_ERRORS:ECC Err instance created ;[ 19.535300] pfeng 46000000.pfe: BMU1 buffer base: p0xc0000000 1[ 19.535388] pfeng 46000000.pfe: BMU2 buffer base: p0x34000000 (0x80000 bytes) ;[ 19.536682] pfeng 46000000.pfe: register IRQ 76 by name 'PFE BMU IRQ' 3[ 19.536851] pfeng 46000000.pfe: Firmware .elf detected 9[ 19.536853] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x000000002bafc76d). Pool ready. m[ 19.536857] pfeng 46000000.pfe: Uploading CLASS firmware V[ 19.536865] pfeng 46000000.pfe: Selected FW loading OPs to load 8 PEs in parallel A[ 19.536866] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x00000000a2386541). Pool ready. S[ 19.556236] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" T[ 19.571482] pfeng 46000000.pfe: [FW VERSION] 1.8.0, Build: Nov 16 2023, 07:46:11 (nogitaaa), ID: 0x30 [ 19.571773] pfeng 46000000.pfe: EMAC timestamp external mode bitmap: 0 :[ 19.571814] pfeng 46000000.pfe: Uploading UTIL firmware [ 19.571819] pfeng 46000000.pfe: Selected FW loading OPs to load 1 PEs in parallel I[ 19.574246] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" n[ 19.575323] pfeng 46000000.pfe: FW feature: drv_run_on_g3 i[ 19.575328] pfeng 46000000.pfe: FW feature: jumbo_frames t[ 19.575333] pfeng 46000000.pfe: FW feature: software_vlan_table i[ 19.575337] pfeng 46000000.pfe: FW feature: timestamping a[ 19.575340] pfeng 46000000.pfe: FW feature: qos_mapping l[ 19.575344] pfeng 46000000.pfe: FW feature: core_functionality i[ 19.575348] pfeng 46000000.pfe: FW feature: extended_features z[ 19.575353] pfeng 46000000.pfe: FW feature: flexible_router e[ 19.575357] pfeng 46000000.pfe: FW feature: validate_hif_csum [ 19.575361] pfeng 46000000.pfe: FW feature: err051211_workaround P[ 19.575365] pfeng 46000000.pfe: FW feature: IPsec F[ 19.575368] pfeng 46000000.pfe: FW feature: l2_bridge_aging E[ 19.575373] pfeng 46000000.pfe: FW feature: receive_malformed s[ 19.575379] pfeng 46000000.pfe: FW feature: ptp_conf_check 19.575384] pfeng 46000000.pfe: FW feature: vlan_conf_check [[ 19.575389] pfeng 46000000.pfe: FW feature: hash_load_spread 0[ 19.575395] pfeng 46000000.pfe: FW feature: ingress_vlan m[ 19.575398] pfeng 46000000.pfe: FW feature: safety .[ 19.577825] pfeng 46000000.pfe: VLAN ID incorrect or not set. Using default VLAN ID = 0x01. [ 19.577830] pfeng 46000000.pfe: VLAN stats size incorrect or not set. Using default VLAN stats size =. [ 19.577916] pfeng 46000000.pfe: Software vlan hash table @ p0x20001278 [ 19.578088] pfeng 46000000.pfe: Fall-back bridge domain @ 0x20000a80 (class) [ 19.578092] pfeng 46000000.pfe: Default bridge domain @ 0x20000a78 (class) [ 19.579076] pfeng 46000000.pfe: Routing table created, Hash Table @ p0xc00e0000, Pool @ p0xc00e8000 () [ 19.579290] pfeng 46000000.pfe: Feature err051211_workaround: DISABLED [ 19.587357] pfeng 46000000.pfe: MDIO bus 0 enabled [ 19.593821] pfeng 46000000.pfe: MDIO bus 1 enabled [ 19.599713] pfeng 46000000.pfe: MDIO bus 2 enabled [ 19.599725] pfeng 46000000.pfe: HIF0 not configured, skipped [ 19.600089] pfeng 46000000.pfe: HIF1 enabled [ 19.600319] pfeng 46000000.pfe: HIF2 enabled [ 19.600325] pfeng 46000000.pfe: HIF3 not configured, skipped [ 19.600400] pfeng 46000000.pfe pfe1 (uninitialized): Subscribe to HIF1 [ 19.600407] pfeng 46000000.pfe pfe1 (uninitialized): Host LLTX disabled [ 19.600833] pfeng 46000000.pfe pfe1 (uninitialized): Enable HIF1 [ 19.600994] pfeng 46000000.pfe pfe1 (uninitialized): setting MAC addr: 00:04:9f:be:ef:01 [ 19.601022] pfeng 46000000.pfe pfe1 (uninitialized): PTP HW addend 0x80000000, max_adj configured to b [ 19.601031] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10s Re: Using the PFEng driver with 3 interfaces @XD I believe that guide is specific to the hardware for the RDB3 which doesn't physically allow the three PFEs to be SGMII connected. The hardware I'm working on doesn't have that physical limitation as long as the chip itself supports the configuration.  Re: Using the PFEng driver with 3 interfaces Hi @jspace , According to ethernet enablement user guide, I don't think S32G3 supports all 3 PFE with SGMII mode simultaneously. Thanks, XD Re: Using the PFEng driver with 3 interfaces Hello, @jspace  Thanks for the reply. I do not mean that your settings are incorrect, the serdes combination used could match the RM description from my opinion. As you may know, the BSPs are based on NXP's reference board, specially, only for RDB and EVB(including EVB3 and RDB2/RDB3), and some of the serdes combinations that supported by S32G2/G3 could not be supported by the board(since some actual schematic connections), as a result, some of the combinations may not be supported by the default BSP code since it is not supported on the RDB/EVB, howevery, while this combination may be available from hardware perspective on the custom board due different schematic.  Then before applying any serdes combinations on your custom board, I suggest firstly checking the code if could be supported by the BSP, to avoid any error prints like what had shown in your logs. BR Chenyin Re: Using the PFEng driver with 3 interfaces I do not have any modifications in U-Boot. Since this messaging comes from the NXP code within U-Boot can you confirm that I should be able to use this configuration? Serdes0 Lane0 : PCIe Serdes0 Lane1  : PFE Serdes1 Lane0  : PFE Serdes1 Lane1   : PFE Re: Using the PFEng driver with 3 interfaces Hello, @jspace  Thanks for your post. I understand now that you are working with the BSP40,  may I know if you have done any code modification on the u-boot? From the log "SerDes1 configuration will be ignored as it's invalid", your settings may not fully take effect on the system.     BR Chenyin Re: Using the PFEng driver with 3 interfaces Hey @chenyin_h  Yes it is a custom board. I'm using, Linux - bsp40.0-5.15.145-rt ATF - bsp40.0-2.5 U-Boot - bsp40.0-2022.04 U-Boot hwconfig is, serdes0:mode=pcie&xpcs1,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=1G,an=1;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=100;xpcs1_0:speed=1G,an=1;xpcs1_1:speed=1G,an=1 Also u-boot presents this message when in this setting, Failed to configure XPCS0_1 Failed to update XPCS1 for SerDes0 xpcs0_1 and xpcs 1_0 can't be both SGMII SerDes1 configuration will be ignored as it's invalid s32cc_serdes_phy serdes@40480000: Using mode 2 for SerDes subsystem s32cc_serdes_phy serdes@40480000: Unstable RX detected on XPCS1 Re: Using the PFEng driver with 3 interfaces Hello， @jspace  Thanks for your post. May I know if you are working with your custom board? Which version BSP you are working with?  How about your serdes settings?(like hwconfig or else) Thanks for the clarification in advance. BR Chenyin

decices selection when debugging s32k314 When I choose NXP s32K3 series device with cyclone and IAR IDE,I found 3 types and what are their differences s32k314, s32k314-EMU, s32k314-SECUREBOOT Re: decices selection when debugging s32k314 Hi @luhaiou  The S32K3xx device with HSE firmware installed does not necessarily need secure debugger authentication. When installing HSE, the device is initially in lifecycle CUST_DEL, which has debug access open. It is not until advancing the life cycle that secure debugging is required. Re: decices selection when debugging s32k314 Now that I've turned on the secure boot feature, I still have S32K314 selected and nxp_s32k341_1x32x256k_hse_enabled.arp selected when debugging. I didn't choose S32K314-SECUREBOOT, it still debugs normally, is it necessary to choose S32K314-SECUREBOOT? Re: decices selection when debugging s32k314 Hi @luhaiou  S32K314: during debug entry a hard reset is toggled. Default target.  S32K314-EMU: is no longer available in the latest versions.  S32K314-SECUREBOOT: used when JTAG protection is set or secure boot. Prevents to clear the authentication when enters to debug.  B.R. VaneB

双 vcom fatFS USB OTG1 我正在使用 MIMXRT1170-EVKB 入门套件，我想知道 OTG USB 层是否能够在同一端口上处理 vcom 和 usb 主机 fatFS？ 我正在尝试让两者同时工作，并使用带有 freeRTOS 的相同端口。 提前感谢任何澄清

Choosing USB Dongle for BLE Sniffing Hello, Can I get best recommendation for below USB dongle for BLE Sniffer: USB-KW38 USB-KW41Z USB-KW41 Which one should I choose ? Besides, what is the advantage of that USB dongles comparing with competitor such as NRF52840 ? Best regards, NDX Re: Choosing USB Dongle for BLE Sniffing Thanks. BR, NDX Re: Choosing USB Dongle for BLE Sniffing Hello, Hope you are doing well. You can use the latest device: USB-KW38 For getting the sniffer software, please check the Getting Started with the USB-KW38 | NXP Semiconductors Regards, Ricardo

外部频率和占空比输入测量 大家好， 我想在我的定制板 i.mx.rt1176 上测量外部频率输入和占空比。我没有找到应用说明或示例代码。有没有什么资源可以帮助我开始编写代码？ 顺祝商祺！ 巴士里·卡亚

如何协作完成一个项目？版本控制/git 我和另外两名开发人员组成的团队正在快速掌握 MCUXpresso 的 vsCode 扩展。 我们已经完成了所有设置步骤，并成功在我们的 i.MXRT1050 开发板上运行示例代码。 我们的问题是，我们希望在 github 上合作开展一个新项目。 因此，我克隆了 RT1050 的“新项目” repo，做了一些小改动，然后将项目文件夹推送到我们的 repo。 我们似乎遇到了两个问题： - 如果 .vscode并且 armgcc 文件夹是共享的，那么项目的 CMake 文件中的所有路径都是来自我计算机的绝对路径。因此我们的其他开发人员在尝试构建时会遇到错误。 - 如果将这些文件添加到 gitignore，导入项目时会缺少主板的所有支持文件，因此项目也无法编译。 我们已经在另一台开发人员的计算机上构建了这个项目，并使用了一些 hack-y 解决方案。（复制__repo__ ，.vsCode，和 armgcc 文件夹（来自同名项目，位于我们随后删除并克隆我们自己的项目的同一位置），但这不是正确的方法。 设置该功能的步骤是什么？我的 .gitignore 中应该包含什么？以及需要采取哪些步骤来从存储库设置项目？ 回复：如何合作完成一个项目？版本控制/git 谢谢！这个解决方案有效，我们现在正在一起开展这个项目。 回复：如何合作完成一个项目？版本控制/git 你好@halfordC ， 请参阅下面使项目可在 Git 中共享所需的一些更改： 在你的项目中，在 .vscode 下文件夹（应保存在 Git 中）中有一个名为 mcuxpresso-tools.json 的文件，其中包含两个绝对路径：“toolchainPath”和“path”（在“sdk”节点下）。 您可以引用环境变量来确保这些路径在不同的计算机上起作用。 例如：“toolchainPath”：“ ${env:ARMGCC_PATH} ”——其中 ARMGCC_PATH 是指向工具链的环境变量。 ide_overrides.cmake 可以添加到。gitignore，因为它是由构建过程重新生成的。 应将生成构建工件的文件夹添加到。gitignore 也是如此。 希望这些步骤有所帮助。 谢谢！ Dragos。

MUX_0_CSC only use FIRC clock? Hello, While referring to the document on generating clocks for the S32K314, I came across a question. [Figure1] In [Figure1], it states that MUX_0_CSC receives either PLL_PHI0_CLK or FIRC_CLK as its input. [Figure2] However, in [Figure2], the explanation for the SELCTL bit of MSC_0_CSC only indicates that FIRC can be selected. So, does this mean that MUX_0_CSC cannot use PLL_PHI0_CLK as a clock source? Re: MUX_0_CSC only use FIRC clock? thank you! Re: MUX_0_CSC only use FIRC clock? Hi@studyseok8466 Please refer to latest datasheet , "S32K3xx Reference Manual, Rev. 9, 07/2024".

Using the memmove function provided by the libc99 library gives an error result in S32 DS USING 5744 Hi NXP experts, Recently we are using mpc5744 with S32 Design Studio for Power Architecture Version 2017.R1 to compile the project. Now we are facing a memmove function problem. The project in the attachment is modified based on "hello world" and can reproduce the issue we encountered. We defined a 40-byte array of type U8 as the data source, used 0x4001268e as the data destination, called the memmove function to copy data, but found that the last 6 bytes of the destination data were not copied correctly. Upon analyzing the standard C code, we discovered that the issue might be related to the macro replacement of deref_auto_inc in __copy_long_mem.c. The memmove.o included in libc99.a should have enabled #define deref_auto_inc(p) *++(p), but it was incorrectly enabled as #define deref_auto_inc(p) *(p)++. We want to confirm if this issue is caused by a bug in the default lib library provided by s32DS or an default method we have usd. We also found in the map file that the memmove function is not compiled from the C source code but rather uses library functions from libc99.a. This means that we cannot solve this problem by modifying the C source code, is that correct? How should we go about resolving this issue then? We are in urgent need of your help. Project is attached. Thanks!!!  Thanks! Re: Using the memmove function provided by the libc99 library gives an error result in S32 DS USING Hi,  I already put answer to your original thread - https://community.nxp.com/t5/MPC5xxx/mpc5744-facing-a-memmove-function-bug/m-p/1850679#M25343 

プロジェクトで協力して取り組むには?バージョン管理 / git 私と他の2人の開発者のチームは、MCUXpressoのvsCode拡張機能に追いついています。 すべてのセットアップ手順を完了し、i.MXRT1050 開発ボードでサンプル コードを実行することに成功しました。 私たちの問題は、githubの新しいプロジェクトに協力して取り組みたいということです。 そこで、RT1050 の "新しいプロジェクト" リポジトリを複製し、いくつかの小さな変更を加え、プロジェクト フォルダーをリポジトリにプッシュしました。 2つの問題に遭遇したようです。 - .vscode の場合armgccフォルダが共有されている場合、プロジェクトのCMakeファイル内のすべてのパスは、私のコンピューターからの絶対パスです。そのため、他の開発者がビルドしようとするとエラーが発生します。 - これらのファイルが gitignore に追加されている場合、プロジェクトのインポートにはボードのすべてのサポート ファイルがないため、プロジェクトもコンパイルできません。 私たちは、いくつかのハックのような解決策を使用して、別の開発者のコンピューター上に構築するプロジェクトを持っています。( __repo__、.vsCode、そして、同じ名前のプロジェクトからarmgccフォルダを、その後、自分のプロジェクトを削除してクローンしたのと同じ場所にあります)、これはこれを行う正しい方法ではありません。 これを設定する手順は何ですか?私の.gitignoreには何が必要ですか、また、リポジトリからプロジェクトを設定するには、どのような手順を実行する必要がありますか? Re:プロジェクトで協力して取り組むには?バージョン管理 / git 感謝！この解決策が功を奏し、今では全員が一緒にプロジェクトに取り組んでいます。 Re:プロジェクトで協力して取り組むには?バージョン管理 / git こんにちは@halfordC、 プロジェクトを Git で共有可能にするために必要な変更を以下に示します。 プロジェクト内の .vscodeフォルダ (Git に保存する必要があります) には、"toolchainPath" と "path" ("sdk" ノードの下) の 2 つの絶対パスを含む mcuxpresso-tools.json というファイルがあります。 環境変数を参照して、これらのパスが異なるコンピューターで機能することを確認できます。 例: "toolchainPath": "${env:ARMGCC_PATH}" – ここで、ARMGCC_PATHはツールチェーンを指す環境変数です。 ide_overrides.cmake を に追加できます。gitignore は、ビルド プロセスによって再生成されます。 ビルド成果物が生成されるフォルダは、.gitignoreも。 これらの手順がお役に立てば幸いです。 ありがとうございます ドラゴス。

S32K312 Core Clock Hello. I found clock configuration table in Reference Manual Table 145. Is it limitation or just example? I want to set Core Clock = 60 MHz, is it okay? Best Regards, Sean Sung Re: S32K312 Core Clock Hello @Robin_Shen  Thank you for reply. Best Regards, Sean Sung Re: S32K312 Core Clock Hi There is a NOTE in S32K3XXRM: The frequencies in the table above are maximum frequencies for a specific clock. However, any clock frequency selected must adhere to the same clock divider ratios shown in System clocking configurations.   So it is possible to set Core Clock to 60MHz, but you need to pay attention to modifying the divider of other clocks.   Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

Daul vcom fatFS USB OTG1 I'm using the MIMXRT1170-EVKB starter kit and I would to know if OTG USB layer able to handle both vcom and usb host fatFS on the same port? I'm trying to get both working at the same time, using the same port with freeRTOS. Thanks in advance for any clarification 回复： Daul vcom fatFS USB OTG1 Hi @PaoloRB , Thanks for your interest in NXP MIMXRT series! It is possible to switch between device and host roles using the same USB port. The pin_detect example provided in the SDK can be a start: Best regards, Gavin

External Frequence and Duty Input Measurement Hello Everyone, I want to measure external frequency input and duty cycle on my custom board i.mx.rt1176. I did not find application note or example code. Is there any source that help me to start writing my code? Best Regards, Basri KAYA Re: External Frequence and Duty Input Measurement Hi @Bkaya  Thank you very much for your patience.  The QTIMER is limited to work with the BUS_CLK_ROOT, given the fact that you are already using the maximum prescaler value, I would think that testing with reducing the frequency of the bus clock could have been an option.  Another way to measure with such low frequecy would be using low clock reference like the RTC.  Diego Re: External Frequence and Duty Input Measurement Hi @diego_charles, Thank you. I read the frequency input. I changed the divider to 128 so i can measure between 20-10.000 Hz. I did not measure below 20 Hz. Is there a way to do it ?  Best Regards, Basri KAYA Re: External Frequence and Duty Input Measurement Hi @Bkaya  Thank you for reaching us and for your patience.  I think you could use the QTIMER peripheral for this purpose. There is input capture demo on the SDK (qtmr_inputcapture_outputpwm_cm7) this could help you as a starting point to measure frequency.  As one of my colleagues mention the QTIMER could also help you to measure duty cycle.  See this post PWM duty cycle measurement on RT105x for a more detailed idea.  I hope this still could help you.  Diego.

How to work on a project collaboratively? Version control / git Me, and a team of 2 other developers are getting up to speed on the vsCode extension for MCUXpresso.  We've done all the setup steps, and have had success running example code on our i.MXRT1050 development boards.  Our issue, is that we would like to work collaboratively on a new project in github. So, I cloned the "new project" repo for the RT1050, made a few small changes, and pushed the project folder to our repo.  We seem to have run into 2 problems:  - If the .vscode and armgcc folder is shared, then all of the paths in the CMake file for the project are the absolute paths from my computer. So our other devs get errors when they try to build.  - If these files are added to the gitignore, importing the project is missing all the support files for the board, and so project is also not able to compile.  We have got the project to build on another devs computer with some hack-y solutions. (copying the __repo__, .vsCode, and armgcc folder from a project of the same name, in the same location that we then deleted and cloned our own project into), but this can't be the correct way to do this.  What are the steps to set this up? What should I have in my .gitignore, and what steps need to be taken to set up a project from a repository? Re: How to work on a project collaboratively? Version control / git Thanks! This solution worked, we are now all working on the project together.  Re: How to work on a project collaboratively? Version control / git Hi @halfordC,  Please find below some changes needed to make the project shareable in Git: In your project, under .vscode folder (which should be saved in Git), there is a file called mcuxpresso-tools.json that contains two absolute paths: “toolchainPath” and "path" (under “sdk” node).          You can refer environment variables to make sure these paths work on different computers.          Ex:  "toolchainPath": "${env:ARMGCC_PATH}" – where ARMGCC_PATH is an environment variable that points to a toolchain. ide_overrides.cmake can be added to . gitignore as it is regenerated by the build process. Folders where the build artifacts are generated should be added to . gitignore too. Hope these steps help. Thanks, Dragos.