BCTU DMA I’m working on reading ADC data using DMA. I’ve set up the DMA to trigger each time the FIFO is full, but I’m encountering an issue where the DMA only triggers once. I’m monitoring this with the Fifo1DmaComplete callback function. I’ve attached my project files. Could you help me identify the problem? Re: BCTU DMA Hi@Ayaz It is fixed，Please use the callback function below.  Dma0_CH1_IRQHandle  Dma0_CH16_IRQHandle Those two function will be called again in the program. Bctu_Ip_Bctu0Fifo1DmaComplete Bctu_Ip_Bctu0Fifo2DmaComplete  " Re: BCTU DMA Yes , but should this one be used  Bctu_Ip_Bctu0Fifo1DmaComplete Bctu_Ip_Bctu0Fifo2DmaComplete  Or  Dma0_CH1_IRQHandle  Dma0_CH16_IRQHandleWhat is the difference? Re: BCTU DMA Hi@Ayaz Yes, you are right, but the callback function for the highlighted part is incorrect, please check it carefully. Re: BCTU DMA Thanks for the info  for this specific configuration, do we need to set the handle as shown in the image below or should it be replaced by  Bctu_Ip_Bctu0Fifo1DmaComplete  Bctu_Ip_Bctu0Fifo2DmaComplete  what is the difference?   Re: BCTU DMA Hi@Ayaz The usage provided by our RTD is fixed, and the DMA configuration has been completed for the user. P lease refer to the following usage Read ADC data from "BctuDmaFifo1" in "BctuWatermarkNotifFIFO1"

S32 Design Studio - How to set FreeRTOS cpu clock Hello and Happy new year! I am developing sw for the S32G399A MCU (M7 core) using the S32 Design Studio tool. My role is to develop the TCP/IP part so I created the example project (lwip_FreeRTOS_S32G399A_M7) and checked it. After checking, I created a new project and following the contents of the example project. But the cpu clock[Hz] in the FreeRTOS configuration didn't change even though I followed the exact same settings. (Pins / Clocks / Etc...) And In the example, the config mode is Default Clock (not the User Clock) I wannted to upload the screenshot buf unfortunately, due to my company policy, file/screenshot uploads are not allowed. Could you please how to change the cpu clock? Thank you. Re: S32 Design Studio - How to set FreeRTOS cpu clock hi，Boniface I would be glad to help you. BR Joey Re: S32 Design Studio - How to set FreeRTOS cpu clock Hi, Joey Finally, I made it. I installed S32DS 3.5.3 / FreeRTOS 4.0.3 CD3 / SW32G_RTD_4.4_4.0.2_HF02 and It worked. Thank you for your help. Best Regards, Boniface Re: S32 Design Studio - How to set FreeRTOS cpu clock hi,Boniface Thank you for your reply. I have the same problem when I use your .mex file, but I did not encounter the problem when I created a new project to add FreeRTOS.I use the 4.0.2 HF3 version of RTD. Refer to the Release Note, you can try the 4.0.2 version of RTD in S32DS. BR Joey Re: S32 Design Studio - How to set FreeRTOS cpu clock Hi, Joey Thank you for your reply. My coworker installed S32DS 3.5.3 and created a new project. He just added the freertos component after creating the project and the Default clock is still '0'. (He didn't change the default setting, including clocks.) Could you please check the mex file I attached? Best regards, Boniface Re: S32 Design Studio - How to set FreeRTOS cpu clock hi,Boniface Thank you for your reply. I encountered the same problem when testing the provided .mex file. However, I did not experience the issue when I set up a new project and added FreeRTOS as shown in the following picture. You can try setting up a new project only to add FreeRTOS; then, if the problem still occurs, you could try using version S32DS 3.5.3, which I normally use. Hope it can help you. BR Joey Re: S32 Design Studio - How to set FreeRTOS cpu clock Hi, Joey Thanks for your fast reply. I changed the setting but the clock didn't change. Even though I clicked the Update Code button, deleted and re-added the freertos component in the Peripherals it didn't change. What else should I check? Best regards, Boniface Re: S32 Design Studio - How to set FreeRTOS cpu clock hi,Boniface In the FreeRTOS configuration, the CPU clock and XBAR_CLK should maintain the same value. To change the XBAR_CLK, you need to adjust CORE_PLL_DFS1 as shown in the following picture. BR Joey Re: S32 Design Studio - How to set FreeRTOS cpu clock Hi, Joey Unfortunately, I already set XBAR_CLK to 400MHz but it didn't work. So I attached the MEX file of the project that I create. I hope this helps you analyze it. Best regards, Boniface Re: S32 Design Studio - How to set FreeRTOS cpu clock Hi,Boniface Thank you for your detailed reply. You need to fix XBAR_CLK as the following picture. Hope it can help you. BR Joey Re: S32 Design Studio - How to set FreeRTOS cpu clock Hi, Joey Thanks for your reply. I'm using these SW.  - S32 Design Studio for S32 Platform V3.5 (Update 14)  - S32G3 RTD AUTOSAR 4.4 Version 4.0.0  - FreeRTOS for S32CC 4.0.2  - TCPIP_STACK for S32G version 1.0.4 I got the example by  : File - New - S32DS Project from Example - S32G TCPIP STACK 1.0.4 D2310 Example Projects - S32G399A - lwip_FreeRTOS_S32G399A_M7 And the Target board is S32G-VNP-RDB3. (Actually, I ordered that board and haven't received it yet.) Best regards, Re: S32 Design Studio - How to set FreeRTOS cpu clock Hi，Boniface Thank you for contacting us. Which version of RTD and S32DS you are use? In addition , Are you using a custom board? Is lwip_FreeRTOS_S32G399A_M7 normal for you? How do I get the same version of this routine as yours? BR Joey

从 Lpspi_Ip_AsyncTransmit() 函数传输数据时 LPSPI_IP_BUSY 状态 我们对S32K44有一个问题， 使用 EB tresos 配置 LPSPI 并尝试使用 Lpspi_Ip_AsyncTransmit() 传输数据 一旦调用被执行，其他调用就会被拒绝，因为驱动程序保持在 LPSPI_IP_BUSY 状态。 您能否分享一个 S32K344 的示例项目（带有 EB tresos 配置）？ 对于 Lpspi_Ip_AsyncTransmit()；使用 DMA？ #S32K344 回复：从 Lpspi_Ip_AsyncTransmit() 函数传输数据时，LPSPI_IP_BUSY 状态 谢谢 Petr 使用这个例子我可以使用SPI，问题就解决了

找不到S32K3下的块 你好，希望这条消息对你有帮助。我已经为 S32K3xx MCU 安装了 NXP MBDT 工具箱，但由于某种原因，我在 S32K3xx 核心、系统、外围设备和实用程序选项卡下的 Simulink 库中看不到任何内容，如附图所示。您能否告知问题是什么以及如何解决？ 非常感谢， 小梅 回复：无法找到S32K3下的块 你好 Dragos，我使用的 Matlab 版本是 2024b，工具箱是 1.5.0 版本。请告知下一步该尝试什么。 非常感谢， 小梅

i.MXRT1020 Security Reference Manual? Where can I find the i.MXRT1020 Security Reference Manual? Best regards. Re: i.MXRT1020 Security Reference Manual? Hi @spthx , Thanks for your interest in NXP MIMXRT series! Currently SRM and some security related ANs are controlled and require customers to sign an NDA before they can access them. For more information on how to sign the NDA and obtain the documentation, please refer to a previous document by our colleague. Best regards, Gavin

S32K3の下のブロックが見つかりませんでした こんにちは、このメッセージがあなたを元気に見つけてくれることを願っています。S32K3xx MCU用のNXP MBDT Toolboxをインストールしましたが、添付の写真のように、なぜかS32K3xxコア、システム、ペリフェラル、ユーティリティタブの下のSimulinkライブラリに何も表示されませんでした。問題の内容と解決方法をアドバイスしていただけますか? どうもありがとう シャオメイ 日時:S32K3の下のブロックが見つかりませんでした こんにちはドラゴス、私が使用しているMatlabバージョンは2024bで、ツールボックスはバージョン1.5.0です。次に何を試してみるべきかアドバイスしてください。 どうもありがとう シャオメイ

Lpspi_Ip_AsyncTransmit()関数からデータを送信中のLPSPI_IP_BUSY状態 S32k44に問題があります。 EB tresosを使用してLPSPIを設定し、Lpspi_Ip_AsyncTransmit()を使用してデータを送信しようとしました ドライバーがLPSPI_IP_BUSY状態のままであるため、他の呼び出しが拒否されると、呼び出しが実行されます。 S32K344のサンプルプロジェクト(EB tresos構成を使用)を共有していただけますか? Lpspi_Ip_AsyncTransmit() の場合;DMAを使用していますか? #S32K344 Re:Lpspi_Ip_AsyncTransmit()関数からデータを送信している間のLPSPI_IP_BUSY状態 ありがとうPetr この例を使用すると、SPIを使用できるようになり、問題は解決します

Instruction access violation after initializing FlexSPI driver Hello, I'm trying to add a FlexSPI driver to my project to read/write a portion of my SPI flash. This SPI flash also runs the program code, but the data space will be located in a separate region. I'm using an i.MXRT1062. I was able to run the example "flexspi_nor_polling_transfer" successfully, so now trying to adapt this example to my project.  I see that one of the requirements when using this driver, at least for initialization, is that the program code needs to run in RAM somewhere, as the flash is reset during initialization and this would cause problems with the app execution. I've set up the linker script the same as the example: data.ldt < # if memory.name=="SRAM_ITC"> *flexspi_nor_flash_ops.o(.text*) *fsl_flexspi.o(.text*) main_text.ldt *(EXCLUDE_FILE(*flexspi_nor_flash_ops.o *fsl_flexspi.o) .text*) I wasn't able to place the .bss portion into SRAM_OC like in the example bc it wouldn't fit, but maybe this is not necessary if nothing is accessed in the .bss region during initialization. After importing the driver into my project, I'm able to execute everything in flexspi_nor_flash_init(FLEXSPI_Type *base) up until FLEXSPI_Init(base, &config) has finished, then I receive a hard fault - Instruction access violation flag. I'm not sure why this is happening at this point, I would think every instruction should be contained inside the files flexspi_nor_flash_ops.c & fsl_flexspi.c within SRAM_ITC. Are there any other pitfalls when using this example within a larger project? Or is there a better example flexspi example to use for spi flash? Thanks i.MXRT 106x Re: Instruction access violation after initializing FlexSPI driver I'm also using FreeRTOS in this project.  The issue seems to be fixed after setting a critical section when flexspi_nor_flash_init() is called. This is probably needed whenever the spi flash code is called. Please refer to the forum post on this: https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Implement-example-flexspi-nor-polling-transfer-in-project-based/m-p/1475208 

i.MXRT1020 セキュリティリファレンスマニュアル i.MXRT1020セキュリティ・リファレンス・マニュアルはどこで入手できますか? よろしくお願いいたします。

PT2001AEのクロック信号が失われます。 問題は次の通りです: SPI を使用して PT2001AE のクロック ステータス レジスタを読み取ると、返されるデータはクロックが欠落していることを示しています。しかし、私のクロックは正常に出力されており、オシロスコープでPT2001AEのclkピンにクロック信号があることを測定しました。では、なぜレジスタはクロックが欠落していることを示しているのでしょうか。 Re:PT2001AEのクロック信号が失われています。 私はあなたの提案に従って位置を1に設定し、その後再びSPIリターンデータを受け取りました。今回、返されるデータは **cksys_missing** を示しています。

Couldn't find the blocks under S32K3 Hi there, I hope this message finds you well. I have installed the NXP MBDT Toolbox for S32K3xx MCUs, but for some reason I couldn't see anything in the Simulink library under the S32K3xx core, system, peripherals and utilities tab, as shown in the attached photo. Could you advise what the issue is and how to solve it? Many thanks, Xiaomei Re: Couldn't find the blocks under S32K3 Hi @dragostoma , Thanks Dragos, it works. Many thanks! from Xiaomei Re: Couldn't find the blocks under S32K3 Hi, @XH, The problem you are experiencing is because you are trying to open the block mask directly in the library. Each block contains various parameters and channels, specific to the configuration of each model. Because of this, the block mask in the library is grayed out. You can use the block and its parameters by adding the block to a Simulink model. Best regards, Dragos Re: Couldn't find the blocks under S32K3 Hi, @dragostoma  Thanks very much for your reply. Once I click on this blocks, to open its mask configuration box, some areas are greyed. Is this normal, like also a part of the visual issues? Please see attached photo for this. Many thanks, Xiaomei Re: Couldn't find the blocks under S32K3 Hi @dragostoma , Thanks very much for your reply. Once I click on this blocks, to open its mask configuration box, some areas are greyed. Is this normal, like also a part of the visual issues? Please see attached photo for this. Re: Couldn't find the blocks under S32K3 Hi, @XH, This is a known issue in MATLAB 2024a and will be fixed in the next release. But it is only a visual issue, you can still use the blocks by dragging and dropping them into a Simulink model. Thank you for reporting this issue to us. Best regards, Dragos Re: Couldn't find the blocks under S32K3 Hi @dragostoma , Thanks for your reply. I have uninstalled Matlab 2024b and re-installed 2024a. Then I followed the steps in " Model-Based Design Toolbox S32K3xx Series Quick Start Guide" to set up the toolbox. Now I can see the names of the blocks in the Simulink Library but not the whole block, as shown in the attached photo. Could you please advise what to do next? Many thanks, Xiaomei Re: Couldn't find the blocks under S32K3 Hi, @XH, Please check the Model_Based_Design_Toolbox_S32K3xx_Series_Release_Notes.pdf document to view all the features available in this version of the toolbox, and the supported MATLAB versions. Version 1.5.0 is developed and tested to support the following versions of MATLAB: - R2021a; - R2021b; - R2022a; - R2022b; - R2023a; - R2023b; - R2024a; Best regards, Dragos Re: Couldn't find the blocks under S32K3 Hi @dragostoma , Thanks for your reply. Can I ask does toolbox version 1.5.0 support for MATLAB version 2024a? Many thanks, Xiaomei Re: Couldn't find the blocks under S32K3 Hi, @XH, Try the second option - "Generate repositories in memory" when you press the refresh button. Keep in mind that the toolbox version 1.5.0 does not include support for MATLAB version 2024b. Therefore, you need to make sure that you run the path creation script (mbd_s32k3_path.m) to generate the codertarget folder corresponding to the version you are using (folder found at mbdtbx_s32k3|codertarget|2024b). If the folder exists but is empty, run the command mbd_s32k3.nxp.target.create_codertarget() to generate the folder contents. After that, make sure that this folder is in the MATLAB path. You should be able to use blocks by dragging and dropping them into a Simulink model. Try this and let me know how it worked. Hope this helps, Dragos Re: Couldn't find the blocks under S32K3 Hi @dragostoma  Thanks for your reply. The Matlab I use is 2024b, and the S32k3xx MBDT toolbox is Ver 1.5.0 After I refresh the tab "communication blocks", this window jumps out as shown in the attached photo. Please advise what to try next Many thanks, Xiaomei Re: Couldn't find the blocks under S32K3 Hi Dragos, The Matlab version that I use is 2024b, and the Toolbox is version 1.5.0. Please advise what to try next. Many thanks, Xiaomei Re: Couldn't find the blocks under S32K3 Hi, @XH, Thank you for your interest into Model-Based Design Toolbox for S32K3. First of all, what versions of MATLAB and Toolbox are you currently using? This way, we can try to reproduce your problem directly on your setup. Until then, try reopening MATLAB and Simulink and refreshing the Simulink Library, by pressing F5 or by right-clicking on any section in the dropdown: Keep us updated on your progress. Best regards, Dragos

i.MXRT1020 安全参考手册？ 在哪里可以找到 i.MXRT1020 安全参考手册？ 顺祝商祺！

LPSPI_IP_BUSY state while transmitting data from Lpspi_Ip_AsyncTransmit() function We have  an issue With S32k44, configured LPSPI using EB tresos and tried to transmit data using Lpspi_Ip_AsyncTransmit() call gets executed once Other calls are rejected because the drivers stay in the LPSPI_IP_BUSY state. Can you please share an Example project of S32K344(with EB tresos configuration) for Lpspi_Ip_AsyncTransmit(); using DMA? #S32K344 Re: LPSPI_IP_BUSY state while transmitting data from Lpspi_Ip_AsyncTransmit() function Thanks Petr using this example I can use SPI, and the issue is resolved  Re: LPSPI_IP_BUSY state while transmitting data from Lpspi_Ip_AsyncTransmit() function Hi, try to look over below example, not for EB but is using HLD driver as well. https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-SPI-Transmit-amp-Receive-Using-DMA-DS3-5-RTD500/ta-p/1992224 Also this one could be useful https://community.nxp.com/t5/S32K/S32K344-SPI-DMA-with-MCAL-configuration-not-send-out-all-bytes/td-p/1767072 BR, Petr

S32 设计工作室 - 如何设置 FreeRTOS CPU 时钟 您好，新年快乐！ 我正在使用 S32 Design Studio 工具为 S32G399A MCU（M7 核心）开发软件。 我的职责是开发 TCP/IP 部分，因此我创建了示例项目（ lwip_FreeRTOS_S32G399A_M7 ）并对其进行了检查。 检查之后，我创建了一个新项目并遵循示例项目的内容。 但是，即使我遵循完全相同的设置，FreeRTOS 配置中的CPU 时钟 [Hz]也没有改变。（别针/时钟/等等...） 在示例中，配置模式是默认时钟（不是用户时钟） 我想上传截图，但不幸的是，由于公司政策，不允许上传文件/截图。 你能告诉我如何更改 CPU 时钟吗？ 谢谢！

S32K312 FEE FLS INIT time hello,expert there ia a question in my boot and app, before step into boot ,i will write a flag ( program request ) in eeprom ,and use jump function jump to boot, after download all the data ,i will write a flag ( app valid ) , then i will jump to app. but i find that every cyclic,the Fee_MainFunction loop and MemAcc_MainFunction loop will take longer time. for example, the 1st is 10ms,the 2nd cyclic is 20ms it will lead to the fault of uds timer Re: S32K312 FEE FLS INIT time It's probably caused by RAM initialization. This piece of RAM should be initialized conditionally. If the source of reset power-on reset, the RAM must be initialized. If it is not power-on reset, you can skip the initialization. Re: S32K312 FEE FLS INIT time accoring to your advice, i allocate a RAM(ORIGIN = 0x20407E00, LENGTH = 0x00000100)section for flag which app jump to boot. i am sure that the ram section will not be affected by DATA and BSS init. then in app i set address 0x20407E00  as 0x55aa55aa, and use jump function to boot , in boot read the address value is always zero. that's why? Re: S32K312 FEE FLS INIT time thanks Re: S32K312 FEE FLS INIT time Hi @PINKMAN  This is natural and expected behavior of Fee module. The more data is present in Fee blocks, the more time will initialization take. If there are a lot of records, it can take much(!) more time than tens of milliseconds. Also cluster swap may be necessary sometimes during initialization which will significantly affect the timing. If timing is critical, don't use Fee module for this. Either program some flash directly, so you can read the flash immediately without any delays after reset or use RAM only - if it is sufficient to keep the information only during reset and not during power off. Regards, Lukas

The clock signal of PT2001AE is lost. The problem is as follows: when I use SPI to read the clock status register of PT2001AE, the returned data indicates that the clock is missing. However, my clock is outputting normally, and I have measured with an oscilloscope that there is a clock signal on the clk pin of PT2001AE. So why does the register indicate that the clock is missing? Re: The clock signal of PT2001AE is lost. Dear Babylove, this is correct behavior. Please refer to the section 13.3.4.8 in the PT2001 full datasheet. Please download the datasheet from the PT2001 product page, under the secure files.  With Best Regards, Jozef Re: The clock signal of PT2001AE is lost. I followed your suggestion and set the position to 1, then received the SPI return data again. This time, the returned data indicates **cksys_missing**. Re: The clock signal of PT2001AE is lost. Dear Babylove, please refer to the section 13.3.4.8 in the PT2001 full datasheet.  "Once the loss_of_clock bit sets, it can be reset only by completing a 'switch to clock' pin. For this operation to complete, it must be requested when the main clock input pin again provides a valid clock frequency." There was probably short loss of clock and the loss_of_clock bit was set. To reset this bit the please set the switch_to_clock_pin to 1. With Best Regards, Jozef

S32 Design Studio - FreeRTOS CPUクロックの設定方法 こんにちは、新年あけましておめでとうございます! S32G399A MCU(M7コア)用のswをS32 Design Studioツールで開発しています。 私の役割はTCP/IP部分の開発なので、サンプルプロジェクト(lwip_FreeRTOS_S32G399A_M7)を作成して確認しました。 確認後、新しいプロジェクトを作成し、サンプルプロジェクトの内容に従って作成しました。 しかし、FreeRTOS設定の CPUクロック[Hz] は、まったく同じ設定に従っても変わりませんでした。(ピン/クロック/その他...) この例では、設定モードは デフォルトクロック です(ユーザクロックではありません) 残念ながら、私の会社のポリシーにより、ファイル/スクリーンショットのアップロードは許可されていません。 CPUクロックの変更方法を教えてください。 ありがとうございます。

RTD 5.0.0 documentation unclarities Hi, we are in the process of integrating the RTD 5.0.0 in our SW to replace the 4.0.2 P12. We had issues in integrating it together with LLCE 1.0.8. After almost 2 days, we found out, that the memory section name was changed within the Can_43_LLCE_MemMap.h. With the 4.0.2 RTD the memory section for CAN LLCE was ".can_43_llce_sharedmemory", now it is changed to "llce_can_sharedmemory". Why is this not specifically documented in the release notes? The Release Notes are not mentioning this change. Or maybe I don't see it. The BaseNxp only vaguely mentions that "memory shall be allocated for every section in the driver's ' '_MemMap.h". But this is written for each module IM. The RTD 5.0.0 linker command files doesn't accompany the name change for this memory section. Then we thought, ok, maybe the LLCE 1.0.9 contains this change, since we have the older LLCE 1.0.8 version, and the RTD 5.0.0 is just not compatible with the 1.0.8. But, also the LLCE 1.0.9 mentions in the integration manual that the section in the linker file is the "old" one I am not finding in the release notes a compatibility list of the non-RTD components, such as LLCE, PFE, LIN, etc. Is it maybe mentioned somewhere else? Then I started analyzing the release notes and noticed that many entries (bugs, new features, etc.) do not show the "Proposed solution" part completely in the document. Example, ARTD-38632, Bug: ARTD-71613, Bug: Can you please address these issues? Thank you Re: RTD 5.0.0 documentation unclarities Hi @Jasmin_IM, Unfortunately, there is not a LLCE version that has been tested with the RTD 5.0.0 yet. I recommend waiting until a new LLCE version releases with test on the RTD 5.0.0 to port all your application to this RTD version. I found the tested versions at the LLCE Release notes: [page 2, Release Notes for LLCE 1.0.8, Rev. 1, 02/2024] [page 2, Release Notes for LLCE 1.0.9, Rev. 1, 08/2024] There is not a list of the non-RTD components at the RTD release notes because the non-RTD components firmware is done with the RTD as base, each non-RTD components mentions the RTD versions used to test develop/test it at each release notes. Referring to the bugs you mention it are part of the change list, so that means that bugs are already fixed in the current version of RTD.  Let me know if you have more questions. 

s32g BootRom & reset Hi, Dear nxp fellow: I have some questions when reading the S32G3 RM manual recently. 1. When reading the Boot chapter of the s32g3 RM manual, it mentions boot The HSE_H core begins executing firmware from the HSE_H ROM module that contains the BootROM firmware. So I would like to ask, where is the bootrom stored, doesn't the s32g3 have on-chip flash, and what is the size of the bootrom? I didn't see it in the attached "S32G3_memory_map.xlsx" table 2. Pass control to outside the HSE_H subsystem,Is it possible to specify M7 or A53? In a non-secure boot, firmware passes control to customer software that runs on a processor core that is outside the HSE_H subsystem. 3. In RDB3 Schematic,the "SOFT_RESET" it determines whether some S32G3 pins are connected to BOOT_RCON or other peripherals. I know that SOFT_RESET is high after power-on, so that the S32G3 pins are no longer connected to BOOT_RCON, but I don't know the specific time, such as after the PMIC is stable or other Please help answer the above questions,thanks Re: s32g BootRom & reset Hello @jiajun_cheng, Here are my answers to your questions:  Q1) When reading the Boot chapter of the s32g3 RM manual, it mentions boot The HSE_H core begins executing firmware from the HSE_H ROM module that contains the BootROM firmware. So I would like to ask, where is the bootrom stored, doesn't the s32g3 have on-chip flash, and what is the size of the bootrom? I didn't see it in the attached "S32G3_memory_map.xlsx" table A1) The bootROM is stored in the S32G3, the exact details about the implementation of how it is stored, accessed and executed are not publicly available. In any case, it is not configurable or customizable in any way, so you won't have to worry about it. Q2) Pass control to outside the HSE_H subsystem, Is it possible to specify M7 or A53? In a non-secure boot, firmware passes control to customer software that runs on a processor core that is outside the HSE_H subsystem. A2) Yes it is possible to select M7 or A53, you can learn mor about it in this app note AN13456 - S32G3 Boot Process, in particular check page 8: You can learn more about the IVT in the reference manual [page 1320, S32G3 Reference Manual, Rev. 4, 02/2024 ]: Q3) In RDB3 Schematic,the "SOFT_RESET" it determines whether some S32G3 pins are connected to BOOT_RCON or other peripherals. I know that SOFT_RESET is high after power-on, so that the S32G3 pins are no longer connected to BOOT_RCON, but I don't know the specific time, such as after the PMIC is stable or other A3) as you can see from the schematic, this signals depends on the PMIC's PGOOD signal: the VR5510 releases the reset pin only after all the voltage lines have the correct values, this means that the SOC does not have control over the delay for the reset release [page 15 of the VR5510 datasheet, Rev. 6 — 31 July 2023]: it is also possible to add a delay to this process via an one time programable (OTP) register. [page 177]: Let me know if this fully answers your questions.

PCA9617波形 该电路与 PCA9600 配合良好，但为了降低成本，我修改了电路板以使用 PCA9617 并检查了波形。 观察时钟波形，没有特别的失真， 所以看起来没有问题，但是在数据波形输出低电平的时候， 我观察到在时钟下降沿被拉高的波形。 我想知道这是否是由于时钟和数据之间的串扰造成的（安装 PCA9600DPZ 时没有问题）， 或者是修改电路板图案（图案切割/电缆焊接）的效果？ 我将非常感激您的意见。