Hi, Dear nxp fellow:
I have some questions when reading the S32G3 RM manual recently.
1. When reading the Boot chapter of the s32g3 RM manual, it mentions boot
The HSE_H core begins executing firmware from the HSE_H ROM module that contains the BootROM firmware.
So I would like to ask, where is the bootrom stored, doesn't the s32g3 have on-chip flash, and what is the size of the bootrom? I didn't see it in the attached "S32G3_memory_map.xlsx" table
2. Pass control to outside the HSE_H subsystem,Is it possible to specify M7 or A53?
In a non-secure boot, firmware passes control to customer software that runs on a processor core that is outside the HSE_H subsystem.
3. In RDB3 Schematic,the "SOFT_RESET" it determines whether some S32G3 pins are connected to BOOT_RCON or other peripherals. I know that SOFT_RESET is high after power-on, so that the S32G3 pins are no longer connected to BOOT_RCON, but I don't know the specific time, such as after the PMIC is stable or other
Please help answer the above questions,thanks
Hello @jiajun_cheng,
Here are my answers to your questions:
Q1) When reading the Boot chapter of the s32g3 RM manual, it mentions boot
The HSE_H core begins executing firmware from the HSE_H ROM module that contains the BootROM firmware.
So I would like to ask, where is the bootrom stored, doesn't the s32g3 have on-chip flash, and what is the size of the bootrom? I didn't see it in the attached "S32G3_memory_map.xlsx" table
A1) The bootROM is stored in the S32G3, the exact details about the implementation of how it is stored, accessed and executed are not publicly available. In any case, it is not configurable or customizable in any way, so you won't have to worry about it.
Q2) Pass control to outside the HSE_H subsystem, Is it possible to specify M7 or A53?
In a non-secure boot, firmware passes control to customer software that runs on a processor core that is outside the HSE_H subsystem.
A2) Yes it is possible to select M7 or A53, you can learn mor about it in this app note AN13456 - S32G3 Boot Process, in particular check page 8:
You can learn more about the IVT in the reference manual [page 1320, S32G3 Reference Manual, Rev. 4, 02/2024 ]:
Q3) In RDB3 Schematic,the "SOFT_RESET" it determines whether some S32G3 pins are connected to BOOT_RCON or other peripherals. I know that SOFT_RESET is high after power-on, so that the S32G3 pins are no longer connected to BOOT_RCON, but I don't know the specific time, such as after the PMIC is stable or other
A3) as you can see from the schematic, this signals depends on the PMIC's PGOOD signal:
the VR5510 releases the reset pin only after all the voltage lines have the correct values, this means that the SOC does not have control over the delay for the reset release [page 15 of the VR5510 datasheet, Rev. 6 — 31 July 2023]:
it is also possible to add a delay to this process via an one time programable (OTP) register. [page 177]:
Let me know if this fully answers your questions.