Multi Source Translation Content

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

Multi Source Translation Content

讨论

排序依据:
FLEXPWM outputs I need 5 different PWM outputs with adjustable different frequency and different duty cycle. I am using IMXRT1176 and it has 4 PWM peripherals from PWM1 to PWM4. I am using all physical ouptut pins of PWM2, PWM3 and PWM4 for another ICs.(for SDRAM and ENET connections.)  So I have only PWM1 available for my task. - FLEXPWM1_PWM0_A (N12 pin) - FLEXPWM1_PWM0_B (R14 pin) - FLEXPWM1_PWM1_A (R13 pin) - FLEXPWM1_PWM1_B (P15 pin) - FLEXPWM1_PWM2_B (P13 pin) The above PWM1, I can adjust different output frequency and duty cycle separately for each except (R14 pin) and (P15 pin).  For  (R14 pin) and (P15 pin), I can adjust different duty cycle but not adjust different frequency. Because both are connected to the same sub module of PWM1. How can achieve to use 2 extra PWM ouptuts that I need with different freq and duty cycle? Thanks. i.MXRT 106x Re: FLEXPWM outputs @MultipleMonomials  thank you very much for sharing very valuable information with us. You are right. By using XBARA peripheral, I can use 11 seperate PWMs with different frequency and different duty cycle adjustable each. I am not sure why NXP support team not well guide me in a right way.  I have tested it on my eval board imxrt1166 with adding following lines; I share with anyone who needs  more PWM outputs in addition to existing peripheral output pins pyhsically. With using XBARA, all FLEXPWM1-2-3-4 sub-module outputs can be directed/routed to XBARA physical output pins. BOARD_PWM_BASEADDR->SM[3].TCTRL = PWM_TCTRL_PWAOT0(1) | PWM_TCTRL_PWBOT1(1); //FLEXPWM1_PWM3SUBMODULE_A //FLEXPWM1_PWM3SUBMODULE_B XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputFlexpwm1Pwm3OutTrig0, kXBARA1_OutputIomuxXbarInout18); and add below lines to pin_mux.c files; IOMUXC_GPR->GPR20 |= IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18(0x01); IOMUXC_SetPinMux(IOMUXC_GPIO_AD_34_XBAR1_INOUT18, 0U); // FLEXPWM1_PWM3_A Re: FLEXPWM outputs Another option here would be to route the signals from PWM2, 3, or 4 to other pins via the XBAR.  PWM signals can be routed through the XBAR via PWM register settings, see here for some more info. Re: FLEXPWM outputs @Gavin_Jia Do you have any suggestion about the problem? 回复: FLEXPWM outputs Hello @Gavin_Jia . I am working on FLEXIO, today . I viewed the "flexio_pwm" example in SDK. I applied it on my eval board to see its effect. I changed my previous two PWM pins to FLEXIO. See the below pls: IOMUXC_SetPinMux(IOMUXC_GPIO_AD_00_FLEXIO2_D00, 0U);  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_FLEXIO2_D02, 0U);  Later, I observed two signals on oscilloscope. I adjusted two pins as different freq and duty cycles as FLEXIO. My observation is as follows; - When I set some freq values for my two pins, one of the signal is not set at programmed freq value, instead it produces different freq. Such as when I set freq to 13KHz, I see it on scope screen as 49KHz or something different. This is true for 15,10,12,18Khz. However when setting to 20Khz, it is set as correctly. So, some freq values are not programmed well. For another Flexio signal, it is always set to 50KHz and always correct during my observation. - When I set only one of my signals, freq value is correctly programmed to 12,13,15,18,20,30Khz. No problem exists. Setting single pin works as expected. However, as I stated above, setting 2 pins yield unexpected results.Why? - Lastly, whether setting single or both Flexio output pins; When I set freq value below 12Khz, the example in SDK, is not working because of below lines;  #define FLEXIO_MAX_FREQUENCY (DEMO_FLEXIO_CLOCK_FREQUENCY / 2U) #define FLEXIO_MIN_FREQUENCY (DEMO_FLEXIO_CLOCK_FREQUENCY / 512U) Even though I changed FLEXIO_MIN_FREQUENCY as  DEMO_FLEXIO_CLOCK_FREQUENCY / 4096U value, I can not program freq value to flexio pins correctly. I tried that for only setting my single FLEXIO signal and both. However every time I saw the wrong freq setting on oscilloscope screen. Demo example and the .pdf link you sent, uses 48KHz pwm freq for only one output pin. I tried to change freq values lower than 12KHz, but it is not working as expected. Freq settings get wrong every time evn though I lowered FLEXIO_MIN_FREQUENCY macro. - Is there any limitation with setting lower freq with using Flexio? Below 12Khz is possible? Such as 500Hz or 1Khz? Wait your helps.Thanks  回复: FLEXPWM outputs Hi @burhanhagi , Thanks for your interest in NXP MIMXRT series! In this usage scenario, hardware resources are limited, so we can consider using FlexIO to generate PWM.  FlexIO is an on-chip peripheral available on NXP I.MXRT series. It is a highly configurable module capable of emulating a wide range of communication protocols, such as UART, I2C,SPI, and I2S. Users can also use FlexIO to generate PWM and PFM waveform. The standalone peripheral module FlexIO is not used for replacement of the PWM and PFM generator, but as an additional peripheral module of the MCU. This module enable users to build their own peripheral directly in the microcontroller. It is suggested to refer to this application note, as well as the flexio_pwm demo in the SDK: Best regards, Gavin
查看全文
FTM0でPWMとICを使用することに疑問 PWM_PALを使用して、FTM0チャネル1、3、7でPWMを生成し、入力キャプチャ立ち上がりエッジコールバックFTM0チャネル2および6を手動で初期化します。 SDKの設定から、同じFTM0周辺機器を使用してIC_PALとPWM_PALを使用/設定できないことは明らかです。そこで、PWM_PALを使用してPWMチャネルを設定し、FTM0チャネル2および6の立ち上がりエッジを検出するために入力キャプチャを手動で初期化する方法を取りたいと思います。 それが可能かどうか、status = PWM_Init(&pwm_pal_1_instance, &pwm_pal_1_configs); PWM(1、3、および7)として設定されているチャネルにのみ影響し、FTM0の他のチャネル(2および6)は入力キャプチャ(立ち上がり/立ち下がり/立ち下がり)エッジ入力として設定できます。 これらの設定は、プロジェクトの要件に基づいて必要です。 Re: FTM0 で PWM と IC を使用することに疑問 Hi@Shail_meera おっしゃる通り、ICRSTビットを設定してから、他のタイマーを使用してトリガーイベントの時間を記録することはできません。あなたはそれを好きなように自由に設定することができますが、これは推奨される使用法ではなく、参照するためのそのようなルーチンはありません。 Re: FTM0 で PWM と IC を使用することに疑問 つまり、すべての入力キャプチャイベントでFTM0_COUNT FTM0で一般的に使用される0にリセットされます。 各チャネルで使用されるレジスタ CnSC があり、ICRST = 0 を設定してもFTM0_COUNT値はリセットされません。これにより、同じFTM0インスタンスを使用した入力キャプチャを使用できるようになります。 入力キャプチャには、立ち上がり/立ち下がりエッジでの割り込み呼び出しのみが必要であり、LPTMRを使用して2つの立ち上がりエッジ間のカウントを測定することで周波数を計算しています。 FTM0 1、3、および 7 に PWM 出力を持ちながら、FTM0 チャネル 2 からの入力周波数を測定するソリューションが必要です。 Re: FTM0 で PWM と IC を使用することに疑問 Hi@Shaik_meera SDKに関連するだけでなく、FTMの機能もあります。 私の提案は、PWM出力機能と入力キャプチャ機能をそれぞれ実装するために、2つのFTMモジュールを使用する必要があるということです。 Input Capture では、キャプチャ イベントが検出されると、カウンタがリセットされ、PWM 出力に影響します。 Re: FTM0 で PWM と IC を使用することに疑問 これを行う別の方法はありますか。Cコードのみを使用してPWMとICの両方を手動で初期化している可能性があります。これを行う例はありますか? Re: FTM0 で PWM と IC を使用することに疑問 Hi@Shaik_meera いいえ、あなたはまだそれを達成することはできません、 Re: FTM0 で PWM と IC を使用することに疑問 Hi@Shaik_meera いや、これはできません、 PWMとICには、それぞれ2つの異なるFTMインスタンスを使用する必要があります。
查看全文
Wire ACK FAULT Hi, when our team working project we faced Wire ACK fault. While dumping code we are facing the Wire ACK fault. Some how we found the scenario to make to avoid the Wire ack Fault. Working scenario: 1) power UP the board 2) Then connect the USB for Programming. Fault Scenario: A) 1) power UP the board 2) Then connect the USB for Programming. in this scenario if i remove the USB cable first and then removing power supply, it leads to Wire ack fault after this when even i follow the working condition procedure.  B)  1) connect the USB for Programming. 2) power UP the board.         above this also leads to wire ack fault. There is only way to overcome is by using MCUxpresso secure provisioning tool to write new image.  Any comments or suggestion please let mw know.  @RT1170 @kerryzhou @nxp  Regards, Sandeep C Re: Wire ACK FAULT As per the MCU link user manual we need to remove R16 if we are facing  wire ack issue. Regards, Sandeep C Re: Wire ACK FAULT Yes,. We are using custom board Regards  Sandeep  Re: Wire ACK FAULT Hello, in other words, are you using a custom board? Best regards, Pavel Re: Wire ACK FAULT Hi Thanks for the reply Even now also it's working with the first scenario(working scenario). We need eliminate the fault scenarios. Our requirements which ever we connect first it should work, either we connect USB or power up the board. @Pavel_Hernandez  Regards, Sandeep C Re: Wire ACK FAULT Hello, my name is Pavel, and I will be supporting your case, the scenario that you describe looks like a good behavior because the communication was lost through USB. Is this scenario working in the past?  Best regards, Pavel
查看全文
串行下载器运行时 FlexSPI 配置? 在 i.MX RT1021 上,将 eFuses 设置为从串行 NOR 闪存启动(BOOT_CFG1[7:4] = 0 ]),如果它在串行下载器模式下运行,并且我使用 JTAG 调试器进行中断,我是否应该能够看到 flexSPI 上连接的串行 NOR 闪存设备的内容? IEbootROM 串行下载应用程序是否正确配置 flexSPI 来访问闪存? 读取 FlexSPI/MCR0 寄存器(@0x402a8000),结果为:0xffff80c2 这使得 MCR0[MDIS] 位 = 1,禁用整个 flexSPI 接口!我根本无法(通过 JTAG 调试器)清除 [MDIS] 位。 内存读取到 0x60000000(闪存的开始)读取的是乱码;但 MCUExpresso GUI 闪存工具写入并验证那里有一个 FCFB 块。 i.MXRT 102x 回复:串行下载器运行时的 FlexSPI 配置? 谢谢你,Deigo。我还可以找到与其一起使用的 Kinetis 引导加载程序映像和主机 PC blhost 应用程序。使用 sdphost,我能够将引导加载程序映像上传到 MCU RAM 并在 MCU 处于串行下载模式时使用它来查看。
查看全文
Serial Downloader実行時のFlexSPI構成は? i.MX RT1021 で eFuse を serialNOR フラッシュ (BOOT_CFG1[7:4] = 0) から起動するように設定し、Serial Downloader モードで実行していて、JTAG デバッガでブレークインした場合、接続されている Serial NOR Flash デバイスの内容を flexSPI で表示できますか。 つまりbootROM シリアル ダウンロード アプリケーションは、フラッシュにアクセスするために flexSPI を正しく設定していますか? FlexSPI/MCR0レジスタ(@0x402a8000)を読み取ると、次のように表示されます0xffff80c2 これにより、MCR0[MDIS]ビット= 1になり、flexSPIインターフェース全体が無効になります。私は(JTAGデバッガを介して)[MDIS]ビットをまったくクリアできません。 メモリは0x60000000(フラッシュの開始)に読み取って意味不明な読み取りをします。ただし、MCUExpresso GUI フラッシュ ツールは、そこに FCFB ブロックが書き込まれ、検証されます。 i.MXRT 102倍 Re:シリアルダウンローダー実行中のFlexSPI構成? Deigoさん、ありがとうございました。また、Kinetisブートローダイメージとそれを使用するホストPCのblhostアプリケーションも見つけることができました。sdphostを使用すると、ブートローダーイメージをMCU RAMにアップロードし、MCUがシリアルダウンロードモードにあるときにそれを使用して周囲を見回すことができました。
查看全文
S08PT60 EVK 板 TSI 模块配置 我正在使用 s08 开发板来配置 TSI。我已经下载了 evk 板的示例代码,并尝试获取触摸感应输入来改变板上 RBG led 的状态。它不起作用。我也查看了应用笔记AN4431。我尝试使用硬件触发器来获取输入。有人能帮我分析一下吗? 回复:S08PT60 EVK 板 TSI 模块配置 你好@Itzzamna_Supp , 谢谢您的回复。我已经编辑了示例代码。在s08pt60_evk_board.c中示例代码文件中,作者注释了Touchpad_Init()函数内部的TSI_Init()函数。我调用了该函数并尝试了,但是开发板上的触摸板不起作用。 回复:S08PT60 EVK 板 TSI 模块配置 我懂了。据我了解,该 S08PT60 EVK 网站上的示例代码适用于加速度计和 RGB LED 示例应用程序。因此,当你移动电路板时,LED 应该会改变颜色。另外,这意味着该代码不适用于触摸感应输入,我已经验证了代码并且触摸感应端口尚未设置。此外,TSI 也没有包含在此示例代码中,这可能是 TSI 和触摸感应输入不起作用的原因。 您可能需要为此 MCU 创建一个新项目或编辑示例代码以正确设置 TSI 和触摸感应输入。 回复:S08PT60 EVK 板 TSI 模块配置 是的,我尝试了相同的示例代码。 回复:S08PT60 EVK 板 TSI 模块配置 感谢您联系我们!我叫 Itzamna Fuentes,我将负责此案。   您能否确认您下载的示例代码位于下一个链接中? https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/s08p-mcus-evaluation-kit:S08PT60-EVK 我想尝试一下,所以我下载了 S08PT60-EVK 示例代码,这是您正在使用的吗?
查看全文
The s32k312 retains part of the SRAM interval to store data, causing the system to crash first i did some changes in the linker doc "linker_flash_s32k312.ld" then i use this section likes follow: when i did a line like this " if( eBootFlag == 0xAA) ", i got data from this section when power off the MCU and then power it on 5v. This line of code will crash the system. i want to know if there some wrong thing i did. Re: The s32k312 retains part of the SRAM interval to store data, causing the system to crash thanks @Senlent  I chose the area where SRAM starts and then i choose not to  I chose not to initialize the SRAM at the time of the function event reset . the sram data i put in doesn't change. Re: The s32k312 retains part of the SRAM interval to store data, causing the system to crash Hi@yiyiyinyi So your first problem is that "int_sram_ebotflg" is not initialized, right? You can try to modify it in this way. You still modify the link file as in the first problem, and then: The program enters main() 1. Determine the reason for the MCU reset 2. If the last reset of the MCU is a functional reset, do not initialize "int_sram_ebotflg" 3. Otherwise, initialize the "int_sram_ebotflg" area This should be able to solve your problem Re: The s32k312 retains part of the SRAM interval to store data, causing the system to crash so i need to change Sd32? Where do you suggest I should change it? Re: The s32k312 retains part of the SRAM interval to store data, causing the system to crash Hi Senlent thanks for your reply. i did some changes , _INT_SRAM_END which single is in the  startup file . _INT_SRAM_END equal to ram_rsvd2 , so it is can't be initialized. but if i distribute the SRAM as shown in the figure below  : After the following code is executed, the value in SRAM will be initialized to 0, but will Function Event Reset not change the value in SRAM? so where should i to change make sure this data can‘t be changed if i choose "ram_rsvd2 : ORIGIN = 0x20418000, LENGTH = 0", The selection of SRAM is distributed in this way. Re: The s32k312 retains part of the SRAM interval to store data, causing the system to crash Hi@yiyiyinyi 1. Make sure that the SRAM must be initialized before use The link file provided by NXP has already initialized the SRAM in the startup file. If the user modifies the link file, then it is necessary to ensure that the modified SRAM area is initialized. 2. Is the MPU configured correctly? You can turn off the MPU and try again you can disable MPU like below shows and try again. Re: The s32k312 retains part of the SRAM interval to store data, causing the system to crash Is it because of the power failure and rewriting the SRAM region? But if I take a value in this area, why does it crash? I spent a lot of time, but I still haven't solved this problem. Can you tell me, where is my problem?
查看全文
S32K3 DFSR Where can I find information about the S32K3 DFSR? Re: S32K3 DFSR Hi @kjy106906, That's here: https://developer.arm.com/documentation/ddi0403/d/Debug-Architecture/ARMv7-M-Debug/Debug-register-support-in-the-SCS/Debug-Fault-Status-Register--DFSR?lang=en Regards, Daniel Re: S32K3 DFSR Thank you @danielmartynek  But I inquired about DFSR and not HFSR Can you explain DFSR? Re: S32K3 DFSR Hello @kjy106906, ARM documentation of the CM7 core: https://developer.arm.com/documentation/dui0646/c/Cortex-M7-Peripherals/System-control-block/HardFault-Status-Register Regards, Daniel
查看全文
What should the LPC84x FLASHTIM register be set to? Hello Team, My customers are using LPC845 and they frequently encounter a HardFault while debugging. Their painstaking analysis revealed that it was related to the FLASHTIM register. They are using a 30MHz system clock, in which case setting FLASHTIM=1 will prevent the HardFault. I found similar posts in the community, but the Flash access time specifications are not clear here. https://community.nxp.com/t5/LPC-Microcontrollers/LPC8xx-Flash-access-time-aka-setting-FLASHTIM/m-p/1186229 In other LPC series it is clearly stated in UM. Ex LPC111x : Ex LPC546xx : However, this point is not clearly stated in the LPC84x UM. Please clarify the specifications related to FLASHTIM so that customers can freely handle the system clock. Thanks, George LPC800 Re: What should the LPC84x FLASHTIM register be set to? hello @xiangjun_rong, There is no sample code that uses the CLOCK_SetFLASHAccessCyclesForFreq() in the latest SDK, so few users will notice its existence. In any case, our question is answered. Thank you for your detailed answer. BR, George  Re: What should the LPC84x FLASHTIM register be set to? Hi, Unfortunately, the section  6.4.1 Flash configuration register in UM11029.pdf has not any update till now. But the SDK package adds a function to set up the FLASHTIM bits in FLASHCFG reg. The core frequency of LPC84x can reach up to 30MHz, if the core frequency is less than 24Mhz, you set the FLASHTIM bits as 0, which means 1 clock cycle delay. if the core frequency is equal or greater than 24Mhz and less than 30Mhz, you set the FLASHTIM bits as 1, which means 2 clock cycle delay. The void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) api function input variable is the actual core frequency, it set up the FLASHTIM bits based on the core frequency. Hope it can help you BR XiangJun Rong Re: What should the LPC84x FLASHTIM register be set to? Hello @xiangjun_rong  Thanks for the reply, as far as I know I can't find that information anywhere in the NXP documentation. In other words, So does that mean the flash access time needs to be 24MHz or less as a chip specification? Thanks, George Re: What should the LPC84x FLASHTIM register be set to? Hi, I suppose the SDK team has addressed the issue. Pls download SDK package from the website: https://mcuxpresso.nxp.com/en The SDK version has updated to 2.16.000, which has added a function void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) to solve the issue. /*! brief Set the flash wait states for the input freuqency. * param iFreq : Input frequency */ void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) { uint32_t num_wait_states; if (iFreq <= 24000000UL) { /* [0 - 24 MHz] */ num_wait_states = 0UL; } else { /* Above 24 MHz */ num_wait_states = 1UL; } FLASH_CTRL->FLASHCFG = ((FLASH_CTRL->FLASHCFG & ~FLASH_CTRL_FLASHCFG_FLASHTIM_MASK) | FLASH_CTRL_FLASHCFG_FLASHTIM(num_wait_states)); } when the core frequency is less than 24MHz, 1 clock cycle is added. when the core frequency is above 24MHz, 2 clock cycle is added.  For the user manual update, it requires time. Hope it can help you BR XiangJun Rong
查看全文
Increasing swap memory for S32G2 Hello all, I have loaded the A53 with the fsl-base-image. I checked the RAM utilisation and it shows that the allocated space for swap memory is 0 bytes. How can I increase this? Do I have to make any configuration changes in the Yocto files? Please let me know. Best, Vishnu  Re: Increasing swap memory for S32G2 Hello, @Vishnu3 Thanks for the reply. Sorry that I do not find related information from BSP document, from my experience, you may have to firstly rebuild the kernel with CONFIG_SWAP=Y, once booting the system, the following link could be used for your reference. https://docs.oracle.com/cd/E24457_01/html/E21988/giprn.html BR Chenyin Re: Increasing swap memory for S32G2 Hi @chenyin_h , Thanks for the response. We are running cmake to build a library and that's consuming the RAM. This is a one time thing but we need it. Do you have any resources which I can use to configure the kernel to include the swap feature? Best, Vishnu  Re: Increasing swap memory for S32G2 Hello, @Vishnu3  SWAP memory is by default disabled in kernel configurations, from my experiece, the swap is not very commonly used in embedded systems, since there is not usually a large size HD attached. If you do have RAM limitation issue and need the feature, then you may enable it from kernel configuration, but it is not tested from BSP perspective. BR Chenyin
查看全文
S32k312 在S32DS 工具中配置CANFD功能 请问: 1.S32K312 在S32DS 工具中配置CANFD功能 ,发现有Drivers 和MCAL两项,如果只在RTOS中使用是不是只需要在Drivers添加CAN Driver即可? 2.是否有CANFD功能只在RTOS使用的Demo code,或是CANFD配置及收发流程? Re: S32k312 在S32DS 工具中配置CANFD功能 Hi@Bert2023 1.RTD驱动提供了两种开发方式来满住客户的需求,其包涵了LLD和HLD两个独立的部分,分别对应Drivers和MCAL,对于有Autosar需求的人,可以选择MCAL来配置亦或者使用EB(推荐),如果没有Autosar要求,那么Drivers更合适,其配置更直观简洁。 所以你直接使用Drivers的FlexCAN组件即可。 2.我可以给你一些配置CAN的用例,但是如果你想要一个FreeRTOS的FlexCAN收发例程,我想我们是没有的,FreeRTOS是一个第三方提供的,我们不去支持FreeRTOS的问题(这应该不难做,参考我们提供的例程应该很容易实现)。 你可以看看下面的例程,S32K3的FlexCAN模块用法都是几乎一样的 https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K358-FlexCAN-TXRX-ISR-S32DS35-RTD400/ta-p/1981987
查看全文
S08PT60 EVK Board TSI module configuration I'm working on s08 development board to configure the TSI. I've downloaded the sample codes of the evk board and tried to get touch sense input to change the status of the RBG led on the board. It's not working. I've also checked the application note: AN4431 for the same. I tried the hardware trigger to get the input. Can someone give me an insight on this? Re: S08PT60 EVK Board TSI module configuration Hi @Itzzamna_Supp, Thanks for the reply. I've edited the sample code. In the s08pt60_evk_board.c file of the sample code, the author commented the TSI_Init() function inside the Touchpad_Init() function. I called that function and tried, but the touchpad on the development board is not working. Re: S08PT60 EVK Board TSI module configuration I see. From my understanding, the sample code that is on the website for this S08PT60 EVK is for the accelerometer and RGB LED sample application. Therefore, the LED should change the color when you move the board. Also, this means that this code is not for the touch sense input, I already validate the code and the Touch sense ports are not setup. In addition, the TSI is also not included in this sample code which could be the reason why the TSI and the Touch sense inputs are not working. You may need to create a new project for this MCU or edit the sample code to setup the TSI and touch sense inputs correctly. Re: S08PT60 EVK Board TSI module configuration Yes, the same sample code was I tried.  Re: S08PT60 EVK Board TSI module configuration Thanks for reaching us! My name is Itzamna Fuentes and I'll be attending this case.   Can you please confirm that the Sample code that you downloaded is located in the next link? https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/s08p-mcus-evaluation-kit:S08PT60-EVK I would like to give it a try so I downloaded the S08PT60-EVK Example Codes, is that the one that you are using?
查看全文
DQS-DQ skew with LPDDR4 in i.MX93EVK Hello. I am in charge of transmission line simulation at a board design company. I was asked by a customer to start a board design using i.MX93 and I used the HyperLynx DDRx batch wizard to analyze LPDDR4 using i.MX93EVK board data. The IBIS model for the DRAM was MT53E1G16D1ZW from z42n_1p1v_at.ibs referring to the i.MX93EVK schematic, and the observation points were performed on the die. Looking at the analysis results without leveling, it seems that the DQS-DQ skew is way off and there is little margin on the Hold side. The hardware guide describes routing constraints for delay time, but are these constraints specified as the range of phase adjustment based on the assumption of delay and leveling operation in the package on the DRAM side? Is the range that can be adjusted by leveling described anywhere? The attached image is the result of HyperLynx analysis and the eye mask is the default setting of HyperLynx, not the i.MX93 specification Re: DQS-DQ skew with LPDDR4 in i.MX93EVK Hi, @TTamura_Apollo_Giken  Our EVK PCB design has been proven, So if you have following the HDG file, then your board is no problem. And you can use the Config Tool run the vTSA test. B.R Re: DQS-DQ skew with LPDDR4 in i.MX93EVK Hi @pengyong_zhang  Thanks for the reply. Is it your understanding that as a device manufacturer, you guarantee operation by following the hardware design guide and matching the delay time of the PCB wiring design? In the simulation, is it enough to confirm that the adjusted time is within the leveling range by performing Write leveling, and that the i.MX93 eye mask regulations are satisfied as signal quality? Re: DQS-DQ skew with LPDDR4 in i.MX93EVK Hi, @TTamura_Apollo_Giken  >>>Is it assumed that even if there is a phase difference (wire length difference) between DQS and DQ in i.MX93EVK, it will be adjusted by leveling? Yes! >>>the i.MX93 package delay and PCB routing delay alone are specified, but does this mean that the specified values are such that problems do not occur without considering the DRAM package delay? It is the design range, The DDR training will calibration the DQS2DQ, and this is fine-tuned and must be based on meeting the PCB design. Re: DQS-DQ skew with LPDDR4 in i.MX93EVK Hi @pengyong_zhang  JEDEC 209-4B confirmed. LPDDR4-3200 read as follows TdIVW_total max:0.25UI tDQS2DQ min:200ps / max:800ps tDQ2DQ max:30ps Is it assumed that even if there is a phase difference (wire length difference) between DQS and DQ in i.MX93EVK, it will be adjusted by leveling? Also, the i.MX93 package delay and PCB routing delay alone are specified, but does this mean that the specified values are such that problems do not occur without considering the DRAM package delay? Translated with DeepL.com (free version) Re: DQS-DQ skew with LPDDR4 in i.MX93EVK Hi JEDEC 209-4B confirmed. LPDDR4-3200 read as follows TdIVW_total max:0.25UI tDQS2DQ min:200ps / max:800ps tDQ2DQ max:30ps Is it assumed that even if there is a phase difference (wire length difference) between DQS and DQ in i.MX93EVK, it will be adjusted by leveling? Also, the i.MX93 package delay and PCB routing delay alone are specified, but does this mean that the specified values are such that problems do not occur without considering the DRAM package delay? Re: DQS-DQ skew with LPDDR4 in i.MX93EVK Hi, @TTamura_Apollo_Giken  Different DDR type have different Spec document, For i.MX93 LPDDR4, you can refer JEDE209-4C. B.R Re: DQS-DQ skew with LPDDR4 in i.MX93EVK Hi We were aware that the range that can be supported by leveling depends on the DDR controller. Also, the JEDEC standard is a specification for the DRAM side, so we do not know the specifications for the controller side. The old i.MX6 datasheet included DDR2/3 timing specifications, but the recent DDR timing specifications are not included, so we do not know the controller specifications. Re: DQS-DQ skew with LPDDR4 in i.MX93EVK Hi, @TTamura_Apollo_Giken  About all of the DRAM range that can be adjusted by leveling, you can find it on JEDEC spc document. B.R
查看全文
S08PT60 EVKボードTSIモジュール構成 TSIを構成するためにs08開発ボードに取り組んでいます。evkボードのサンプルコードをダウンロードし、タッチセンス入力を取得して、ボード上のRBG LEDのステータスを変更しようとしました。うまく行きません。また、アプリケーションノートAN4431も確認しました。入力を取得するためにハードウェアトリガーを試しました。誰かが私にこれについての洞察を与えることができますか? Re:S08PT60 EVKボードTSIモジュール構成 こんにちは @Itzzamna_Supp、 返信ありがとうございます。サンプルコードを編集しました。s08pt60_evk_board.c でサンプルコードのファイルで、著者は Touchpad_Init() 関数内の TSI_Init() 関数にコメントを追加しました。その機能を呼び出して試してみましたが、開発ボードのタッチパッドが動作しません。 Re:S08PT60 EVKボードTSIモジュール構成 なるほど。私の理解では、この S08PT60 EVK の Web サイトにあるサンプル コードは、加速度計と RGB LED のサンプル アプリケーション用です。したがって、ボードを移動するとLEDの色が変わるはずです。また、これは、このコードがタッチセンス入力用ではなく、すでにコードを検証し、タッチセンスポートが設定されていないことを意味します。さらに、TSIもこのサンプルコードに含まれていないため、TSIとタッチセンス入力が機能しない理由である可能性があります。 このMCU用に新しいプロジェクトを作成するか、サンプルコードを編集してTSIおよびタッチセンス入力を正しく設定する必要がある場合があります。 Re:S08PT60 EVKボードTSIモジュール構成 はい、私が試したのと同じサンプルコードです。 Re:S08PT60 EVKボードTSIモジュール構成 ご連絡いただきありがとうございます!私の名前はイツァムナ・フエンテスで、この事件に立ち会います。   ダウンロードしたサンプルコードが次のリンクにあることを確認できますか? https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/s08p-mcus-evaluation-kit:S08PT60-EVK 試してみたいので、S08PT60-EVKサンプルコードをダウンロードしましたが、それはあなたが使用しているものですか?
查看全文
S32DS creates S32K341 and S32K342 without J-LINK debugging options When I use S32DS to create the S32K344 project, I can choose GDB PEMicro and Segger in the debug options. However, when I create the S32K342/S32K341 project, only GDB PEMicro is available without the Segger option. How can I use J-LINK to debug my S32K341 project? 回复: S32DS creates S32K341 and S32K342 without J-LINK debugging options Hi@jiafeimao I forgot that J-LINK does not support S32K341&S32K342 Then it cannot be supported, because essentially S32 DS is implemented by calling J-link DLL. 回复: S32DS creates S32K341 and S32K342 without J-LINK debugging options Thank you for providing the information. S32K341 is not on SEGGER's support list. Are you aware of this? The following image shows the S32K3 series supported by SEGGER's J-LINK, which includes S32K342 and S32K344. Unfortunately, S32K341 is not included. We look forward to any suggestions from you. Re: S32DS creates S32K341 and S32K342 without J-LINK debugging options Hi@jiafeimao Here is a article to show you how to use J-Link in S32 DS. https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/S32-Design-Studio-for-S32-Platform-V3-4-V3-5-SEGGER-J-LINK-Plus/ta-p/1635798
查看全文
MCU Link デバッグプローブファームウェア V0.078は入手できますか? こんにちは、 私の環境ではバージョン11.9.0と11.9.1の両方が正しく動作しないため、現在MCUXpressoバージョン11.5.0を使用しています。 現在、問題について問い合わせていますが、まだ解決されていないため、常に解決策を探しています。 このような状況のため、現在使用しているMCU-LINK-DEBUG-PROBEをダウングレードしたいと思います。 私は3つ持っていますが、MCUXpresso 11.9.0以降で使用するために、そのうちの2つをV3.133に更新しました。 したがって、バージョン 11.5.0 で使用できるのは 1 つだけです。 また、MCU-LINK-DEBUG-PROBEのファームウェアバージョンは現在V0.078です。 そこで、MCUXpressoバージョン11.5.0で使用できる同じバージョンまたはバージョンを見つけたいと思います。 今は追加購入が無理で、もし故障したらもう働けなくなってしまうので不安です。 スクリプトを使用してアップグレードする方法は知っていますが、ダウングレードするファームウェアまたは工場出荷時設定へのリセット機能を見つけるのに苦労しています。 誰かが情報を見つける方法や場所を知っているなら、私は助けを大いに感謝します。 ありがとうございます。 Re:この段階での更新方法 インストール後、MCUリンクプローブを更新した後、MCUXpresso V11.10とPCでもまったく検出されません。FWにジャンパーを挿入した場合、その時間のみ検出します。 Re:MCU LinkデバッグプローブファームウェアV0.078を取得できますか? こんにちは@Alice_Yang。 ありがとうございます。 しかし、このコンテンツには添付ファイルが見つかりません。 メールでファイルを送ってくれた場合は、お知らせください。 メールが届いていないので、メールサーバー管理者に連絡して確認する必要があります。
查看全文
Issue with dpdk-l2fwd-crypto Application SW on Ubuntu 20.04 PC I am testing dpdk application in PC with PCI-E Dual-RJ45 gigabit NIC card to develop a network based application. I have started my project with dpdk 21.08 and Codewarrior IDE. PC details : uname -a Linux mglocadmin-ThinkCentre-M73 5.15.0-105-generic #115~20.04.1-Ubuntu SMP Mon Apr 15 17:33:04 UTC 2024 x86_64 x86_64 x86_64 GNU/Linux The following steps to install DPDK (Data Plane Development Kit) on Ubuntu 20.04: sudo apt update sudo apt install build-essential meson python3-pyelftools libnuma-dev pkgconf wget https://fast.dpdk.org/rel/dpdk-21.08.tar.xz tar -xf dpdk-21.08.tar.xz meson build ninja -C build meson -Dexamples=all build sudo ninja install sudo ldconfig Setup hugepage in PC: mkdir -p /dev/hugepages mountpoint -q /dev/hugepages || mount -t hugetlbfs nodev /dev/hugepages echo 64 > /sys/devices/system/node/node0/hugepages/hugepages-2048kB/nr_hugepages Setup NIC card in PC: sudo ifconfig enp2s0f1 down sudo ifconfig enp2s0f0 down cd / /dpdk-21.08/usertools/ sudo modprobe uio sudo modprobe uio_pci_generic sudo dpdk-devbind.py -b uio_pci_generic 02:00.0 sudo dpdk-devbind.py -b uio_pci_generic 02:00.1 dpdk-devbind.py -s Log "dpdk-devbind.py -s": Network devices using DPDK-compatible driver 0000:02:00.0 '82571EB/82571GB Gigabit Ethernet Controller D0/D1 (copper applications) 105e' drv=uio_pci_generic unused=e1000e,vfio-pci 0000:02:00.1 '82571EB/82571GB Gigabit Ethernet Controller D0/D1 (copper applications) 105e' drv=uio_pci_generic unused=e1000e,vfio-pci Network devices using kernel driver 0000:03:00.0 'RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller 8168' if=enp3s0 drv=r8169 unused=vfio-pci,uio_pci_generic *Active* cd / /dpdk-21.08/build/examples sudo ./dpdk-l2fwd -c 0x3 -n 4 -- -p 0x3 -q 8 --no-mac-updating Openssl and cryptodev details: mglocadmin@mglocadmin$ sudo modprobe cryptodev [sudo] password for mglocadmin: mglocadmin@mglocadmin$ openssl version OpenSSL 1.1.1f 31 Mar 2020 mglocadmin@mglocadmin$ ls /dev/crypto /dev/crypto NOTE : DPDK-L2fwd application is working But ,I am unable to get dpdk-l2fwd-crypto to function properly on my Ubuntu 20.04 system. I've checked the dependencies, ensured that DPDK is properly configured, and attempted various troubleshooting steps, but to no avail. ERROR log: sudo ./dpdk-l2fwd-crypto -l 1 -n 2 --vdev "crypto_openssl0" --vdev "crypto_openssl1" -- -p 0x3 --chain CIPHER_ONLY --cdev_type SW --cipher_algo aes-cbc --cipher_op ENCRYPT --cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f --cipher_iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f --no-mac-updating EAL: Detected 4 lcore(s) EAL: Detected 1 NUMA nodes EAL: Detected static linkage of DPDK EAL: failed to parse device "crypto_openssl0" EAL: Unable to parse device 'crypto_openssl0' EAL: Error - exiting with code: 1 Cause: Invalid EAL arguments kindly help us to resolve this issue. Re: Issue with dpdk-l2fwd-crypto Application SW on Ubuntu 20.04 PC After configuring PKG_CONFIG_PATH, you need to recompiling DPDK with "meson arm64-build" command. For details, please refer to section "Compiling DPDK using meson" in LSDK 21.08 user manual. Re: Issue with dpdk-l2fwd-crypto Application SW on Ubuntu 20.04 PC The step which i followed is below : mglocadmin@mglocadmin-ThinkCentre-M73:~/NIC/dpdk-21.08$ export PKG_CONFIG_PATH=/usr/local/ssl/lib/pkgconfig:$PKG_CONFIG_PATH mglocadmin@mglocadmin-ThinkCentre-M73:~/NIC/dpdk-21.08$ cd build/ mglocadmin@mglocadmin-ThinkCentre-M73:~/NIC/dpdk-21.08/build$ sudo ninja install mglocadmin@mglocadmin-ThinkCentre-M73:~/NIC/dpdk-21.08/build$ cd examples/ mglocadmin@mglocadmin-ThinkCentre-M73:~/NIC/dpdk-21.08/build/examples$ sudo modprobe cryptodev mglocadmin@mglocadmin-ThinkCentre-M73:~/NIC/dpdk-21.08/build/examples$ ls /dev/crypto /dev/crypto mglocadmin@mglocadmin-ThinkCentre-M73:~/NIC/dpdk-21.08/build/examples$ openssl engine (rdrand) Intel RDRAND engine (dynamic) Dynamic engine loading support mglocadmin@mglocadmin-ThinkCentre-M73:~/NIC/dpdk-21.08/build/examples$ sudo ./dpdk-l2fwd-crypto -l 1 -n 2 --vdev "crypto_openssl0" --vdev "crypto_openssl1" -- -p 0x3 --chain CIPHER_ONLY --cdev_type SW --cipher_algo aes-cbc --cipher_op ENCRYPT --cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f --cipher_iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f --no-mac-updating EAL: Detected 4 lcore(s) EAL: Detected 1 NUMA nodes EAL: Detected static linkage of DPDK EAL: failed to parse device "crypto_openssl0" EAL: Unable to parse device 'crypto_openssl0' EAL: Error - exiting with code: 1 Cause: Invalid EAL arguments Still same issue @yipingwang  Re: Issue with dpdk-l2fwd-crypto Application SW on Ubuntu 20.04 PC As I mentioned previously, please execute the following before building DPDK. export PKG_CONFIG_PATH= /lib/pkgconfig:$PKG_CONFIG_PATH Re: Issue with dpdk-l2fwd-crypto Application SW on Ubuntu 20.04 PC Thank you for reply @yipingwang ... But I was tried to build and run dpdk-l2fwd-crypto application in PC .so I am directly install DPDK not with flex-builder. Is there any configuration in DPDK i need to change or modify for enable openssl ? Re: Issue with dpdk-l2fwd-crypto Application SW on Ubuntu 20.04 PC Can you please check whether DPDK is being compiled with "openssl" library. Below path is must to compile DPDK with openssl:   export PKG_CONFIG_PATH= /lib/pkgconfig:$PKG_CONFIG_PATH   Please refer to the following line in flexbuild_lsdk2108_github/packages/apps/networking/dpdk.mk export PKG_CONFIG_PATH=$(DESTDIR)/usr/local/lib/pkgconfig:$(PKG_CONFIG_PATH) && \
查看全文
S32K3 マルチプレクサ ピン構成 2 つの入力ピンをマルチプレクサにできるように、2 つの入力ピンをどのように構成しますか。
查看全文
MPC5634 eTPU Crank Tooth period log get an err number When I was conducting engine tests, I encountered an eTPU crankshaft tooth counting error that caused the engine to no longer synchronize. When I check "*cpba_tooth_period_log" in “crank_instance_t",I foung some member become very small。 The experimental results are as follows.While running, etpu_tooth_period_log[80] suddenly drops from 33800 to 21800.And crank states err occur.The rest of the etpu tooth period log(log[0],log[40],log[119],) data looks normal.   I checked the input crankshaft original signal and there was no signal anomaly when the fault occurred.I tested the duration of the first 1 and 2 teeth of the failure,They all last around 820us. Here are some of my eTPU parameter matching values.       I also added an IO flag to the crankshaft interrupt function, which outputs the current state of the IO output after entering the interrupt.In the figure below, the blue signal is a sign that the entry crankshaft is interrupted.      Green indicates synchronization. When the green signal is high power level, it indicates non-synchronization("crank_states.eng_pos_state" is not "FS_ETPU_ENG_POS_FULL_SYNC").     As can be seen from the diagram, the crankshaft abnormal entry break caused the engine to no longer synchronize.   Could you help me analyze the cause of this problem and how to solve it? Thank you very much! Re: MPC5634 eTPU Crank Tooth period log get an err number You have solved my problem, thank you very much. However, I still have other puzzles in the use of eTPU. I have created a new topic as follows.... How to achieve single crankshaft and single camshaft synchronization and running eTPU program - NXP Community Re: MPC5634 eTPU Crank Tooth period log get an err number Hi Jasting, excellent observation! Thanks for pointing this out. I've created a similar setup, located the issue (after few minutes of execution) and ... fixed a bug in INJ. You can take the attached file and update the "_etpu_set" folder in the example application, or you can create a new eTPU function set yourself using CW eTPU Function Selector - the fix is already available there. Regards, Milan Re: MPC5634 eTPU Crank Tooth period log get an err number Thanks for your reply! I have connected ETPUA1 to ETPUA2 and ETPUA3 to ETPUA4.Have been collected to ETPUA10, ETPUA11 ETPUA12, ETPUA13 injection signal. I made some simple adjustments to the routine you gave me.I have added monitoring for injection status errors to each injection interrupt, with the "LED2_pin" output low when a fault occurs.All four channels are set this way.The state of this pin is externally observed through an oscilloscope.This pin is observed to be low after some time, indicating that an injection state failure has been detected.This is consistent with my previous tests. As shown in the figure below, I monitored the status signal for injection status errors (blue) and the signal for injection channel One (yellow). When the injection status error signal appears, there is a problem of injection signal loss. (Not every injection error is accompanied by injection signal loss, but every injection signal loss is accompanied by injection error) Re: MPC5634 eTPU Crank Tooth period log get an err number Hi Jasting, we created an example project for you. It includes eTPU code newly generated by CW Function Selector. It uses TG function to generate a CRANK & CAM pattern. In order to feed the CRANK and CAM inputs by TG outputs, connect eTPU A channel 1 and 2 (CRANK), and 3 and 4 (CAM). INJ outputs are on eTPU A channels 10, 11, 12, 13. INJ configuration mimics your case. Re: MPC5634 eTPU Crank Tooth period log get an err number Could you provide a eTPU2 test project that can work normally, so that I can test and troubleshoot problems? Re: MPC5634 eTPU Crank Tooth period log get an err number Yes, I've changed all of its configuration areas to 100. Re: MPC5634 eTPU Crank Tooth period log get an err number Did you change the injection parameters? Injection duration must not be 0. Re: MPC5634 eTPU Crank Tooth period log get an err number Whether or not the injector is connected, "inj_states_t.error" will periodically report the "FS_ETPU_INJ_ERROR_LATE_START_ANGLE_NTH" fault, and the frequency of the fault is related to the engine speed. The faster the speed, the faster the frequency. Re: MPC5634 eTPU Crank Tooth period log get an err number The following is the injector drive diagram.There is no associated pin to change the state. Re: MPC5634 eTPU Crank Tooth period log get an err number Interesting. The injector is connected to output pins, isn't it? May it prevent the output pins to change state? Check the pin drive strength is correct and it can toggle. I don't my yesterady's replay here in the chain. Hm, let me write it again. Re: MPC5634 eTPU Crank Tooth period log get an err number Thank you for the information. In addition, in my previous tests, the failure did not occur when the injector was not connected. But I'm not sure it's necessarily related. Re: MPC5634 eTPU Crank Tooth period log get an err number Thank you for the information. The first observation is the behaviour of the INJ function. The duration of each injection pulse is set to 0. According to the detailed scope, the first injection pulse is about 400 usec and the second about 800 usec. Duration of 0 is nonsence. It might cause a wrong order of events or something like that. Please try to set e.g. 100 usec duration of each injection. Next observation on the same detailed scope is that the injection duration of 800 usec corresponds to 1 tooth period. If there is a latency as long as one tooth on the eTPU engine, that would break the tooth processing and cause the synchronisation lost. I'm not sure where the latency might come from. Each event (transition or edge) should be processed within 2-5 usec. Anyway, the duration of injection pulse, set to 0 but generated as 800 usec, shows there might be such a latency. Please monitor INJ error variable: struct inj_states_t { uint8_t error; /**< This is the error status of INJ. It includes the following error flags: - @ref FS_ETPU_INJ_ERROR_PREV_INJ_NOT_FINISHED - @ref FS_ETPU_INJ_ERROR_LATE_START_ANGLE_1ST - @ref FS_ETPU_INJ_ERROR_LATE_START_ANGLE_NTH - @ref FS_ETPU_INJ_ERROR_STOPPED_BY_STOP_ANGLE The eTPU sets the error flags, the CPU clears them after reading. */ Generally, it is very difficult to find a bug which appears once per hours or days. You can try to narrow the reason by removing the INJ at all, and if the issue disappears, try to add injections little by little. Another technique is to use FreeMASTER. It enables set a trigger on the sync loss and record selected eTPU variables, including pre-trigger values. The best options would be to use Lauterbach with trace and record all the processor and eTPU behaviour before the sync lost.  In summary: - set injection durations to 100usec - monitor INJ error - remove INJ (- prepare FreeMASTER) Milan Re: MPC5634 eTPU Crank Tooth period log get an err number Thank you for your reply. 1)On the eTPU Engine,I use three functions(etpu_crank,etpu_cam and etpu_inj),and their are the parameters as follow. 2)I marked the signal on the scope .       yellow signal - Fuel injector operating current,As is shown in the picture, there is a loss of signal at ①.       magenta - crank signal.       blue - eTPU crank isr flag.This flag flips when the entry eTPU crank isr.       green - when crank_states.eng_pos_state" is not "FS_ETPU_ENG_POS_FULL_SYNC",it become high.     3)Yes ,of course.Is the information I provided above about the tooth period log inadequate? if so i will do this.But it may take some time. 4)The loss of synchronization happens at different positions and occasionally.Sometimes every few minutes, sometimes every few hours, sometimes every few days. Re: MPC5634 eTPU Crank Tooth period log get an err number Hello Jiandong, could you give me more detailed information? 1) What are all the functions running on the same eTPU engine, their parameters, timing, .... 2) What are the signals on the last scope        yellow signal - ???       magenta - crank       blue - toggle is an interrupt? which interrupt?       green - crank_states.eng_pos_state" is not "FS_ETPU_ENG_POS_FULL_SYNC" 3) If possible, can you make a memory dump of eTPU DATA RAM, starting at Crank cpba, including the tooth period log? 4) Does the loss of synchronization happens always at the same position, at different positions, or just occasionally? Regards, Milan
查看全文
Creating binary with Bootloader and application Hi, I'm developing a booloader for an LPC550X board. The bootloader should at a certain point in the code start the application. This application should be allocated in the flash memory at a fixed address.  I'd like some help to create a binary, which we can flash to the board and which contains both binaries (bootloader and application). Any ideas where to start? Thank you! LPC55xx Re: Creating binary with Bootloader and application Hi Frank, I've tested it and flashed it to the board and it worked nicely. Thank you a lot ! Summary of operations: * [srec_cat] Convert Application binary ->intel hex format with srec_cat * [srec_cat] Convert intel hex Application to hex with offset  * [objcopy] Create bootloader elf-> bootloader hex file * [srec_cat] Merge hex files (Application hex file with offset + bootloader hex file) * [srec_cat] Create final binary from merged intel hex file Re: Creating binary with Bootloader and application hi Frank, thank you a lot for the info. I'll try it next week and let you know what we find out and whether it worked. Have a nice WE. Re: Creating binary with Bootloader and application Yes, objcopy would work, too. As a starter, here a link to a tutorial regarding this topic. https://mcuoneclipse.com/2017/03/29/mcuxpresso-ide-s-record-intel-hex-and-binary-files/ > I've seen that with objcopy I can teoretically convert ELF to SRC Format but what I don't fully understand is how to tell to the resulting file that the BL should be in a given position in the FLASH and the Application in another position. The S19 (SREC) and Intel HEX format contain both addresses and data. These are basically human-readable text format files, that define both that target address and the data. Since BL and application are in different sectors and thus different addresses, they don't interfere. https://en.wikipedia.org/wiki/SREC_(file_format) Although you might need to restrict yourself with the syntactically possible combinations of SREC/HEX files, because some flashing tools are poorly written in this regard. While allowed by the SREC file format definition, I dealt with flashing tools that expected a fixed input line length, a fixed address size, and only ascending addresses. The mentioned SRecord tool could deal with all this requirements. Re: Creating binary with Bootloader and application hi Frank, thank you for your message. I'm unfortunately not very experienced with this platform. By default I'm creating ELF files after compilation from the console (or AXF from the MCUXpresso IDE). Is the SRC Format compatible with the ARM/Cortex M33 architecture?  I've seen that with objcopy I can teoretically convert ELF to SRC Format but what I don't fully understand is how to tell to the resulting file that the BL should be in a given position in the FLASH and the Application in another position. Re: Creating binary with Bootloader and application Thank you Pavel but what I'm trying to do is to create a binary containing both BL and Application which I can flash N times, not to flash BL and Application directly to the MCU (which is very useful indeed) Re: Creating binary with Bootloader and application I would recommend using SREC/S19 or HEX files instead. Since the BL and the application are in different sectors, both files would be easy to merge. Occasionally I have even done so manually, i.e. copied the data contents of the BL into the SREC file of the application. Of course one need to consider structure and syntax of the S19 file format. My company often used the "srec_cat" tool to join both in a post-build step. This tool is part of the free "SRecord" package, which you will easily find with a search engine. Re: Creating binary with Bootloader and application Hello, my name is Pavel and I will be supporting your case, maybe this tool is what are you looking for, with BLHOST you can send the command to write a certain region of the flash. blhost -p COMxx write-memory 0x0 root.bin (for the bootloader) blhost -p COMxx write-memory 0x6000 root.bin (for the image) the command needs to modify the regions only for example. To use the BLHOST I recommend install the SPSDK. Installation Guide — SPSDK documentation
查看全文