s32k3 secure debug interface? Hi Nxp,     i've set S32K312  LC to OEM_PROD and secure debug is active.  i only got jlink now and have some question : 1. to open the secure debug,  is interface JTAG / SWD both available or ONLY JTAG? 2. is there any scripts for jlink to authurize secure debug?   Re: s32k3 secure debug interface? thanks, use pylink to implement CR auth works. Re: s32k3 secure debug interface? Hi @victory  1. To open secure debugging, are JTAG/SWD or JTAG ONLY interfaces available? Both JTAG and SWD interfaces are available. 2. Is there any script for jlink to enable secure debugging? I am afraid J-Link does not support secure debugging of applications with password authentication or with challenge/response authentication. BR, VaneB

S32k142中的默认启动模式和启动引脚 我正在研究S32k142 MCU。我希望启动模式是从Flash启动。 S32k14x MCU 中的默认启动模式是什么？而且我在引脚排列中没有找到任何启动引脚，启动模式配置是如何完成的？ 谢谢， 杰万

尝试使用 EGL_image_external 进行渲染时出现 GPU 错误 在 iMX.8QuadMax 上运行，我正在尝试部署一个 Gstreamer 管道，该管道解码 HEVC 帧，然后将其传递给“glupload”，这是一个能够生成 EGL_image 支持的 GL 纹理的 Gstreamer 元素。 根据其调试和日志输出，glupload 在从 DMA 缓冲区创建 EGL 图像时似乎设置了正确的参数。 但是，当我尝试在 GLES 中渲染解码后的帧并从 EGL_image 支持的纹理中进行采样时，出现错误： [ 1] ES30: 验证过程中出现一些绘制错误并被跳过 此外，在从纹理中采样的过程中，偶尔会出现 SEGFAULT。调用堆栈是： #0 0x0000fffff5a48e68 在 ?? () 中来自 /usr/lib/libGAL.so #1 0x0000fffff59edcb4 在 gcoSURF_DisableTileStatus () 中来自 /usr/lib/libGAL.so #2 0x0000fffff5a036e8 在 gco3D_SetTarget () 中来自 /usr/lib/libGAL.so 我可以得到一些帮助来找出问题所在吗？ 回复：尝试使用 EGL_image_external 进行渲染时出现 GPU 错误 我解决了这个问题。Gstreamer 插件使用它们自己的 GL 上下文而不是共享我的渲染上下文，因此我获得的纹理 ID 尽管在渲染上下文中是有效的纹理 ID，但实际上并不是相同的对象。因此，尝试将这些纹理采样为 EGLImage 外部支持纹理是错误的。 回复：尝试使用 EGL_image_external 进行渲染时出现 GPU 错误 我真的不认为这是一个内存空间限制。纹理为 200x200 RGBA。我正在播放的视频流中有 3 帧。总共只有 160KB。 我已阅读 Gstreamer 指南。它主要讨论使用 gst-launch 构建管道，但在这里没有帮助。 “验证过程中某些绘制出现错误并被跳过”是什么意思？我如何获得有关实际*错误*的更多详细信息？ 我也尝试了 VIV_DEBUG=-MSG_LEVEL:WARNING，但没有打印任何新内容。

EGL_image_externalでレンダリングしようとするとGPUエラーが発生しました iMX.8QuadMaxで実行し、私は、HEVCフレームをデコードし、それを「glupload」、つまりEGL_imageに裏打ちされたGLテクスチャを生成できるGstreamer要素に渡すGstreamerパイプラインをデプロイしようとしています。 glupload は、デバッグおよびログ出力に基づいて、DMA バッファーから EGL イメージを作成するときに正しいパラメーターを設定しているようです。 ただし、デコードされたフレームを GLES 内でレンダリングしようとすると、EGL_image で裏付けられたテクスチャからサンプリングすると、次のエラーが発生します。 [ 1] ES30:一部の描画取得エラーと検証中にスキップ また、テクスチャからサンプリングするドロー中にSEGFAULTが発生することがあります。呼び出し履歴は次のとおりです。 #0 0x0000fffff5a48e68 で ??()を/usr/lib/libGAL.soから #1 gcoSURF_DisableTileStatus() の 0x0000fffff59edcb4 (/usr/lib/libGAL.so から) #2 gco3D_SetTarget () の 0x0000fffff5a036e8 /usr/lib/libGAL.so から 何が問題なのかを理解するのに助けてもらえますか? Re:EGL_image_externalでレンダリングしようとするとGPUエラーが発生します 問題を解決しました。Gstreamerプラグインは、レンダリングコンテキストを共有する代わりに独自のGLコンテキストを使用していたため、レンダリングコンテキストで有効なテクスチャIDであるにもかかわらず、取得していたテクスチャIDは実際には同じオブジェクトではありませんでした。したがって、これらのテクスチャを EGLImage の外部バッキング テクスチャとしてサンプリングしようとすると、エラーが発生しました。 Re:EGL_image_externalでレンダリングしようとするとGPUエラーが発生します メモリスペースの制限だとは思いません。テクスチャは200x200 RGBAです。再生中のビデオストリームには3つのフレームがあります。これは合計でわずか 160KB です。 Gstreamerのガイドを読みました。主に gst-launch を使用したパイプラインの構築について説明しており、ここでは役に立ちません。 「一部の抽選でエラーが発生し、検証中にスキップされました」とはどういう意味ですか?実際の*エラー*の詳細を取得するにはどうすればよいですか? 私もVIV_DEBUG=-MSG_LEVEL:WARNINGを試しましたが、新しいものは何も印刷されませんでした。

S32 Design tool Launching issue Hello Community, As I am start to work with NXP s32 design studio IDE for my Client project, I have installed s32 IDE after installation I trying to open the IDE,but facing the issue. Kindly help me on this Please find the attachment.  Re: S32 Design tool Launching issue Hi @KarthickArumin  The issue you are encountering seems to be related to an installation problem. To help diagnose this, it would be useful to review the installation logs from both the base tool and any associated packages. You can find the installation logs in the following directories: - C:\NXP\S32DS.3.6.0\_S32 Design Studio for S32 Platform 3.6.0_installation\Logs\S32_Design_Studio_for_S32_Platform_3.6.0_Install_MM_DD_YYYY (date)_HH_MM_SS(time).log - C:\Users\workspaceS32DS.3.6\.metadata\.log If you prefer, you can also try reinstalling S32 Design Studio to resolve the issue. BR, VaneB

CAN1 using in iMXRT1170 EVKB Hello,  I'm using the " iMXRT1176DVMAA" microcontroller - iMXRT1170 EVKB to implement the CAN Bus functionality. I used CAN3 and it worked fine, there were two jumpers to remove  ( j102 & j103 ) and now I don't know if there are any jumpers or resistors to remove before using CAN1. Any help ?  Thank you. Re: CAN1 using in iMXRT1170 EVKB Hi @D_D97 , Thank you for your interest in the NXP MIMXRT product, I would  like to provide service for you. I did a test, I connect MIMXRT1170-EVKB board CAN1(J83) and MIMXRT1050-EVKB board  CAN2(J11),  CAN communication works normally. So I think you can refer to what I do. For hardware modification, you need to mount   R2057 and R2058.   For software, you need set CAN1 pins.  You also need modify some code based on CAN1.   Wish it helps you. If you still have question about it, please kindly let me know. Wish you a nice day! BR MayLiu Re: CAN1 using in iMXRT1170 EVKB Hi @mayliu1  I am using an  MIMXRT1170-EVKB board I have previously established CAN3 communication on the board using the Example codes available in the SDK. Now I wanted to establish CAN1 communication on the same board and I came across your solution. Could you please share the photo for the hardware modification that you have mentioned as I am unable to locate the R2057 and R2058..  It would be great if you can share the example code as well. 

GPU error attempting to render with EGL_image_external Running on an iMX.8QuadMax, I am trying to deploy a Gstreamer pipeline that decodes HEVC frames that are then passed to "glupload", a Gstreamer element capable of producing EGL_image-backed GL textures. glupload appears to be setting the correct parameters when creating the EGL image from the DMA buffer, based on its debug and logging output. However, when I attempt to render the decoded frame inside GLES, sampling from the EGL_image-backed texture, I get the error: [ 1] ES30: some draw get error and skipped during validation Also, it will occasionally SEGFAULT during the draw which samples from the texture. The call stack is: #0 0x0000fffff5a48e68 in ?? () from /usr/lib/libGAL.so #1 0x0000fffff59edcb4 in gcoSURF_DisableTileStatus () from /usr/lib/libGAL.so #2 0x0000fffff5a036e8 in gco3D_SetTarget () from /usr/lib/libGAL.so Can I get some help figuring out what is wrong? Re: GPU error attempting to render with EGL_image_external I solved the issue. The Gstreamer plugins were using their own GL context instead of sharing my render context, so the texture IDs I was getting, despite being valid texture IDs in the render context, were not actually the same objects. Hence, attempting to sample those textures as EGLImage external backed textures was an error.  Re: GPU error attempting to render with EGL_image_external I really don't think it's a memory space limitation. The texture is 200x200 RGBA. The video stream I'm playing back has 3 frames in it. That is only 160KB total. I've read the Gstreamer guide. It mostly talks about constructing pipelines with gst-launch and isn't helpful here. What does "some draw get error and skipped during validation" mean? How do I get more details on the actual *error*? I also tried VIV_DEBUG=-MSG_LEVEL:WARNING and that didn't print anything new. Re: GPU error attempting to render with EGL_image_external Hello, For supported formats one can refer to the Release Notes, and the graphics user guide. pay attention to Table 15. i.MX GStreamer 1.0 plugins. Also if you are receiving segmentation fault is due to your don't have enough memory to run the graphics check this part. Regards

S32G399A - MDIO configuration in the Device Tree Dear NXP fellows, I am using BSP41.0 and a board based on S32G399ARDB3. Looking at the Linux Kernel Device Tree Configuration file, I see this PFE MDIO2 definition: &pfe_mdio2 { /* AR8035 */ pfe_mdio_b_phy4: ethernet-phy@4 { reg = <4>; }; /* SJA1110's phys: 0x09-0x0e */ }; Then I see this PFE_MAC2 interface definition: &pfe_netif2 { phy-mode = "rgmii-id"; phy-handle = <&pfe_mdio_b_phy4>; }; It uses as PHY handle the pfe_mdio_b_phy4 declared above. What concerns me are the comments. According to the User Guide we have this configuration as default: In this configuration, the PFE_MAC2 interface is connected through RGMII to the PHY Micrel KSZ9031. The PHY Atheros AR8035 is connected through RGMII to the ports 2 and 3 of the SJA1110 switch. The switch is accessed by default through SGMII in its port 4 by PFE_MAC0. So what is the relation between PFE MDIO2 and the SJA1110? Why is the SJA1110 PHY MDIOs in PFE_MAC2 interface if the PFE_MAC2 is not even connected to the switch? Thank you very much for the support, Best regards Guilherme Re: S32G399A - MDIO configuration in the Device Tree Hello @alejandro_e , Thank you for your reply. Yes, this certainly worth a try. Best regards, Guilherme Re: S32G399A - MDIO configuration in the Device Tree Hello @GuilhermeS32G3 , I have received the following answer from the internal team: " Yes, if ethernet-switch@1 is enable ,then the PHYs driver of Port 2 &3, and 6 * 100BaseT Ports of SJA1110 will be loaded when Linux kernel boots and The ports could be viewed with command "ifconfig -a" " Let me know if this information solves your questions. Re: S32G399A - MDIO configuration in the Device Tree Hello @alejandro_e , Thank you very much for your reply, Yes, I think it answers my question, and it complements Pavel's reply in my other question. In the default case (AR8035 connected to the SJA1110) there is no need to configure the AR8035 PHY in the Linux Kernel Device Tree, as this is responsibility of the SJA1110 firmware. As we are discussing this, another question arises. Still in the s32gxxxa-rdb.dtsi file, line 761, it defines the spi5 configuration. Within spi5, there are 3 nodes relative to SJA1110: sja1110-uc@0  (line 772), sja1110-sw@1 (line 780), and ethernet-switch@1  (line 795).  The former two are the SPI interfaces for reading the SJA1110 microcontroller firmware and switch configuration. But the latter one, ethernet-switch@1,  is an alternative, that requires the other two to be disabled before enabling it. I would like to know in which cases ethernet-switch@1 is used? If I enable this node, can I configure the PHYs connected to Ports 2 and 3 in the same way as the PHY connected to pfe_netif2? Best regards, Guilherme Re: S32G399A - MDIO configuration in the Device Tree hello @GuilhermeS32G3 , I have received an answer from the internal team: " There are two MDIO interfaces in SJA1110, the one is SMI_OUT_MDC and SMI_OUT_MDIO, the SMI_OUT interface is intended to be used to configure external PHY devices from the SJA1110 internal M7 core. The other is SMI_AP_MDC and SMI_AP_MDIO, The SMI access point (SMI-AP) interface allows S32G to access SJA1110 internal 100BASE-T1 PHYs. From the schematics of SJA1110 part in S32G-RDB3 board, the SMI_OUT_MDC and SMI_OUT_MDIO connected to 2 external PHYs  AR8035, and PFE_MDIO2 connected to SMI-AP of SJA1110, so that S32G could access the internal SJA1110 100BASE-T1 PHYs (address from 0x09~0x0e): Notes: the phy address in the node pfe_mdio2 of device tree is really for pfe2 PHY KSZ9031. " Let me know if this answers your question Re: S32G399A - MDIO configuration in the Device Tree Hello @GuilhermeS32G3, I will try to reach the internal team in charge of the component and come back to you. I appreciate your patience. Best regards

Default boot mode and Boot pins in S32k142 I am working on S32k142 MCU. I want the boot mode to be from Flash. What is the default Boot Mode in S32k14x MCUs and also i did not found any Boot pins in the Pinout, How is the Boot mode configuration done? thanks, jeevan Re: Default boot mode and Boot pins in S32k142 Hi @Jeevansagar  S32K1xx devices have only one boot mode - from internal flash from address 0 (0x0 initial SP_main and 0x4 initial PC). There are no other options, so there are no boot pins. Regards, Lukas    

DMA For ADC I am using DMA to transfer data from FIFO1 and FIFO2 into a buffer. I am utilizing fixed DMA configurations for this data transfer. when completion of the transfer, the following functions will be called: Bctu_Ip_Bctu0Fifo1DmaComplete Bctu_Ip_Bctu0Fifo2DmaComplete              The system functions correctly when I use an interrupt from RTD (IntCtrl_Ip_Init). However, for my project, I am using a different file to configure the interrupt handler, set priority, and enable the handler. For DMA0_CH1 &DMA0_CH16,i am using IRQ :  DMATCD1_IRQn / Dma0_Ch1_IRQHandler / Priority DMATCD16_IRQn / Dma0_Ch16_IRQHandler / Priority It works for BCTU_IRQn and PIT0_IRQn. It also works with DMA when it is triggered by PIT using the following configurations:   However, it does not show any indication if the transfer has begun or not, and it is not raising an interrupt when the transfer is completed for DMA while reading data from FIFO using the fixed RTD configuration setup for DMA transfer (Bctu_FifoSetupDma).        What additional configurations are needed to get the system working?   Re: DMA For ADC Hi, I do not expect issue with clock gating. You can check DMA TCD dest address if is has desired value. 1-2) No, it is always enabled 3) if Dcache is enabled and buffer not placed in non cacheable area, then you should use it flush/invalidate cache if needed 4) depend on application, if peripheral is used/accessed must not be clock gated.  BR, Petr Re: DMA For ADC Hi@PetrS Thanks for the information. Here is the list of clocks enabled in my project: TRGMUX BCTU 0 eMIOS 0 eMIOS 1 eMIOS 2 ADC 0 ADC 1 ADC 2 PIT 0 PUPD MC_ME_CTL_KEY_KEY(0x5AF0) MC_ME_CTL_KEY_KEY(0xA50F) eDMA - Control & Status eDMA - Transfer Control Descriptor 0 to 31 DMA Channel Multiplexer 0 DMA Channel Multiplexer 1 MSCM STM0 SIUL2 CMU 0-6 PLL FlexCAN 0 to 3 LPI2C 0 to 1 LPSPI 0 to 3 CRC PCUD 1 )Does XRDC need clock enabling? If yes, can you provide the information on how to enable it? 2) Does Crossbar need clock enabling? If yes, can you provide the information on how to enable it? 3)Do i need to Adde Cache_Ip driver into the project ? 4)Are there any other clocks that need to be enabled? Re: DMA For ADC Hi, error may happen in case destination address points to memory range that is inaccessible - it means either access to reserved memory space or to disabled or un-clocked peripheral or protected by any kind of protection leading in bus error (MPU, XRDC). BR, Petr Re: DMA For ADC Hi@PetrS I have tested the system and identified Destination Bus Errors on channels 1 and 16.” Do you have any idea about the cause of this ? Re: DMA For ADC Hi, not sure of the code you execute, probably just IntCtrl_Ip_InstallHandler and IntCtrl_Ip_EnableIrq. But the same is done in IntCtrl_Ip_Init as well. Try to check/compare in debugger NVIC content and assigned handler in vector table for both ways. BR, Petr

S32k142のデフォルトのブートモードとブートピン S32k142 MCUに取り組んでいます。ブートモードを Flashからにしたいです。 S32k14x MCUの デフォルトのブートモード とは何ですか、またピン配置に ブートピン が見つかりませんでしたが、ブートモードの設定はどのように行われますか? 感謝 ジーバン

could you share the link to get rtos code for LS1017/LS1028 Hi,  Our hareware engineer is designing the develop board with LS1017. Could you share me rtos code or uboot code to bring up the develop board?  Re: could you share the link to get rtos code for LS1017/LS1028 Hello,  You can use as reference the LLDPUG to bring up your board, please find the link of the document below: https://www.nxp.com/docs/en/user-guide/UG10081_LLDP_6.1.55_2.2.0.pdf 

PCA9555 - 20kHz PWM signal for driving low side MOSFET Hello, I am looking for a I2C/SPI interfaced PWM expander IC to to generate 20kHz PWM signal (30% duty cycle to 100% duty cycle) to multiple low side MOSFETs to drive solenoid valve. It seem PCA can generate  up to 97 kHz PWM signal with a duty cycle that is adjustable from 0 % to 99.6 %. I see to achieve 100% duty cycle is a concern. Is it possible to use PCA9635 chip as a PWM expander to drive multiple low-side MOSFET.  We need automotive qualified component. If this IC doesn't work, do you have other solution to generate multiple 20kHz PWM signal using I2C or SPI interface.  Thank you Re: PCA9555 - 20kHz PWM signal for driving low side MOSFET Hi Labib, yes, it should work. There is an example in the PCA9685 datasheet, in the page 29. using external MOSFET to drive LEDs, with required bit settings. I guess you can also use it to drive solenoid.  With Best Regards, Jozef   Re: PCA9555 - 20kHz PWM signal for driving low side MOSFET We wan to drive solenoid like this, it it possible to drive like this   Re: PCA9555 - 20kHz PWM signal for driving low side MOSFET Hi Jozef, Thank you very much for your prompt response.  It seems MC33816, PT2001, and PT2000 would be over kill for our application. I really like PCA9635 and PCA9745B. Can I drive LS MOSFET a attached herewith? I am concerned about whether all LED channels are sinking pins.      Re: PCA9555 - 20kHz PWM signal for driving low side MOSFET Hello Labib, we have programmable controllers for solenoid control applications, with adjustable frequency and adjustable duty cycle up to 100%. They are MC33816, PT2000 and PT2001.  The MC33816, PT2001, and PT2000 are all designed for automotive applications, particularly for engine and powertrain control, but they have differences in functionality and performance that can guide your choice based on your specific needs for controlling a direct injection diesel engine. 1. MC33816 Type: Programmable Solenoid Controller Application: Designed for engine control, such as driving injectors in gasoline and diesel direct injection engines. Features: Capable of driving both peak-and-hold current for fuel injectors, allowing control of injection timing and quantity. Offers dual injector drivers and is programmable for adaptive fuel control. Integrated diagnostics, including under-voltage, over-temperature, and short-circuit protection. Has built-in digital signal processing for precise control. Supports custom engine control algorithms. Flexibility: The MC33816 is more versatile and programmable, making it suitable if you need highly adaptive control, advanced diagnostics, and customization.   2. PT2001 Type: Injector Driver IC Application: Primarily for fuel injectors in internal combustion engines. Features: Designed to drive solenoids with peak-and-hold currents, typically for gasoline or diesel injection systems. Provides both the injector current profile and diagnostics. It integrates an advanced level of protection (over-current, short-to-ground, short-to-battery). Offers precise current control and supports external microcontroller interfacing. Targeted Design: The PT2001 is aimed at applications that require robust injector driving with safety mechanisms, but it is less flexible than MC33816 in terms of programmability.   3. PT2000 Type: Solenoid Driver IC Application: General-purpose solenoid driver, often used in automotive engine management for fuel injectors and transmission control. Features: Provides peak-and-hold control for solenoid driving applications. More basic compared to the PT2001 and MC33816, with fewer programmable options. Ideal for straightforward applications without the need for advanced customization. Includes basic protection features like over-temperature and over-voltage protection. Simplicity: PT2000 is suited for simpler injector control tasks where extensive programmability or advanced diagnostics are not required. How to Choose: MC33816: Choose this if your application demands high precision, customization, or advanced engine control strategies. It’s ideal for future-proofing designs where adaptability is crucial. PT2001: This is suitable if you need a robust, reliable injector driver with good protection and diagnostics but don’t need as much flexibility or programmability as the MC33816 offers. PT2000: Opt for the PT2000 if you are working on simpler applications where the focus is on cost-effectiveness and basic injector control, without the need for advanced customization or features. The PCA9635 you mentioned comes from LED drivers portfolio. Most of them have the duty cycle adjustable maximally to 99.6%.  For the LED drivers with PWM output and duty cycle up to 100% We have PCA9745B. PWM frequency fixed to 31.25kHz. PCA9685. PWM frequency adjustable from 24Hz to 1526Hz.  With Best Regards, Jozef

S32K344 RMII Problem with GMAC driver Hello, I am working with the S32K344 MCU and using the LAN8710A Ethernet PHY in RMII mode. My goal is to transmit data from the MCU to a PC, but I am facing issues in the process. Setup and Observations: I can access the LAN8710A registers via MDIO. I have verified that the STRAP pins are correctly set for RMII mode. The GMac_IP_Internal_Loopback example code runs successfully. When I disable MAC_CONFIG_LOOPBACK in the EthCtrlConfigMac section of the GMac driver configuration and attempt to send data to the PC, I receive nothing. When I enable Far Loopback mode on the LAN8710A, it correctly echoes back the data sent from the PC. Initially, after disabling internal loopback, I observed corrupted data on the PC. Later, I found that the EMAC_MII_RMII_TX_CLK pin was floating and was not connected to a 50 MHz clock signal. Even with the floating TX_CLK, I was able to receive corrupted data. However, after properly connecting the TX_CLK to 50 MHz, I can no longer receive any data at all. One unusual observation: When TX_CLK was not connected, I could still receive some form of data, though it was corrupted. For example, if I sent a packet filled with 0xFF, I would receive only 0xFF values. If I sent a packet filled with 0xF0, I received a mix of 0x30 and other byte values. Questions: What could be causing the transmission failure after properly connecting the 50 MHz TX_CLK? Is there any additional configuration required in the GMAC driver to enable external transmission? Are there any known issues or errata related to S32K344 + LAN8710A RMII mode that could explain this behavior? How was I able to receive any data at all when TX_CLK was not connected? Even though it was corrupted, it seemed to maintain a pattern related to the original data. What could be the explanation for this behavior? Any insights or suggestions would be greatly appreciated. Thank you! Re: S32K344 RMII Problem with GMAC driver Hi Julián, Thank you for your response. I wanted to share my findings in case anyone else encounters a similar issue. After further debugging, I was able to resolve the problem by making two key modifications: Before calling Siul2_Port_Ip_Init, I applied the following configuration: IP_DCM_GPR->DCMRWF1 = (IP_DCM_GPR->DCMRWF1 & ~DCM_GPR_DCMRWF1_EMAC_CONF_SEL_MASK) | DCM_GPR_DCMRWF1_EMAC_CONF_SEL(2U); In the clock configuration, I set the dividers for EMAC_TX_CLK and EMAC_RX_CLK to 2, reducing their frequencies to 25 MHz. After applying these changes, data transmission started working correctly. For reference, the corrupted data issue observed when TX_CLK was not connected remains an interesting behavior, but after properly setting up the reference clocks and configuration registers, the system now operates as expected. I hope this helps others who might face similar issues. Best regards, Mehmet Fatih Re: S32K344 RMII Problem with GMAC driver Hi @MehmetFatih, Since the LAN8710A is a third-party device, support is limited, because of this, there is no S32K344 + LAN8710A erratas or documentation. I'm not sure what the corrupted data may indicate, since transmission was made without a clock, but are you able to analyze the signal with an oscilloscope or logic analyzer to see if the frame is being sent/received correctly after connecting the 50Mhz? in order to configure transmission and reception, you must also configure the interrupt driver, please refer to this community post: Solved: GMAC of S32K344 Callbackfun - NXP Community. Could you also share the connection for the reference clock? Best regards, Julián

仅通过 I²C 引脚排列使用 PN7160。 对于我们的产品，我们只有 2 个可用引脚可用于 PN7160 NFC 板。一个SDA和一个SCL。作为概念证明，我尝试使用仅通过 I²C（以及电源）连接的评估套件运行轮询示例（nfcDemoApp poll）。有可能这样做吗？到目前为止，我已经测试过使用和不使用接口板的情况，但均未成功。我只需要证明我不需要中断引脚，据我所知，轮询时我不需要它。非常感谢您的建议！ 此外，入门指南并非 100% 正确，示例在安装了 Bookworm 的 Raspberry Pi 5 上不起作用。 接触式智能卡读卡器芯片 回复：仅通过 I²C 引脚排列使用 PN7160。 你好@Jansch ，祝你有个愉快的一天！ 请考虑我们的建议是遵循参考文档中描述的处理这些引脚的指南，因为采用任何其他处理方式我们都无法确保设备的正常功能。 但是，如果您不需要为 PN7160 的 EEPROM 下载升级，您可以考虑不处理 DWL_REQ 引脚而只是将其连接到 GND，因为该引脚仅在进行此类升级时使用。请参阅PN7160/PN7161 数据表的第 11.5.4 节。 另一方面，建议对 VEN 复位引脚进行动态处理，因为在可能的上电序列中，它需要保持低电平至少 10 μs，然后才能拉高并启动启动过程，以使主机通信成为可能（参见同一文档中的表 36）。 请确保您进行的任何测试都是基于我们提供的文档进行的。您可以参考上面提到的部分和图 20 至 25来更深入地了解可能的上电序列。 谨致问候， 丹尼尔。 回复：仅通过 I²C 引脚排列使用 PN7160。 你好@Jansch ，祝你有个愉快的一天！ 非常感谢您对我们的产品感兴趣。 值得一提的是， PN7160 评估套件快速入门指南中描述的一些软件设置步骤仅适用于 OM27160A1HN 版本的电路板，其中一些适用于 OM27160B1HN 版本。请确保您使用的是OM27160A1EVK板，因为这是嵌入 PN7160 的 I²C 变体的板。 我想问一下您是否可以提供有关您正在使用的电源引脚名称的更多详细信息，以及 GND 引脚是否已连接？ 请记住，在所有情况下都应处理 VEN 复位引脚，以使主机通信成为可能。还要考虑到，诸如 DWL_REQ 之类的引脚（它提供了固件升级的可能性）和 IRQ 同样重要，以确保 PN7160 和主机之间的数据流控制。 请参阅PN7160/PN7161 数据表的第 11.5 节，以更深入地了解如何处理这些引脚以确保系统的整体健康。 谨致问候， 丹尼尔。

PN7160はI²Cピン配置でのみ使用します。 私たちの製品では、PN7160 NFCボードに使用できる2つの空きピンしかありません。1 つの SDA と 1 つの SCL。概念実証として、I²C(および電源)を介してのみ接続されたevalキットを使用して、ポーリングの例(nfcDemoAppポーリング)を実行しようとしています。その可能性はありますか?私はこれまでにインターフェースボードの有無にかかわらずテストしましたが、成功しませんでした。私の知識では、ポーリング時に必要ないはずの割り込みピンが不要であることを証明する必要があります。アドバイスをいただければ幸いです! さらに、スターターガイドは100%正しいわけではなく、この例はBookwormがインストールされているRaspberry Pi 5では動作しません。 接触型スマートカードリーダーIC Re:PN7160をI²Cピン配置でのみ使用します。 こんにちは @Jansch、こんにちは! 他の取り扱い方法ではデバイスの適切な機能を確保できないため、参照されたドキュメントに記載されているピンの取り扱いに関するガイドラインに従うことをお勧めします。 ただし、PN7160 の EEPROM のアップグレードをダウンロードする必要がない場合は、DWL_REQ ピンを扱わずに GND に接続することを検討できます。これは、このピンがアップグレードが行われる場合にのみ使用されるためです。PN7160 / PN7161データシートのセクション11.5.4を参照してください。 一方、可能な電源投入シーケンスでは、ホスト通信を可能にするためにプルアップしてブートプロセスを開始する前に、少なくとも10μsの間LOWにする必要があるため、VENリセットピンの動的処理が推奨されます(同じドキュメントの表36を参照)。 テストを行う場合は、提供されたドキュメントに基づいて行うようにしてください。上記のセクションと 図20から図25 を参照して、可能な電源投入シーケンスについてより深く理解することができます。 よろしくお願いします。 ダニエル書。 Re:PN7160をI²Cピン配置でのみ使用します。 こんにちは @Jansch、こんにちは! この度は、弊社製品にご興味をお持ちいただき、誠にありがとうございます。 PN7160評価キットのクイックスタートガイドに記載されているソフトウェアセットアップの手順の一部は、ボードのOM27160A1HNバージョンでのみ実行することを意図しており、一部はOM27160B1HNバージョンを対象としていることに言及することが重要です。PN7160のI²Cバリアントを埋め込むボードである OM27160A1EVK ボードを使用していることを確認してください。 使用している電源ピンの名前と、GNDピンが接続されているかどうかについて詳しく教えていただければ幸いです。 すべての場合において、ホスト通信を可能にするためにVENリセットピンを処理する必要があることに注意してください。また、ファームウェアのアップグレードを可能にするDWL_REQやIRQなどのピンは、PN7160とホスト間のデータフロー制御を確保するために同様に重要であることも考慮してください。 PN7160/PN7161データシートのセクション11.5を参照して、システムの全体的な健康状態のためにこれらのピンをどのように処理するかについて理解を深めてください。 よろしくお願いします。 ダニエル書。

Using PN7160 only through I²C pinout. For our product we only have 2 free pins we could use for the PN7160 NFC board. One SDA and one SCL. As a proof of concept I am trying to run the polling example (nfcDemoApp poll) with the eval kit only connected through I²C (aswell as power). Is there a possibility to do so? I have so far tested it with and without the interface board without success. I just need to proof that I don't need the Interrupt pin, which in my knowledge I shouldn't need when polling. Advice would be greatly appreciated! Also furthermore the starter guide is not 100% correct, the example doesn't work on Raspberry Pi 5 with Bookworm installed. Contact Smart Card Reader ICs Re: Using PN7160 only through I²C pinout. Hello @Jansch, Good Day! Please consider that our recommendation is to follow the guidelines for the handling of those pins described in the referred document, given that with any other way of handling we cannot ensure a proper functionality of the device. However, if you do not require to download upgrades for the EEPROM of the PN7160, you could consider not handling the DWL_REQ pin and just have it connected to GND, given that this pin is only used when such an upgrade will take place. Please refer to section 11.5.4 of the PN7160/PN7161 Data Sheet. On the other hand, dynamic handling of the VEN reset pin is recommended, since in possible power-up sequences, it needs to be LOW for at least 10 μs before pulling up and starting the boot process to make host communication possible (see Table 36 in the same document). Please make sure that any test you make, you do it based on the documentation we have provided. You may refer to the sections mentioned above and Figures 20 to 25 to get a deeper understanding of the possible power-up sequences. My best regards, Daniel. Re: Using PN7160 only through I²C pinout. Hey Daniel, I was curious, do I have to set the pin actively to different states, or could I just put a set pullUp onto it? Re: Using PN7160 only through I²C pinout. Hello Daniel, I am asking because we have a size constraint board and nfc is an optional requirement, therefore we are trying to get it to work on our board without it being absolutely necessary. The only way we could make this happen is, if we could use the PN7160 through I²C pins alone, meaning: 1) GND 2) Power 3) SDA 4) SCL You mentioned I need to have the VEN pin connected. Therefore we sadly won't be able to work with NFC here.  I do own the correct board. Through further research it seems like the Pi5 problem is a common one, and not yet fixed on NXP side. I found multiple posts in this forum suggesting so. Either way I hope you have a great day! Re: Using PN7160 only through I²C pinout. Hello @Jansch, Good Day! Thank you very much for your interest in our products. It is important to mention that some of the steps for software setup described in PN7160 evaluation kit quick start guide are meant to be executed only on the OM27160A1HN version of the board and some of them are meant for the OM27160B1HN version. Please make sure you are working with the OM27160A1EVK board, as this is the one that embeds the I²C variant of the PN7160. I would like to ask if you could please provide more details about the names of the power pins that you are using, as well as if the GND pin is being connected?  Keep in mind that in all cases the VEN reset pin, should be handled in order to make host communication possible. Also consider that pins such as DWL_REQ, which provides the possibility for firmware upgrades, and IRQ are equally as important in order to ensure data flow control between PN7160 and the host. Please refer to section 11.5 of the PN7160/PN7161 Data Sheet to get a deeper understanding on how to handle those pins for the overall wellbeing of the system. My best regards, Daniel.

How to make MC33774 send wakeup signal on TPL to wakeup MC33665 Hi  I want to make MC33774 to send wakeup signal to MC33665 through TPL when there is overvoltage happened. I set MC33774 to cyclic mode and it will wakeup and measure the voltage every 10 seconds. If the voltage is over 3.5V there will be a overvoltage event happened and I want MC33774 to wakeup MC33665 through the TPL communication. I found a register related to this function and I wrote it according to the user manual but it cannot work. Is there any other register need to be configured? Below picture is the register I configured I wrote it to 1 to enable TPLWAKEUP, Is it correct? The picture below is the VAUX voltage which MC33774 wakeup every 10 seconds  Re: How to make MC33774 send wakeup signal on TPL to wakeup MC33665 Thanks @tianxing  so much for your reply. Re: How to make MC33774 send wakeup signal on TPL to wakeup MC33665 Hi HusseinMoanes:      Because the TPL wakeup message will just be sent once so I missed it when I checked the message. At last I use the Oscilloscope with trigger mode and then caught the wakeup message on TPL.     In sumerize to make the TPL wakeup work we have to configure the registers as below:  1. enable TPLWAKEUP 2. write registers  FEH_WAKEUP_CFG0  and set VCOV(register PRMM_VC_OV_TH_CFG and write PRMM_VC_OV_UV_CFG0) 3. write the registers TARGETMODE (Sleep mode)and  SYS_CYC_WAKEUP_CFG cyclic timer  PERIOD value   Re: How to make MC33774 send wakeup signal on TPL to wakeup MC33665 @tianxing Kindly can you please explain how it worked fine with you as I have the same issue now. Re: How to make MC33774 send wakeup signal on TPL to wakeup MC33665 It is ok now Thank you Re: How to make MC33774 send wakeup signal on TPL to wakeup MC33665 Hi Xing, please refer to the section 7.1.1.1 in the MC33774A full datasheet. Please check if the MC33774A is in Sleep mode or in Deep Sleep mode. Deep Sleep mode is entered automatically after a power-on reset. The device remains in Deep Sleep mode until it detects bus activity. Other wake-up sources are disabled.  You can check if the MC33774A was in Sleep or in Deep Sleep mode by checking the PREVMODE bits in the SYS_MODE register, address 4h. Please refer to the Table 65. in the MC33774A full datasheet.  With Best Regards, Jozef

NTAG213の事前定義されたパスワードでタグを認証する際の問題 みなさん、こんにちは。私はワン・アマール 上記のトピックを参照すると、PWD_AUTHコマンドを使用してNTAG213であるタグを認証できません。 ビルドされたプログラムのフロー: 1. プログラムはタグにファイルを送信します 2. 次に、プログラムはブロック 2 のタグにパスワードを設定します 3.プログラムは、送信されたファイルを元のファイルと比較して検証します タグを確認するために、プログラムはパスワードを取得する必要がありました。 プログラムを実行するときに、送信および保存するためのパスワードを記録しましたが、パスワードは異なります。 保存されたパスワードブロック2:00050000 送信されるパスワード:31323334 誰かが私にこれを説明できますか? Re:NTAG213の事前定義されたパスワードでタグを認証する際の問題 こんにちは、ワン・アンマール!NTAG213タグのパスワード認証に問題があるようです。一緒にこれを理解してみましょう。 あなたの説明から、保存されたパスワードと認証プロセス中に送信されるパスワードとの間に不一致があるようです。確認すべき点は次のとおりです。 パスワードの形式: パスワードが正しくフォーマットされ、タグに保存されていることを確認します。パスワードは 16 進数形式である必要があります。たとえば、パスワード31323334は 0x31323334 として保存する必要があります。 コマンド シーケンス: パスワードの設定と認証の実行のコマンド シーケンスが正しいことを確認します。パスワードの設定と認証の一般的な手順を次に示します。 パスワードの設定:FF D6 00 2B 04 31 32 33 34 セットパック:FF D6 00 2C 04 00 00 00 00 AUTH0をアクティブにします:FF D6 00 29 04 04 00 00 00 認証: FF 00 00 1B 31 32 33 34 メモリブロック:パスワードが正しいメモリブロック(この場合はブロック2)に保存されていることを確認します。 コマンド構造: コマンド構造を再確認し、正しい APDU コマンドが送信されていることを確認します。PWD_AUTHコマンドは次のようになります。 PWD_AUTHコマンド:FF 00 00 1B 31 32 33 34 リーダーの互換性: リーダーがNTAG213と互換性があり、PWD_AUTHコマンドをサポートしていることを確認してください。

Issue while authenticate tag with predefined password for NTAG213 Hello all. I am Wan Ammar Referring to the above topic, I cannot authenticate the tag which is the NTAG213 using the PWD_AUTH command.  The flow of the program that has been built: 1. the program send a file to the tag  2. the program then set a password to the tag in Block 2 3. the program verifies the sent file comparing it with the original file In order to verify the tag, the program got to have the password. When running the program, I have logged the password for being sent and stored, and it is different: Stored password Block 2: 00050000 Password being sent:31323334 can someone explain this to me? Re: Issue while authenticate tag with predefined password for NTAG213 Hi Wan Ammar! It sounds like you're having an issue with the password authentication for your NTAG213 tag. Let's try to figure this out together. From your description, it seems there's a discrepancy between the stored password and the password being sent during the authentication process. Here are a few things to check: Password Format: Ensure that the password is correctly formatted and stored in the tag. The password should be in hexadecimal format. For example, the password 31323334 should be stored as 0x31323334. Command Sequence: Verify that the command sequence for setting the password and performing the authentication is correct. Here's a typical sequence for setting the password and authenticating: Set Password: FF D6 00 2B 04 31 32 33 34 Set PACK: FF D6 00 2C 04 00 00 00 00 Activate AUTH0: FF D6 00 29 04 04 00 00 00 Authenticate: FF 00 00 1B 31 32 33 34 Memory Block: Ensure that the password is stored in the correct memory block (Block 2 in your case). Command Structure: Double-check the command structure and ensure that the correct APDU commands are being sent. The PWD_AUTH command should look like this: PWD_AUTH Command: FF 00 00 1B 31 32 33 34 Reader Compatibility: Make sure that your reader is compatible with the NTAG213 and that it supports the PWD_AUTH command.