MC33SB0400ESR2とFS32K142HFT0VLHTのウェーハは何nmですか? MC33SB0400ESR2とFS32K142HFT0VLHTのウェーハは何nmですか? Re:MC33SB0400ESR2とFS32K142HFT0VLHTのウェーハは何nmですか? Hi@ニハオロボット S32K1のプロセスは90nmで、MC33SB0400ESR2は250nmです。

TJA1043 - ノーマルモード - バス診断のみに使用 皆さん、こんにちは。 CANバスに問題があるかどうかを検出したいです。最初は、聞くだけのモードでできると思っていました。データシートから理解しているように、バス診断機能はノーマルモードのときのみアクティブになります。その場合、TXDピンに何をする必要がありますか?グランドに接続する必要がありますか、それとも他のものに接続する必要がありますか?TJA 1043 を使用してバスの障害のみを検出できますか?マイコンは使いません。ERRNピンを使用したLEDにエラーがあるかどうかを表示したいです。 事前に感謝いたします。 Re:TJA1043 - ノーマルモード - バス診断のみに使用 トーマスさん、お返事ありがとうございます。 現在の定格については留意してください。TXD ピンはどうですか?GNDや5Vなど、バスに干渉しないように何かに接続する必要がありますか? Sam

S32G RDB2 多核启动在 bsp41 中挂起 您好，NXP团队： 我尝试按照 AN13750 官方文档设置具有 A53 和 M7 的多核环境。 我在 bsp41 中发现了一个启动问题，并且我也使用 bsp42 来澄清。 但是BSP42可以成功启动到Linux内核。 BSP41 将始终坚持 引导加载程序 0x2 从 QSPI 加载的应用程序 1 图像片段 0。 引导加载程序 0x2 应用程序 M7_0 已加载。 我将这两个版本的日志添加到附件中。 您能帮忙澄清一下这个问题吗？ 谢谢。 西南： 集成参考示例S32G2202306 EB 27.1 RTD 4.4_4.0.0_P05_HF01 HSE_FW S32G2XX_0_1_0_16 回复：S32G RDB2 多核启动在 bsp41 中挂起 嗨，乔伊， ATF 加载地址在 bsp41/bsp42 中是相同的。 入口点是0x34700000。 谢谢。 艾伦

S32G RDB2 multicore boot hang in bsp41 Hi NXP team, I try to setup a multicores environment with A53 and M7 following AN13750 official document. I found a boot issue in bsp41 and I also use bsp42 to clarify. But BSP42 can bootup to Linux kernel successfully. BSP41 will always hang in bootloader 0x2 Application 1 image fragment 0 loaded from QSPI. bootloader 0x2 Application M7_0 was loaded. I add these two versions log in attachment. Could you please help to clarify this issue? Thanks. SW: Integration_Reference_Examples_S32G2_2023_06 EB 27.1 RTD 4.4_4.0.0_P05_HF01 HSE_FW S32G2XX_0_1_0_16 Re: S32G RDB2 multicore boot hang in bsp41 Hi Joey, Thanks for your help. I will base on BSP42 for development. Allen Re: S32G RDB2 multicore boot hang in bsp41 HI,Allen_Cheng After investigation, this is a known issue as described in ALB-11457, and it has been resolved in Linux BSP42. The root cause lies in the bootloader de-initializes (in SysDal) the peripheral clocks before starting the applications, but s32_io_setup() is called without any prior initialization of the SDHC clocks from ATF. The description is shown in the BSP42 release note: The easiest solution to fix this issue is recommending use BSP>=42. If continue working with BSP41, you can refer to these public commits to modify ATF code. Hope it can help you. BR Joey Re: S32G RDB2 multicore boot hang in bsp41 hi,Allen_Cheng Thank you for your reply. I have reported the problem,and I will reply to you as soon as I have the result. BR Joey Re: S32G RDB2 multicore boot hang in bsp41 Hi Joey, I try to disable secure boot in EB tresos and disable HSE in u-boot. But it looks like the same result. Thanks. Re: S32G RDB2 multicore boot hang in bsp41 hi,Allen_Cheng Sorry for the late reply. You can try Disable Secure Boot, as shown in the image below. In addition, if you are not using mmc patch, make sure you modify the s32_common.mk file. Wish it can help you. BR Joey Re: S32G RDB2 multicore boot hang in bsp41 Hi Joey, All Configuration of the AN13750 are almost the same but I only modified: 1. u-boot : enable HSE and firmware path 2. ATF not apply mmc patch 3. remove m7_1 and m7_2 in bootloader Attach files are bootlader and eb project. Thanks. Allen Re: S32G RDB2 multicore boot hang in bsp41 hi， 1. According to the printed information, BL2 fails to start. There is an initialization conflict between fip.bin of BSP41 and the Bootloader you made, resulting in a start failure. Did you completely follow the configuration of AN13750? If you made some modifications, could you please give me more specific information? Or could you please provide me with your modified Bootloader project? 2.The ATF Load address in BSP41 is the same as that in BSP42. It should be noted that the Size is a little different, but it does not affect the result of starting kernal. When you have other changes to the initialization requirements, you need to modify the Bootloader project and then regenerate blob.bin. BR Joey Re: S32G RDB2 multicore boot hang in bsp41 Hi Joey, I used the blob.bin and BSP42's fip.bin with BSP41's sdcard(official image+BSP41's fip.s32). It can bootup to linux successfully. So the result means the first question BL2 can't start in BSP41 may have certain issue?   Another confusion: If the ATF Load address and others condition are the same in BSP41 and BSP42, the blob.bin need to rebuild again? or they can use the same blob.bin? Thanks! Allen Re: S32G RDB2 multicore boot hang in bsp41 hi,Allen_Cheng I have received your blob.bin and have repeated your problem and will solve it as soon as possible. In addition, I found that BSP41 can be started using your blob.bin and BSP42's fip.bin, you can try it, I suspect that this may be caused by some initialization conflict between the ATF in BSP41 and the Bootloader used, this needs further testing. BR Joey Re: S32G RDB2 multicore boot hang in bsp41 Hi Joey, Attachment is my blob.bin. Thanks. Re: S32G RDB2 multicore boot hang in bsp41 hi,Allen_Cheng Thank you for your reply. Your BSP41 print message attachment shows that BL2 should not be started, check to see if the fip.bin of BSP41 was loaded correctly during your compliance with AN13750. In addition, in order to provide better support, whether you can provide your blob.bin, I will test this problem for you as soon as possible. BR Joey Re: S32G RDB2 multicore boot hang in bsp41 Hi Joey, The ATF load address are the same in bsp41/bsp42. Entry point are 0x34700000. Thanks. Allen Re: S32G RDB2 multicore boot hang in bsp41 hi，Allen_Cheng Did you change the ATF Load address and Entry point in the Bootloader? As shown in the following figure, the corresponding address is different for different versions of BSP. Also, you need to check that no SRAM image loading and running addresses of M7 and fip are conflicting BR Joey

S32G RDB2 マルチコア ブートが bsp41 でハングする こんにちは、NXPチームの皆様、 公式ドキュメントに従って、A53とM7でマルチコア環境をセットアップしてみますAN13750。 bsp41でブートの問題を見つけたので、bsp42を使用して明確にします。 しかし、BSP42はLinuxカーネルに正常に起動できます。 BSP41は常にハングインします ブートローダー 0x2 アプリケーション 1 のイメージ フラグメント 0 が QSPI からロードされました。 ブートローダー 0x2アプリケーションM7_0がロードされました。 これら2つのバージョンを添付ファイルでログインします。 この問題を明確にするために助けていただけますか? ありがとうございます。 SWです。 Integration_Reference_Examples_S32G2_2023_06 EBの27.1 測温抵抗体(RTD)4.4_4.0.0_P05_HF01 HSE_FW S32G2XX_0_1_0_16 Re:Bsp41のS32G RDB2マルチコアブートがハングする こんにちはジョーイ、 ATF ロード アドレスは bsp41/bsp42 で同じです。 エントリーポイントは0x34700000です。 感謝。 アレン

TJA1043 - Normal Mode - Using for only Bus Diagnostic Hello all, I want to detect if there is a problem in CAN Bus. At first, I thought that I can do it in listen only mode. As I understand from datasheet, bus diagnostic functions are only active when in normal mode. If so, what should I do to TXD pin? Should I connect it to ground or something else? Can I use TJA 1043 to only detect bus failures? I will not use a microcontroller. I want to show if there is an error with led with using ERRN pin.  Thank you in advance. Re: TJA1043 - Normal Mode - Using for only Bus Diagnostic Hello Sam, I think the TXD pin can be left unconnected as it is internally pulled up to VIO. BRs, Tomas Re: TJA1043 - Normal Mode - Using for only Bus Diagnostic Thank you for the reply, Thomas, I will keep in mind about current rating. What about the TXD pin? Should it be connected to GND or 5V or something else to not to interfere the bus? Sam Re: TJA1043 - Normal Mode - Using for only Bus Diagnostic Hello Sam, You are correct that the TJA1043’s bus failure diagnostic is only active in Normal mode (STB_N = EN = 1). The ERRN pin will be pulled low when a bus error is detected. Keep in mind the current rating of the ERR_N pin as shown in table 8 of the datasheet. For more information, please refer to the AH1014, chapter 6.6 - Bus failure diagnosis. BRs, Tomas

SPDIF maximum sampling rate I'm planning to use the SPDIF of the i.MX RT 1060. What is the maximum sample rate that SPDIF can input and output? Is 192kHz correct? Re: SPDIF maximum sampling rate Correct, up to 192kHz. Best regards, Omar

SJC_DISABLE blocking flashing over SWD Hi, When blowing the SJC_FUSE on an i.MX RT1060 two things seems to happen: The debug session I have open over SWD with an MCU-Link connected seems to stop working immediately I'm unable to start new debug sessions or perform other actions towards the MCU using the MCU-LINK and SWD While this is OK, I'm wondering if disabling the JTAG interface on the MCU also disables any SWD interactions? Thanks, Daniel 回复： SJC_DISABLE blocking flashing over SWD Thanks! 回复： SJC_DISABLE blocking flashing over SWD Hi @MulattoKid , It is from AN12419: Secure JTAG for i.MXRT10xx. ANs related to security features now require an NDA and a permission request to access them. Best regards, Gavin 回复： SJC_DISABLE blocking flashing over SWD Hi @Gavin_Jia, Thanks for confirming! Out of curiosity, where is this picture from? Kind regards, Daniel 回复： SJC_DISABLE blocking flashing over SWD Hi @MulattoKid , Please kindly refer to this pic： SJC_DISABLE negates both lines, so both are blocked. Either JTAG/SWD or even test control. Bests, Gavin

S32K311 FLEXIO PWM pulse generation Hi, FLEXIO0 clock is derived from CORE clock. CORE clock is 120MHZ. As per below screenshot FLEXIO0 clock is 120MHZ. In FLEXIO_PWM I am confused in below points. 1) PIN0 represents which PIN? Our understanding is PIN0 means FLEXIO0_D0. PIN0 can be PTD0 or PTA10 or PTD9. Based on which pin is configured as FLEXIO D0 that PIN becomes PIN0. Is my understanding correct? 2) clock prescaler If we set FLEXIO_PWM_IP_CLK_DIV_256 then it divides clock with 256. FLEXIO0 clock =  120MHZ. 120MHZ/256 = 468.750KHZ Is our understanding correct? 3) clock prescaler alternate I dont see PWM enable dual clock mode option in FLEXIO_MCL/FLEIO_PWM modules. 4) Period/Dutycycle [Ticks] What is Ticks? If I set period value 512, Period = 512/(468.750KHZ) = 0.0010922666666667 = 1.092 msec period pulse will get generate correct? Duty = 256 -> 50% duty cycle Thanks, Y Uma Maheswara Reddy. Re: S32K311 FLEXIO PWM pulse generation Thank you Leo. Re: S32K311 FLEXIO PWM pulse generation Hi, Thank you so much for your interest in our products and for using our community. Regarding your questions… 1. Your understanding is correct. 2. It is correct too. 3. There is no dual clock mode for FlexIO_PWM. So there is no need to configure the Clock prescaler Alternate. I will report such issue. 4. Ticks are clock cycles. And yes, with such configuration you get a PWM signal with period 1.092ms and duty cycle of 50%. Have a nice day! Re: S32K311 FLEXIO PWM pulse generation hello brother....can you share that project to me....becuse i dont know which api i have to call and all......so can you please share me that flexio pwm project to me.

SDカードをbz2にする方法についてのお問い合わせ IMX8MPを使用してimx-image-core環境で開発しています。(6.1-mickledore imx8mp-lpddr4-evk) device.sdcardは、kernel、rootfs、my_diskなどを組み合わせて作成しました。 uuuで書くと、うまく機能します。 sdcard ファイルは bz2 で圧縮されました。 sdcard ファイルを bz2 にする方法は、以下の通りです。 tar cvfj device.sdcard.bz2 device.sdcard bz2 ファイルを uuu で書き込んだところ、書き込み操作は完了しましたが、カーネルの起動に失敗しました。 「uuu.exe-b emmc_all imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evkdevice.sdcard.bz2" デバイス 0: 不明なデバイス MMC:カードはありません パーティション#0に切り替えて、OK mmc2(パート0)は現行デバイスです ** パーティションテーブルなし - mmc 2 ** パーティションmmc 2:1が見つかりませんでした どこでうまくいかなかったのでしょうか? Re: SDカードをbz2にする方法についてのお問い合わせ 問題にも書きましたが、自分で画像を組み立てました。 bz2 の代わりに zstd を使用しましたが、うまく機能しました。 私が持っているUUUのドキュメント(nxpfrankliによる)にはbz2を使用するように書かれているので、そうしました。 bz2 は圧縮ファイルを正しく書き出しません。 zstd は正常に動作します。 ありがとうございます。 Re: SDカードをbz2にする方法についてのお問い合わせ 私はNXPリファレンスボードを持っており、それに基づいてボードを設計しました。 作成された iamge が mmc にダウンロードされます。 核心的な問題は、非圧縮画像は機能しますが、作成した圧縮画像は機能しないということです。 Re: SDカードをbz2にする方法についてのお問い合わせ NXPリファレンスボードを使用していますか、それとも自分で設計したボードを使用していますか?適切なブートデバイスを選択しましたか、私はあなたがemmcにイメージをダウンロードするつもりであることがわかります。

88W8987 GPIO制御 こんにちは。 私は88W8987 + i.MX RTで作業しています。私はいくつかのGPIOを制御する必要がありますが、Wi-FiやBluetoothのドキュメントでも、それを行うために必要なコマンドを見つけることができませんでした。これはどのように行うことができますか? この質問をするのは、製造段階でBluetooth、特にPCMピンをテストする必要があるためです。私がすでに作業したBluetoothコントローラーの中には、PCMにループバック機能があり、これに便利なものがありますが、88W8987にはこの機能がないと思います。 ご清聴ありがとうございました。 よろしくお願いいたします J.V.メロ。

Inquiry on how to make sdcard into bz2 I am developing in the imx-image-core environment using IMX8MP. (6.1-mickledore imx8mp-lpddr4-evk) I created device.sdcard by combining kernel, rootfs, my_disk, etc. When written with uuu, it works well. The sdcard file was compressed with bz2. The method for making an sdcard file into bz2 is as follows. tar cvfj device.sdcard.bz2 device.sdcard When I wrote the bz2 file with uuu, the write operation was completed, but kernel booting failed. "uuu.exe -b emmc_all imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evk device.sdcard.bz2" Device 0: unknown device MMC: no card present switch to partitions #0, OK mmc2(part 0) is current device ** No partition table - mmc 2 ** Couldn't find partition mmc 2:1 Where did it go wrong? Re: Inquiry on how to make sdcard into bz2 As I wrote in the question, I assembled the image myself. I used zstd instead of bz2, and it worked well. The UUU documentation I have (by nxpfrankli) says to use bz2, so I did that. bz2 does not write compressed files correctly. zstd works fine. thank you. Re: Inquiry on how to make sdcard into bz2 For detailed usage of UUU, see github.com/NXPmicro/mfgtools/wiki. Re: Inquiry on how to make sdcard into bz2 Hi @kiyoung  For the uncompressed image works well, do you build them yourself or the demo images? Re: Inquiry on how to make sdcard into bz2 I have an NXP reference board and designed the board based on it. The created iamge is downloaded to mmc. The core question is that the uncompressed image works, but the compressed image I created does not work. Re: Inquiry on how to make sdcard into bz2 Are you using NXP reference board or the board you designed yourself? Have you choose the proper boot device, I see that you are going to downlaod images to emmc.

MC33SB0400ESR2和FS32K142HFT0VLHT的晶圆是多少nm的？ MC33SB0400ESR2和FS32K142HFT0VLHT的晶圆是多少nm的？ 回复：MC33SB0400ESR2和FS32K142HFT0VLHT的晶圆是多少nm？ 你好@nihaoROBOT S32K1的工艺为90nm，MC33SB0400ESR2的工艺为250nm。

SPDIF 最大サンプリング レート i.MX RT1060のSPDIFを使う予定です。 SPDIFが入力および出力できる最大サンプルレートはどれくらいですか? 192kHzは正しいですか? 日時:SPDIF最大サンプリングレート 正しい、最大192kHz。 よろしくお願いいたします オマル

88W8987 GPIOs Control Hi guys. I am working with 88W8987 + i.MX RT. I need to control some GPIOs, but I was unable to find the necessary commands to do that, neither in Wi-Fi or bluetooth documentation. How can this be done? I asking this question because I need to test the bluetooth in the production phase, specially the PCM pins. Some bluetooth controllers that I have already worked have a loopback feature in PCM that is useful for this, but I think that the 88W8987 doesn't have this feature. Thanks for your attention. Best Regards, J. V. Melo. Re: 88W8987 GPIOs Control Hi Daniel, Thanks for your reply. Regards, J. V. Melo. Re: 88W8987 GPIOs Control Hi, Sorry for the late reply. The GPIO's are configurable, but the configuration is saved in firmware, and this can't be changed by customers. For BT testing, we usually recommend the SDK demo edgefast_bluetooth_shell. You can find more information in UM11442. I'm sorry for the inconvenience. Regards, Daniel. Re: 88W8987 GPIOs Control Hi Daniel, The HFP has already been running with a proprietary stack. The point is, I am trying to execute a simple test in the production phase and to do that I would like to use the PCM pins like GPIOs, taking then control. As far has I know the datasheed says that these pins can be used like GPIOs, instead of the default PCM function. How can this be done? I mean, pin setup, pin read and pin control. Thanks. Re: 88W8987 GPIOs Control Do you want to test HFP? RT1170 EVK requires a HW rework to enable PCM (I understand you are using a custom board). Just in case you based your design on the EVK, there are some guidelines to enable PCM in Hardware Rework Guide for EdgeFast Bluetooth Protocol Abstraction Layer. This document is available in the following directory of the SDK bundle SDK_2_16_100_MIMXRT1170-EVKB\docs\wireless\bluetooth\edgefast_bluetooth. Regards, Daniel. Re: 88W8987 GPIOs Control Hi Daniel. First, thanks for you quick reply. What RT are you using? i.MX RT1176. Are you using an EVK? No, I have a custom board. What SDK are you using? 2.13.1 SDK. Regarding Wi-Fi, I am working with the SDK drivers. Regarding Bluetooth, I am working with a proprietary stack. Are you using a module for 88W8987? Yes. It is LBEE5QD1ZM from Murata. Thanks. Re: 88W8987 GPIOs Control Hi, What RT are you using? Are you using an EVK? What SDK are you using? Are you using a module for 88W8987? Regards, Daniel.

How many nm is the wafer of MC33SB0400ESR2 and FS32K142HFT0VLHT? How many nm is the wafer of MC33SB0400ESR2 and FS32K142HFT0VLHT? Re: How many nm is the wafer of MC33SB0400ESR2 and FS32K142HFT0VLHT? Hi@nihaoROBOT The process of S32K1 is 90nm，and the MC33SB0400ESR2 is 250nm.

88W8987 GPIO控制 嗨，大家好。 我正在使用 88W8987 + i.MX RT。我需要控制一些 GPIO，但在 Wi-Fi 或蓝牙文档中都找不到执行此操作所需的命令。这该如何做呢？ 我问这个问题是因为我需要在生产阶段测试蓝牙，特别是 PCM 引脚。我已经使用过的一些蓝牙控制器在 PCM 中具有环回功能，这很有用，但我认为 88W8987 没有此功能。 感谢您的关注。 此致， JV Melo。

S32K3 GPIO HIGH-Z Hi，NXP experts In S32DS3.5, how do I configure pin to state HIGH-Z?   S32K312+RTD4.0.0 In picture 1 it says can be configured as HIGH-Z，but I can't find the configuration item. It is configurable in EB（picture 3）. Re: S32K3 GPIO HIGH-Z For anyone looking on using Siul2_Port_Ip_SetPinDirection to set to Hi-Z, here is how to call the function: Siul2_Port_Ip_SetPinDirection(PORT, PIN, SIUL2_PORT_HI_Z); For input variable 1 of the function, which is `Siul2_Port_Ip_PortType * const base`, you need to use the defines mentioned in `Siul2_Port_Ip_Defines.h` and not the ones `Siul2_Port_Ip_Cfg.h`. You can find out what define the Pin you are using belongs to by checking in  `Siul2_Port_Ip_Cfg.h` as shown below: Now that PTD_H_HALF is known, which is Port D High Half Base, find it in `Siul2_Port_Ip_Defines.h` and use it as the first input argument.  For input variable 2, you can use the defines mentioned in  `Siul2_Port_Ip_Cfg.h` which is nothing but the Pin Number.  Once the pin is set to SIUL2_PORT_HI_Z, you do not have to use Siul2_Dio_Ip_WritePin function as it is only used to set the Pin to High or Low and not for SIUL2_PORT_HI_Z.    I hope this gives a bit more clarity.  Re: S32K3 GPIO HIGH-Z Hi @Chenxu1  Unlike EB Tresos, S32 ConfigTools does not have the option to set the PortPin Direction to PORT_PIN_HIGH_Z, as this is the default value. If you want to change it, you can use the functions Siul2_Port_Ip_SetPinDirection() or Port_SetPinDirection(). BR, VaneB

integrating KSZ8795 on imx8mplus This is how I changed the device tree: &eqos { //no-change-(for a qualcomm based eth chip) pinctrl-names = "default"; //eth1 pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rgmii-id"; phy-handle = <&ethphy0>; status = "okay"; mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; reset-assert-us = <10000>; reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-deassert-us = <30000>; eee-broken-1000t; at803x,vddio-1p8v; at803x,vddio-disable; }; }; }; &fec { //linked to ksz8795 pinctrl-names = "default"; //eth0 pinctrl-0 = <&pinctrl_fec>; phy-mode = "rgmii-id"; fsl,magic-packet; status = "okay"; fixed-link { speed = <1000>; full-duplex; }; }; ----------------------------------------------------------------------------------------- &ecspi2 { #address-cells = <1>; #size-cells = <0>; fsl,spi-num-chipselects = <3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, /*SS0*/ <&gpio4 4 GPIO_ACTIVE_LOW>, /*SS1*/ <&gpio4 5 GPIO_ACTIVE_LOW>; /*SS2*/ clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, <&clk IMX8MP_CLK_ECSPI2_ROOT>; clock-names = "ipg", "per"; status = "okay"; ksz8795: switch@0 { reg = <0>; compatible = "microchip,ksz8795"; spi-max-frequency = <5000000>; pinctrl-names = "default"; /* spi-cpha; spi-cpol; */ status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan1"; phy-mode = "rgmii-id"; fixed-link { speed = <100>; full-duplex; }; }; port@1 { reg = <1>; label = "lan2"; phy-mode = "rgmii-id"; fixed-link { speed = <100>; full-duplex; }; }; port@2 { reg = <2>; label = "lan3"; phy-mode = "rgmii-id"; fixed-link { speed = <100>; full-duplex; }; }; port@4 { reg = <3>; label = "cpu"; phy-mode = "rgmii-id"; ethernet = <&fec>; fixed-link { speed = <1000>; full-duplex; }; }; }; }; spidev1: spi@1 { reg = <1>; compatible = "rohm,dh2228fv"; spi-max-frequency = <500000>; }; spidev2: spi@2 { reg = <2>; compatible = "rohm,dh2228fv"; spi-max-frequency = <500000>; }; }; ---------------------------------------------------------------------------- The board is booted and i loads the module: ksz_common, ksz8795 and ksz8795_spi I can see the respective nodes formed. # ifconfig eth0: flags=4163 mtu 1501 inet6 fe80::8bd8:a721:8c85:3a61 prefixlen 64 scopeid 0x20 ether 38:d5:47:00:2e:9d txqueuelen 1000 (Ethernet) RX packets 42 bytes 3094 (3.0 KB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 73 bytes 12753 (12.7 KB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 eth1: flags=4099 mtu 1500 ether 38:d5:47:00:2e:9e txqueuelen 1000 (Ethernet) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 0 bytes 0 (0.0 B) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 device interrupt 52 lan1: flags=4163 mtu 1500 inet6 fe80::f4f3:314b:f7c3:9bd5 prefixlen 64 scopeid 0x20 ether 38:d5:47:00:2e:9d txqueuelen 1000 (Ethernet) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 14 bytes 2434 (2.4 KB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 lan2: flags=4163 mtu 1500 inet6 fe80::1bd1:9463:93c0:732c prefixlen 64 scopeid 0x20 ether 38:d5:47:00:2e:9d txqueuelen 1000 (Ethernet) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 14 bytes 2434 (2.4 KB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 lan3: flags=4163 mtu 1500 inet6 fe80::833e:9b97:6b1e:82ae prefixlen 64 scopeid 0x20 ether 38:d5:47:00:2e:9d txqueuelen 1000 (Ethernet) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 14 bytes 2434 (2.4 KB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 ----------------------------------------------------------------------------------------------------------------------------- I can also see an error from the spi-driver from dmesg log: DBUG: KSZ_common:ksz_switch_register: of_get_phy_mode returned -22 [ 57.561350] DBUG: KSZ_common:ksz_switch_register: Retrieved PHY mode 0 [ 57.561353] DBUG: KSZ_common:ksz_switch_register: Failed to retrieve PHY mode, error -22 from ksz_common.c: if (dev->dev->of_node) { printk("DBUG: KSZ_common:ksz_switch_register: Device tree node found, retrieving PHY mode\n"); ret = of_get_phy_mode(dev->dev->of_node, &interface); if (ret == 0) { dev->compat_interface = interface; printk("DBUG: KSZ_common:ksz_switch_register: Retrieved PHY mode %d\n", interface); } else { printk("DBUG: KSZ_common:ksz_switch_register: Failed to retrieve PHY mode, error %d\n", ret); } PRINT was added by me to debug-this is the only "error msg" i see from driver. But the driver loads successsfully Regarding phy-mode: There are other prints after above error : [ 57.576542] CLSU:KSZ8795: Configuring addr 0x87, bits 0x8, set 1 [ 57.576597] CLSU:KSZ8795: Configuring port 4, offset 0x0, bits 0x40, set 0 [ 57.576631] CLSU:KSZ8795: Configuring port 4, offset 0x2, bits 0x80, set 0 [ 57.576665] CLSU:KSZ8795: Configuring port 4, offset 0x0, bits 0x20, set 1 [ 57.576717] CLSU:KSZ8795: Configuring CPU port [ 57.576750] CLSU:KSZ8795: Setting RGMII mode So i suppose the phy-mode is being set to rgmii ---------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- ISSUE : I connected an ethernet cable between my pc and the board to check the comm ,Set a static ip for eth0 on board. i can see a link is established b/w them . But i cannot ping each other. Data packets are not seem to be receiving at both ends.(Validated that hardware is working fine) from device to pc # ping 192.168.1.50 PING 192.168.1.50 (192.168.1.50) 56(84) bytes of data. From 192.168.1.30 icmp_seq=1 Destination Host Unreachable Since link is being establish and ping is not happening i suspect - it must be some configuration issue. Either in the device tree or in the Register Writes. Please help me to troubleshoot the issue. Re: integrating KSZ8795 on imx8mplus It worked. The issue was that the driver I used was not updated. It was a 5 port switch. And the fifth port was not registering as it does (N-1) check on the ports. with tot no. of ports set to N=5. Adjusting the value slightly solved the issue. Re: integrating KSZ8795 on imx8mplus Hi You can refer other dts to set switch node. switch: switch@5f { compatible = "microchip,ksz9897"; reg = <0x5f>; pinctrl-0 = <&pinctrl_ksz>; interrupt-parent = <&gpio4>; interrupts = <18 IRQ_TYPE_EDGE_FALLING>; phy-mode = "rgmii-id"; ports { #address-cells = <1>; #size-cells = <0>; lan1: port@0 { reg = <0>; label = "lan1"; phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; }; lan2: port@1 { reg = <1>; label = "lan2"; phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; }; lan3: port@2 { reg = <2>; label = "lan3"; phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; }; lan4: port@3 { reg = <3>; label = "lan4"; phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; }; port@5 { reg = <5>; label = "cpu"; ethernet = <&fec1>; phy-mode = "rgmii-id"; fixed-link { speed = <1000>; full-duplex; }; }; Best Regards Zhiming Re: integrating KSZ8795 on imx8mplus kernel is 5.10

新しい MBDT バージョン (1.5.0) のピン配置 S32K3ファミリ用MBDTの新バージョン(1.5.0)へ開発を移行しています。 LCU出力など、さまざまな機能用にいくつかのピンを構成する必要がありますが、新しいバージョンのS32configツール(1.7)は以前のもののように機能しないことがわかりました。 MCAL グループの下に新しい PORT グループが作成され、DRIVERS の下の古い SIUL2-PORT は削除されました。以前のバージョンでは、PIN VIEW に新しいピンが追加されるたびに。PORT グループの設定が更新されません。 この新しいバージョンでピン構成を追加または変更する適切な手順は何ですか。 よろしくお願いいたします。 Re: 新しい MBDT バージョン (1.5.0) のピン構成 情報をありがとう。これで、ピンを正しい方法で構成できます さらに、PWM期間が更新されないという問題があります。すべてのPWM出力は、ConfigToolで設定されたデフォルトのDTにフリーズします。 EMIOS0 チャネル 1 と 2 をアンシングしています。 このテーマについて何か考えはありますか。