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S32K322 - M7-0 と M7-1(デュアル) コアの通信方法は? こんにちはチーム、 1.デュアルコア通信を理解するために私を導いてください。 2. サンプルコードはありますか? 3. 参考書(Rev.8, 01/2024) は、プラットフォーム間通信 (IPC) について見ていませんでした。 S32k322のデュアルコア通信について詳しく教えてください。 Re:S32K322 - M7-0とM7-1(デュアル)コアの通信方法は? こんにちはチーム、 1. パッケージ SW32K3_S32M27x_RTD_4.4_4.0.0_P20 は、デュアルコアのサンプル コードが S32K322 で利用できますか? 2. IPCFドライバーがない場合、デュアルコアはS32K322で通信できますか? 3. S32K322デュアルコア通信のサンプルコードを教えてください。 Re:S32K322 - M7-0とM7-1(デュアル)コアの通信方法は? @VaneB更新していただきありがとうございます
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S32K322 - 如何通信M7-0和M7-1(双)核? 大家好, 1.您能指导我了解双核通信吗? 2. 有没有可用的示例代码? 3. 在参考手册(Rev.8,01/2024)没有看到有关跨平台通信(IPC)的信息。 您能否提供有关 S32k322 中双核通信的一些详细信息? 回复:S32K322 - 如何通信M7-0和M7-1(双)核? 大家好, 1.软件包SW32K3_S32M27x_RTD_4.4_4.0.0_P20 ,其中双核示例代码可用于S32K322? 2.没有IPCF驱动程序,双核可以在S32K322中通信吗? 3.您能分享一下S32K322双核通信的示例代码吗? 回复:S32K322 - 如何通信M7-0和M7-1(双)核? @VaneB感谢更新
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MC9S12C64MFA Port T set up question MC9S12C64MFA, Code Warrior 5.9.0, coding in assembler. I am setting up Port T but I'm not sure I'm doing it right. Here is what I am trying to accomplish: PT0 is for PWM control of a solenoid valve. PT3 is a general purpose output. PT1,2 4,5,6,7 are all output compare channels. All are under port control with interrupt on compare match enabled. When I load the output compare value I will set the associated pin to the appropriate state. When the match occurs and the interrupt is triggered I will set the pin to the appropriate state in the ISR. Here is what I have so far: movb #$FF,DDRT ; All pins outputs movb #$01,MODRR ; PWM control on PT0, PT1,2,3 on Timer control movw #$0000,TCTL1 ; All pins under port control movb #$F6,TIOS ; Output Compare on PT1,2,4,5,6,7 movb #$01,PWME ; PWM control on PT0 Should this work? Regards, Robert Re: MC9S12C64MFA Port T set up question Game modes and events include team play, survival elimination, and seasonal tournaments planet clicker 3 online. Re: MC9S12C64MFA Port T set up question My goodness, I sure had that wrong! Thanks so much for the detailed explanation. As soon as I get my PCB finished I'll try that out. Regards, Robert Re: MC9S12C64MFA Port T set up question Hi, I tried to do it without test. You can compare. If the alternative function (another from GPIO) is enabled it takes precedence over all enable peripherals at pin with less priority. Priority starts from GPIO (the least) in the pin description table. When you disconnect TIM from pin and you want to control them as output by SW in the interrupt(not by automatic OC function) then you have to set it as GPIO output mode. // set ports PTT = ; // good to set initial value at the pins before // it is switched from input(default) to output DDRT = 0xFE; // pin 7,6,5,4, ,2,1 are driven by SW, pin 0 driven by PWM // pin 3 is also output in GPIO mode //select pins connections MODRR = 0B00000001 // TIM,TIM,TIM,TIM, GPIO,TIM,TIM,PWM // select TIM function TCTL1 = 0x00; // The TIM is disconnected from pins, value will be set manualy TIOS = 0xFE // TIM channels 7,6,5,4,3,2,1 in OC function // Set PWM parameters, period, duty, polarity .... // Set TIM parameters .. predcaler, period, OC value .... // enable interrupt for TIM TIE = 0B11100110; // enable TIM interrupt for channel 7,6,5,4, 2,1 //enable interrupt globally asm CLI // Run timer, set debug possibilities, set fast flag clear for TIM TSCR1 = 0xF0; // TEN-run timer; (TSWAI,TSFRZ)-good to set // to be able to debug; fast TIM flags clear,x,x,x,x // Run PWM_0 PWME = 0x01; // run PWM0 at PT0 Best regards, Ladislav
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S32K1xx GPIO pin of J5-17 Reference this pic :  So, how do I use this GPIO pin of [J5-17] ? Ref: https://www.nxp.com/document/guide/getting-started-with-the-s32k144evb:NGS-S32K144EVB  Re: S32K1xx GPIO pin of J5-17 Hi @CY9  Yes, it is the same for those pins.  Re: S32K1xx GPIO pin of J5-17 Got it, Thanks And the same with J2-18/20 , right  Re: S32K1xx GPIO pin of J5-17 Hi @CY9  Sorry for the inconvenience, this is a typo the pin is not connected to anything and there is no pad available to connect it to the MCU.  B.R. VaneB
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[iMX8M Nano] Using General Purpose Timer (GPT) to Count the external Signal Pulses Question:  What is the maximum rising time of external GPT_CLOCK signal? The Problem: We are using iMX8 Nano CPU…We want to use GPT TIMER to count the pulse of external signal…we configure UART3_TXD pad (D18) as GPT1_CLK function and connect our external clock to this pin. We can see the GPT Counter count this signal. However, this only works with simulated signal with rising time about 50ns (see the below picture). When we inject the real signal with rising time about 250ns…the GPT does not count. I use devmem2 tool to access the register directly as below: Set Custom Pin (0x30330248) as GPT1_CLOCK: 0x00000003 Set Clk Select (0x303305E8) to select external clock which is GPT1_CLK: 0x00000001 Set counter mode via Control Reg (0x302D0000): 0x000000C3 Read the Counter value via Count (0x302D0024) Compare the two rising edges of the two signal pulses The Green Line is the simulated signal The Mint Blue is the real signal i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Yocto Project Re: [iMX8M Nano] Using General Purpose Timer (GPT) to Count the external Signal Pulses Hello @Coeus412  Please be sure that this condition is achaiving: The GPT counter can be operated using an external clock from outside the device, and this is the input pin used for that purpose. The external clock input (GPT_CLK) is treated as asynchronous to the peripheral clock (ipg_clk). To ensure proper operations of GPT, the external clock input frequency should be less than 1/4 of frequency of the peripheral clock (ipg_clk). Hysteresis characteristics on this pad will be required because this is a clock input. (From reference manual 12.1.2.1 External Clock Input) Best regards, Salas. Re: [iMX8M Nano] Using General Purpose Timer (GPT) to Count the external Signal Pulses I notice when we use the simulated signal generated by another GPIO of IMX8 the GPT Counter can count correctly (even though the rising time 250ns same as real signal) …but it does not count the real signal. I am checking the datasheet and found below block diagram (there is Sync block with ipg_clk). Does it mean the external GPT_CLK signal need to synchronize with ipg_clk?
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systemd Latest Yocto Build Issue: i.MX6DL Hi  I am facing issue with systemd with fsl-imx-preferred-env.inc, built rootfs using  $ DISTRO=fsl-imx-xwayland MACHINE=imx6dlsabresd source imx-setup-release.sh -b build-xwayland $ bitbake imx-image-full When I boot the they system getting below message, which is stopping me to run systemd.  Reloading system manager configuration. [ 2830.481105] systemd-sysv-generator[677]: SysV service '/etc/init.d/sshd' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! [ 2830.513005] systemd-sysv-generator[677]: SysV service '/etc/init.d/alignment.sh' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! [ 2830.546612] systemd-sysv-generator[677]: SysV service '/etc/init.d/sendsigs' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! [ 2830.577386] systemd-sysv-generator[677]: SysV service '/etc/init.d/trousers' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! [ 2830.608168] systemd-sysv-generator[677]: SysV service '/etc/init.d/umountnfs.sh' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! [ 2830.639632] systemd-sysv-generator[677]: SysV service '/etc/init.d/tee-supplicant' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! [ 2830.670915] systemd-sysv-generator[677]: SysV service '/etc/init.d/halt' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! [ 2830.706333] systemd-sysv-generator[677]: SysV service '/etc/init.d/single' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! [ 2830.739992] systemd-sysv-generator[677]: SysV service '/etc/init.d/reboot' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! [ 2830.770901] systemd-sysv-generator[677]: SysV service '/etc/init.d/rc.local' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! [ 2830.803557] systemd-sysv-generator[677]: SysV service '/etc/init.d/umountfs' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! [ 2830.834325] systemd-sysv-generator[677]: SysV service '/etc/init.d/psplash.sh' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! [ 2830.865316] systemd-sysv-generator[677]: SysV service '/etc/init.d/save-rtc.sh' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! [ 2830.896496] systemd-sysv-generator[677]: SysV service '/etc/init.d/fuse' lacks a native systemd unit file. ~ Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it safe, robust and future-proof. ! This compatibility logic is deprecated, expect removal soon. ! Starting default.target You are in emergency mode. After logging in, type "journalctl -xb" to view system logs, "systemctl reboot" to reboot, or "exiPress Enter for maintenance (or press Control-D to continue): Need solution for this problem. We need systemd in our system for some of services to start. Rgds Chandra i.MX6DL Re: systemd Latest Yocto Build Issue: i.MX6DL Issue got resolved, this problem due to SDCARD flashing. rootfs not had root permissions so some of files not getting created. Re: systemd Latest Yocto Build Issue: i.MX6DL Hello, This error is due to host pc, make sure that your host has all the yocto packages, build the full image first the you can build your image, Regards Re: systemd Latest Yocto Build Issue: i.MX6DL below is the shell we are getting, You are in emergency mode. After logging in, type "journalctl -xb" to view system logs, "systemctl reboot" to reboot, or "exit" to continue bootup. Press Enter for maintenance (or press Control-D to continue): sh-5.2# sh-5.2# sh-5.2#
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unable to use simulink s32 configuration in S32 Design Studio (S32DS) due to version mismatch Hi, I have a Simulink project which I'm trying to debug in S32DS. The code builds, runs, and I can debug, but I'm not able to view (or edit) the configuration in S32DS. I get the attached error. Do I need to install an additional addon version or how can I resolve this? Re: unable to use simulink s32 configuration in S32 Design Studio (S32DS) due to version mismatch Hi, @Deskwork4130 , The newly added S32K3 Toolbox version 1.5.0 is compatible with: - S32 Configuration Tools version 2024.R1.7 - S32 Design Studio version 3.5 Please try this setup with the most recent toolbox version and let us know if you still have issues with Design Studio integration. Hope this helps, Dragos Re: unable to use simulink s32 configuration in S32 Design Studio (S32DS) due to version mismatch the release notes of 1.5 refer to configuration tools version v2021.R1.7. release notes for 1.4 has v2021.R1.6. so this seems like a very minor change. what version of S32DS is compatible with this version of config tools? as a side note for anyone looking in the flexnet SW center v1.5 is not in the same place as the previous versions. it is in the generic MBDT not the S32K3 specific one for some reason. Re: unable to use simulink s32 configuration in S32 Design Studio (S32DS) due to version mismatch Hi, @Deskwork4130 , We just published the MBDT for S32K3 Toolbox version 1.5.0. Installing this version and running the debug again is what I advise.  Let us know if your problem persists. Best regards, Dragos
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S32K312 ICU S32K312,主频120MHz,EMIOS能采集3Hz的PWM信号吗 Re: S32K312 ICU [Google翻訳] S32K312、メイン周波数120MHz、EMIOSは3HzのPWM信号を収集できますか? Hi, 私たちの製品に興味を持ち、コミュニティをご利用いただき、誠にありがとうございます。 PWM 周波数が 3Hz で、eMIOS クロック周波数が 120MHz の場合 (内部カウンタ バスを使用) には 40,000,000 ティックが必要です。 1秒 - > 120MHz(120,000,000ティック) 3Hz = (1/3)秒 ->120,000,000 *(1/3) = 40,000,000ティック ただし、最大ティック数は 65,534 (16 ビット) です。 一方、ICUモード(SAIC、IPWM、IPM)は、Modulus Counterモードをタイムベースとして使用でき、グローバルプリスケーラ(1-256)、マスターバスプリスケーラ(1-12)、ICU eMIOSプリスケーラ(1-12)を使用できます。 したがって、あなたの質問に関しては、モジュラスカウンターモードをタイムベースとして使用する と 、ICUモードで3HzのPWM信号を収集できます。 お役に立てば幸いです。 よい一日を! Re: S32K312 ICU Mcl の構成は次のとおりです。 EMIOSのチャンネルをどのように設定すれば、希望する周波数分割値(240*12)を実現できるでしょうか? ありがとうございます!
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ECC SRAM double-bit error injected triggers hardfault Hi, I am using Error inject Module to inject double-bit to SRAM_U, and the all codes about eim or erm are copied from the link:Example S32K14x SRAM ECC Injection - NXP Community The example from the link does not trigger the hardfault and I have made my code identical to the example.So what's wrong with my code?Can anyone do me a favor? Thanks! Re: ECC SRAM double-bit error injected triggers hardfault Hi, Thank you for responding, I have compared the example with my code one by one and find the difference in linker files, that my linker files has not defined the __flash_vector_table__ which means the vector table will be copied into SRAM_U, this is the reason causes the bug. Re: ECC SRAM double-bit error injected triggers hardfault Hi @n00b123, First of all, you can debug the exception following this document / example: https://community.nxp.com/t5/S32K-Knowledge-Base/Fault-handling-on-S32K14x/ta-p/1114447 In SRAM_U, there is the stack, so there can be an issue on a function exit. What S32K1xx part do you have? If you have S32K11x, in SRAM_U, there is also the copy of the interrupt vector table. The example you linked disables the copying of the table from PFlash to SRAM. Regards, Daniel
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GD3162 SPIERR Hi NXP,  When I'm writing different values in different gate drivers, I'm facing SPIERR. The gate drivers are connected in a daisy chain configuration as is shown in the attached image. I have also attached the code snippet for the function which writes different values in the lower side 3 gate drivers. (Ideally the code design is to support single value to be written in all 6 GD's but due to some HW constraints, I had to implement separate functions for different configurations in lower side GD's. Even though SPIERR is there, I'm able to write the expected values to the registers Re: GD3162 SPIERR Hi all For anyone who wants to see how this case was resolved, please go to: GD3162 Daisy Chain Have a great day and best of luck. Re: GD3162 SPIERR Hi Akshat Sorry for the delay, I needed to do a little more research. What would be most helpful is to provide a scope or logic analyzer capture of the SPI frame, also including INTB signal, showing when the SPIERR is actually happening. Normally the GD should reject any invalid frame and not allow you to write any data in that case. SPIERR may occur if the number of SCLK pulses within an instance of CSB low is not a multiple of 24 (in your case 3x24 bits). SPIERR may also occur if the CRC data is incorrect. Please check which exact SPI frame is generating the SPIERR. Also please list down what register you are intending to write, and with which data, as well as the 3 bytes of data (R/W+addr+data+crc) sent to the SPI peripheral. Have a great day and best of luck. Re: GD3162 SPIERR Yes please do Re: GD3162 SPIERR I am starting to work on your case, I will contact you soon. Re: GD3162 SPIERR Putting it short, what I'm doing is....First sending txData to all 6 gate drivers and then for the particular gate drivers for which the configuration requirement is different, for those gate drivers, I'm over writing to the already configured value
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imx8 Quad Max determine if SOM is closed by reading a fuse? Is there a way to tell by a fuse or other way to determine id the "ahab_close" has been called? I would like to do this in Linux if there is a fuse I can read. Alternative, what user fuse is readable that I could set to use as an indicator if the closed status is not available? i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: imx8 Quad Max determine if SOM is closed by reading a fuse? Without a Linux user space utility that could call SCFW, does not really help. I have  a workaround for our case that allows our manufacturing process the ability to mange the fuses. Re: imx8 Quad Max determine if SOM is closed by reading a fuse? Hi, Thank you for your patience, The fuse is not readable from the user since the security differences from i.MX8MP (SECO and SCFW), there is a SCFW call that handles this and can help you (at U-boot, Linux, etc since it's a SCFW call). The life cycle is indeed a fuse but it's secured and you can read it though the API. U-boot does it in the mentioned command. It's below, I hope it helps. sc_err_t sc_seco_chip_info (sc_ipc_t ipc, uint16_t ∗lc, uint16_t ∗monotonic, uint32_t ∗uid_l, uint32_t ∗uid_h) Regards, Re: imx8 Quad Max determine if SOM is closed by reading a fuse? Response is great is you are using a terminal and a human is reading and acting upon it, so this is not a usable solution. I could not use the "ahab_status" in a uboot "test" command to send the kernel the status in a command line argument (result code was not always correct "$?") I do not understand why NXP could not use a readable fuse to indicate status just like imx8m Plus... There a so many unused fuses. Re: imx8 Quad Max determine if SOM is closed by reading a fuse? Here is the situation: We cannot allow a SOM that is "not closed" to run code that is signed, intended for a closed device. That is a major security hole. On the imx8M Plus, we could read a fuse to determine this and prevent the processor from booting, and report it as a security issue. On the Quad Max, it does not appear that there is a way to determine this by reading a fuse (I hope I am wrong), but Uboot  reporting this does not help... If there was a "user fuse" (NXP refers to them as "Customer OTP fuses") that I can read in user space that can be burned by uboot the same time I close the SOM, that would work. Re: imx8 Quad Max determine if SOM is closed by reading a fuse? Hi, Thank you for your interest in NXP Semiconductor products, You can confirm it in U-boot quickly with the command ahab_status. Regards Re: imx8 Quad Max determine if SOM is closed by reading a fuse? If there is a "Customer fuse" that can be read by the imx-scu-ocotp0 driver, that would work wonderfully...
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imx8 Quad Max 通过读取保险丝来确定 SOM 是否关闭? 有没有办法通过保险丝或其他方式来确定“ahab_close”已被调用? 如果有我可以读取的保险丝,我愿意在 Linux 中执行此操作。 或者,如果关闭状态不可用,我可以设置哪个用户保险丝可读以用作指示器? i.MX 8 系列 | i.MX 8QuadMax (8QM) | 8QuadPlus 回复:imx8 Quad Max 通过读取保险丝确定 SOM 是否关闭? 如果没有可以调用 SCFW 的 Linux 用户空间实用程序,那就没有什么帮助了。对于我们的情况,我有一个解决方法,可以让我们的制造过程能够管理保险丝。 回复:imx8 Quad Max 通过读取保险丝确定 SOM 是否关闭? 如果您使用终端并且有人正在阅读并采取行动,那么响应会很好,因此这不是一个可用的解决方案。 我无法使用 uboot“test”命令中的“ahab_status”向内核发送命令行参数中的状态(结果代码并不总是正确的“$?”) 我不明白为什么 NXP 不能像 imx8m Plus 一样使用可读保险丝来指示状态……有这么多未使用的保险丝。 回复:imx8 Quad Max 通过读取保险丝确定 SOM 是否关闭? 情况是这样的:我们不能允许“未关闭”的 SOM 运行已签名的、用于封闭设备的代码。这是一个重大的安全漏洞。 在 imx8M Plus 上,我们可以读取保险丝来确定这一点并阻止处理器启动,并将其报告为安全问题。 在 Quad Max 上,似乎没有办法通过读取保险丝来确定这一点(我希望我错了),但是 Uboot 报告这一点并没有帮助……如果有一个“用户保险丝”(NXP 将它们称为“客户 OTP 保险丝”),我可以在用户空间读取它,并且可以在我关闭 SOM 的同时由 uboot 烧录,那就可以了。 回复:imx8 Quad Max 通过读取保险丝确定 SOM 是否关闭? 如果有一个可以被 imx-scu-ocotp0 驱动程序读取的“客户保险丝”,那就太好了……
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What causes the RT685 SYSRSTSTAT register bit "ARM_APD_RESET" to be set? The "ARM_APD_RESET" bit of the SYSRSTSTAT register is described as "ARM RESET Event Detected"- what causes an "ARM RESET Event", and this bit to be set when the chip comes out of reset? Thanks! i.MXRT 600 Re: What causes the RT685 SYSRSTSTAT register bit "ARM_APD_RESET" to be set? Hi @NoahPendleton_Memfault, That is correct!  Re: What causes the RT685 SYSRSTSTAT register bit "ARM_APD_RESET" to be set? From some quick testing, I am able to confirm: - VDD_POR is set when the chip is powered up - PAD_RESET is set when the reset pin is used to reset the chip - ARM_APD_RESET is set when I use the debugger to reset the chip, or when NVIC_SystemReset() is triggered Let me know if I got any wrong! Re: What causes the RT685 SYSRSTSTAT register bit "ARM_APD_RESET" to be set? Thanks for the response @EdwinHz ! Will the bit be set from an NVIC SysReset, or only a reset from the debug port? Re: What causes the RT685 SYSRSTSTAT register bit "ARM_APD_RESET" to be set? Hi @NoahPendleton_Memfault, This bit indicates whether the ARM kernel has had a soft reset or not, as mentioned in the following blog post: https://www.cnblogs.com/henjay724/p/14027404.html.
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imx8 Quad Maxは、ヒューズを読み取ることでSOMが閉じているかどうかを判断しますか? ヒューズまたはその他の方法で「ahab_close」が呼び出されたIDを確認する方法はありますか? 私が読むことができるヒューズがある場合は、Linuxでこれをしたいと思います。 別の方法として、閉じたステータスが利用できない場合にインジケーターとして使用するように設定できる読み取り可能なユーザーヒューズは何ですか? i.MX 8ファミリ | i.MX 8QuadMax (8QM) | 8QuadPlus Re:imx8 Quad Maxは、ヒューズを読み取ってSOMが閉じているかどうかを判断しますか? SCFWを呼び出すことができるLinuxユーザースペースユーティリティがなければ、実際には役に立ちません。私は、製造プロセスがヒューズを管理する能力を可能にする、私たちのケースの回避策を持っています。 Re:imx8 Quad Maxは、ヒューズを読み取ってSOMが閉じているかどうかを判断しますか? 応答は素晴らしいです あなたが端末を使用していて、人間がそれを読み取って行動しているので、これは使用可能な解決策ではありません。 uboot の "test" コマンドで "ahab_status" を使用して、コマンドライン引数でカーネルにステータスを送信できませんでした (結果コードは常に正しい "$?" とは限りませんでした) NXPがimx8m Plusのように読み取り可能なヒューズを使用してステータスを表示できなかった理由がわかりません...未使用のヒューズがたくさんあります。 Re:imx8 Quad Maxは、ヒューズを読み取ってSOMが閉じているかどうかを判断しますか? 状況は次のとおりです: "閉じられていない" SOM が、閉じたデバイスを対象とした署名されたコードを実行することを許可することはできません。これは大きなセキュリティホールです。 imx8M Plus では、ヒューズを読み取ってこれを判断し、プロセッサの起動を防ぎ、セキュリティ問題として報告することができました。 Quad Maxでは、ヒューズを読み取ることでこれを判断する方法がないようですが(私が間違っていることを願っています)、これを報告しているUbootは役に立ちません...SOMを閉じると同時にubootで書き込むことができるユーザースペースで読み取ることができる「ユーザーヒューズ」(NXPはそれらを「顧客OTPヒューズ」と呼んでいます)があれば、それは機能します。 Re:imx8 Quad Maxは、ヒューズを読み取ってSOMが閉じているかどうかを判断しますか? imx-scu-ocotp0 ドライバーで読み取れる "Customer fuse" があれば、それは素晴らしい働きをするでしょう。
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FRDM-MCXN947 - CPU connection issue (MCU-LINK CMSIS-DAP issue) Hello, In my engineering school we give labs to a very large number of students using more than 100  FRDM-MCXN947 board. 1) Our students successfully compiled download and run there first programs (RGB led blink, switch etc) during the first lab. 2) During the second lab some of them can't connect anymore to the on-board cpu to download and debug (I suspect that they have updated the firmware, as explained hereunder). Here are the snapshots when entering the debug mode : 3) I disconnect the student board and connect my fresh new board with success ! (Since our labs, are installed with MCUXpresso IDE v11.9.1, I tried with the latest MCUXpresso without success connecting there boards again.) My board (working) : 4) From 3) I see a difference between the probe firmware versions : my working board use a MCU-LINK CMSIS-DAP_V3_128 the problematic board use a MCU-LINK CMSIS-DAP_V3_153 I tried to reverse the firmware to V3.128 but can't find it on your website. On NxP site, I only found MCU-LINK_installer_3.140 which allows me to reverse the board to V3_140 but the problem is still the same Do you know where I can find MCU-LINK_installer_3.128 ? Is is normal that upgrading the firmware cause such issue ? Do you have other ideas ? Thank you for your help ! Thierry Development Board MCXN Re: FRDM-MCXN947 - CPU connection issue (MCU-LINK CMSIS-DAP issue) ==> RESOLVED Dear Alice_Yang, I finally succeed to recover our boards access with MUC-LINK : I clicked several time STP ERASE button, spamming simultaneously the SW1/Reset button of the FRDM-MCXN947 board  (to reset the processor) ! Many thanks for your help ! (This worked with any version of MCU-LINK CMSIS-DAP which was finally not the point) The subject is closed/resolved Have a gret day Re: FRDM-MCXN947 - CPU connection issue (MCU-LINK CMSIS-DAP issue) Dear Alice, Thank you for your answer. Unfortunatly, the first step : STP Erase failed : When I "test connection", I get : Can you tell me please a way to reset the processor as suggested by the error message ? Is it possible without specific external hardware ?  Thank you, Thierry Re: FRDM-MCXN947 - CPU connection issue (MCU-LINK CMSIS-DAP issue) Thank you Alice. Unfortunlatly, the first step failed : SPT Erase give me this error message : Then I clic "Erase" : Clicking on "Test connection" return : Is there a way to reset the processor to attempts to open the debug port ? Thank you for your help, Regards, Thierry PS : the complete screen capture hereunder in case it may helps : Re: FRDM-MCXN947 - CPU connection issue (MCU-LINK CMSIS-DAP issue) Hello @tgrandpi  Please test according to the following steps:   Use SPT Erase. 2. Create a new workspace in MCUXpresso IDE. 3. Import a new simple demo. 4. Build and download the program for testing. If it still doesn't work, please download and install the latest version of MCUXpresso IDE.   BR Alice Re: FRDM-MCXN947 - CPU connection issue (MCU-LINK CMSIS-DAP issue) Thank you Alice for your answer. 1) Unfortunatly, reversing successfully (hereunder)  the version to 3.122  didn't resolve the issue. 2) I still get this message when entering download mode  : (I recall you that my other boards are running correctly on the same computer/MCUxpresso version with CMSIS-DAP V3.128 but can't find it. Anyway, I am wondering if the CMSIS-DAP version is the real issue...) FYI the led blinky application initially downloaded on these boards is still running on the processor. What can I do ? Thank you in advance for any help. Re: FRDM-MCXN947 - CPU connection issue (MCU-LINK CMSIS-DAP issue) Hello @tgrandpi  The attachment is MCU - LINK_V3_122. Please check if it works well on your side.  Please feel free to tell me if still can't work.  BR Alice
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MPC5604P MCU ID Hello, The chip I am currently using is MPC5604P, I need a unique MCU ID for calculation, but I checked the MCU ID registers of the two chips and found that the information is the same, MIDR1=0x56042416, MIDR2=0x28005011. is this normal? Re: MPC5604P MCU ID Hello, Yes there is Uniqe ID: Please refer to the reference manual chapter 17.3.4.2.1 TestFlash block Best regards, Peter
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编译时出现与 GM Libs 相关的 Code Warrior 错误 大家好,我正在与 Code warrior 开发工作室合作开发 DSC MC56F83789。我正在使用 GM 库并且它运行良好。今天,当我调试代码时,出现了 4000 多个与 GM Lib 函数相关的错误。我尝试创建新项目并更新现有代码,但是收到了相同的错误。 你能帮忙吗?
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Code warrior error related to GM Libs while compiling Hi Team, I am working with Code warrior development studio for DSC MC56F83789. I am using GM libraries and it was working fine. Today when I was debugging the code 4000 plus errors came related to GM Lib functions. I tried to create new project and updated the existing code however, I am receiving the same errors. Can you please help on this ? Re: Code warrior error related to GM Libs while compiling Hi, Pls download the library of rtcesl from the link( NXP Embedded Software Libraries 4.2 (DSP56800E, DSP56800EX) 😞 https://www.nxp.com/design/design-center/software/embedded-software/real-time-control-embedded-software-motor-control-and-power-conversion-libraries:RTCESL You have to create a group and load the rtcesl directory to the group, like: Pls have a try BR XiangJun Rong
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LX2160 two 1-Rank DDR4 DIMM modules with one memory controller (MC1) Hello NXP, We have a custom board with LX2160A CPU. We want to use two 1-Rank DDR4 DIMM modules with one memory controller (MC1), but we are getting error "Invalid cs_in_use value" during boot and only 8GB of 16GB of RAM are available after boot. We also tried to boot with two 2-Rank DIMMs in MC1, there were no errors and all 16GB of RAM were available after boot. The error seems to be coming from findrank() function, where cs_in_use value 0x5 (CS2+CS0) seems to be unsupported. Is configuration with two 1-Rank modules per one MC valid? Or maybe software updates are available that add support for this configuration? DIMM modules that we used: Innodisk M4C0-8GS1LCEM, 8GB, 3200 MT/S, 1-Rank, ECC. LX2160A clocks: CPU 2200, PLAT 700, DDR 1800. Software version: LSDK-21.08. Here is full boot log (attached boot-log.txt) with debug level traces enabled, DDR_DEBUG and DDR_PHY_DEBUG options are also enabled. Re: LX2160 two 1-Rank DDR4 DIMM modules with one memory controller (MC1) Using two 1-rank DDR4 DIMM on LX2160A may be possible, but it has not be validated and we don't have supported configuration. You may try it and see if you can get it to work using the QCVS tool. but we cannot guarantee it because it is not a supported configuration. Re: LX2160 two 1-Rank DDR4 DIMM modules with one memory controller (MC1) Yes, we already used QCVS DDR tool in Code Warrior, it allowed us to improve DDR eye diagrams. DDR memory seems to work stable after these adjustments. The problem is that if we use two 1R DIMM modules in one MC, we get an "Invalid cs_in_use value" error during boot and only one of the two 1R modules seems to be active. If we use two 2R modules in one MC, there are no problems or errors during boot and both modules are active. We want to know if two 1R DIMM modules on one MC is a valid configuration or not. Re: LX2160 two 1-Rank DDR4 DIMM modules with one memory controller (MC1) Please confirm the QCVS has been done. QCVS_DDR_User_Guide Thanks
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コンパイル中のGMライブラリに関連するコードウォリアーエラー こんにちはチーム、私はDSC MC56F83789のコード戦士開発スタジオで働いています。私はGMライブラリを使用していますが、正常に動作していました。今日、コード4000をデバッグしていたとき、GM Lib関数に関連するエラーが発生しました。新しいプロジェクトを作成し、既存のコードを更新しようとしましたが、同じエラーが表示されます。 これについて助けてもらえますか?
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