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MR-VMU-TROPIC GitHubリポジトリのライセンスとオープンソースステータス こんにちは、   MR-VMU-TROPIC FMUベースボードを調べています。GitBookのドキュメントには明確に「どちらもオープンソースのデザインであり、希望する形でコピー・再作成可能です」と明記されています。   しかし、 公式GitHub リポジトリには「オープンソースFMUベースボード」と説明されているにもかかわらず、現在LICENSEファイルがなく、設計ファイルの安全な利用や適応が困難になっています。   リポジトリに最近更新があったことに気づきました。チームは、 TropicCommunityVMUで使われているBSD-3-Clauseライセンスのような標準的なオープンソースライセンスファイルをGitHubリポジトリに追加することは可能でしょうか?   ご回答をお待ちしています。   Re: Licensing and open-source status for MR-VMU-TROPIC GitHub repository その問題を指摘していただきありがとうございます。社内で対応します。 Re: Licensing and open-source status for MR-VMU-TROPIC GitHub repository ライセンスファイルがGitHubリポジトリに追加されました。GitHub - NXP-Robotics/MR-VMU-TROPIC: TROPIC VMUシングルボードRT106Xのプレビュー · GitHub https://github.com/NXP-Robotics/MR-VMU-TROPIC/blob/main/LICENSE 指摘していただき、改めてありがとうございます! 敬具 ジェラルド
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i.MX8MP_EVK: YOCTO Compilation Error do_package() (Issue: tar & *at()) Hi, These are my yocto build parameters: Release: imx-linux-walnascar BSP Version: imx-6.12.49-2.2.0 MACHINE: imx8mpevk DISTRO: fsl-imx-xwayland I have been using this build environment successfully for the past couple of months. However, I suddenly started encountering the attached error. To troubleshoot, I completely cleaned the build environment, reinitialized the repository (repo init), synced everything again, and performed a fresh build. Unfortunately, I am still facing the same issue. Please find the attached log file for your reference. I would appreciate your help in identifying the root cause and suggesting a solution. i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: i.MX8MP_EVK: YOCTO Compilation Error do_package() (Issue: tar & *at()) bitbake imx-image-core Re: i.MX8MP_EVK: YOCTO Compilation Error do_package() (Issue: tar & *at()) What "bitbake command" are you using? I will do verification. Re: i.MX8MP_EVK: YOCTO Compilation Error do_package() (Issue: tar & *at()) Thank you for your response. I verified my build environment, and it already matches the configuration you recommended. Host OS: Ubuntu 22.04.5 LTS (Jammy) GNU tar version: GNU tar 1.34 $ cat /etc/os-release PRETTY_NAME="Ubuntu 22.04.5 LTS" ... $ tar --version tar (GNU tar) 1.34 However, I still encounter the same failure Re: i.MX8MP_EVK: YOCTO Compilation Error do_package() (Issue: tar & *at()) Please check the tar version, if the host is Ubuntu 24.04 and tar is 1.35 Build inside a container or VM with: Ubuntu 22.04 LTS GNU tar 1.34 Re: i.MX8MP_EVK: YOCTO Compilation Error do_package() (Issue: tar & *at()) Please find file below,  Here i am pasting the some lines of error  DEBUG: Executing python function extend_recipe_sysroot NOTE: Direct dependencies are ['/home/vvdn/LWT_Build/sources/poky/meta/recipes-devtools/binutils/binutils-cross_2.44.bb:do_populate_sysroot', '/home/vvdn/LWT_Build/sources/poky/meta/recipes-devtools/gcc/gcc-cross_14.3.bb:do_populate_sysroot', '/home/vvdn/LWT_Build/sources/poky/meta/recipes-devtools/quilt/quilt-native_0.68.bb:do_populate_sysroot', '/home/vvdn/LWT_Build/sources/poky/meta/recipes-kernel/kern-tools/kern-tools-native_git.bb:do_populate_sysroot', 'virtual:native:/home/vvdn/LWT_Build/sources/poky/meta/recipes-core/coreutils/coreutils_9.6.bb:do_populate_sysroot', 'virtual:native:/home/vvdn/LWT_Build/sources/poky/meta/recipes-devtools/bison/bison_3.8.2.bb:do_populate_sysroot', 'virtual:native:/home/vvdn/LWT_Build/sources/poky/meta/recipes-devtools/dwarfsrcfiles/dwarfsrcfiles.bb:do_populate_sysroot', 'virtual:native:/home/vvdn/LWT_Build/sources/poky/meta/recipes-devtools/flex/flex_2.6.4.bb:do_populate_sysroot', 'virtual:native:/home/vvdn/LWT_Build/sources/poky/meta/recipes-devtools/patch/patch_2.7.6.bb:do_populate_sysroot', 'virtual:native:/home/vvdn/LWT_Build/sources/poky/meta/recipes-devtools/pkgconfig/pkgconfig_git.bb:do_populate_sysroot', 'virtual:native:/home/vvdn/LWT_Build/sources/poky/meta/recipes-devtools/pseudo/pseudo_git.bb:do_populate_sysroot', 'virtual:native:/home/vvdn/LWT_Build/sources/poky/meta/recipes-devtools/rpm/rpm_4.20.0.bb:do_populate_sysroot', 'virtual:native:/home/vvdn/LWT_Build/sources/poky/meta/recipes-extended/bc/bc_1.08.1.bb:do_populate_sysroot', 'virtual:native:/home/vvdn/LWT_Build/sources/poky/meta/recipes-kernel/kmod/kmod_34.1.bb:do_populate_sysroot'] NOTE: Installed into sysroot: [] NOTE: Skipping as already exists in sysroot: ['gettext-minimal-native', 'binutils-cross-aarch64', 'cmake-native', 'gcc-cross-aarch64', 'libtool-native', 'm4-native', 'quilt-native', 'texinfo-dummy-native', 'kern-tools-native', 'linux-libc-headers', 'file-native', 'openssl-native', 'coreutils-native', 'expat-native', 'ncurses-native', 'readline-native', 'util-linux-libuuid-native', 'zlib-native', 'bison-native', 'dwarfsrcfiles-native', 'elfutils-native', 'flex-native', 'git-native', 'gnu-config-native', 'json-c-native', 'libedit-native', 'lua-native', 'make-native', 'patch-native', 'perl-native', 'pkgconfig-native', 'pseudo-native', 'python3-native', 'rpm-native', 'bc-native', 'bzip2-native', 'libarchive-native', 'libidn2-native', 'lzlib-native', 'xz-native', 'zstd-native', 'kmod-native', 'acl-native', 'attr-native', 'curl-native', 'gdbm-native', 'gmp-native', 'gnutls-native', 'libtasn1-native', 'libcap-native', 'libffi-native', 'libgcrypt-native', 'libgpg-error-native', 'libmicrohttpd-native', 'libmpc-native', 'libunistring-native', 'mpfr-native', 'nettle-native', 'p11-kit-native', 'popt-native', 'sqlite3-native'] DEBUG: Python function extend_recipe_sysroot finished DEBUG: Executing python function sstate_task_prefunc DEBUG: Python function sstate_task_prefunc finished DEBUG: Executing python function do_package DEBUG: Executing python function package_setup_pkgv DEBUG: Python function package_setup_pkgv finished DEBUG: Executing python function package_convert_pr_autoinc DEBUG: Python function package_convert_pr_autoinc finished DEBUG: Executing python function package_prepare_pkgdata NOTE: Installed into pkgdata-sysroot: [] DEBUG: Python function package_prepare_pkgdata finished DEBUG: Executing python function perform_packagecopy ERROR: Error executing a python function in exec_func_python() autogenerated: The stack trace of python calls that resulted in this exception/failure was: File: 'exec_func_python() autogenerated', lineno: 2, function: 0001: *** 0002:perform_packagecopy(d) 0003: File: '/home/vvdn/LWT_Build/sources/poky/meta/classes-global/package.bbclass', lineno: 363, function: perform_packagecopy 0359: rpath_replace (dvar, d) 0360:} 0361:perform_packagecopy[cleandirs] = "${PKGD}" 0362:perform_packagecopy[dirs] = "${PKGD}" *** 0363: 0364:python populate_packages () { 0365: oe.package.populate_packages(d) 0366:} 0367:populate_packages[dirs] = "${D}" File: '/usr/lib/python3.10/subprocess.py', lineno: 421, function: check_output 0417: else: 0418: empty = b'' 0419: kwargs['input'] = empty 0420: *** 0421: return run(*popenargs, stdout=PIPE, timeout=timeout, check=True, 0422: **kwargs).stdout 0423: 0424: 0425:class CompletedProcess(object): File: '/usr/lib/python3.10/subprocess.py', lineno: 526, function: run 0522: # We don't call process.wait() as .__exit__ does that for us. 0523: raise 0524: retcode = process.poll() 0525: if check and retcode: *** 0526: raise CalledProcessError(retcode, process.args, 0527: output=stdout, stderr=stderr) 0528: return CompletedProcess(process.args, retcode, stdout, stderr) 0529: 0530: Exception: subprocess.CalledProcessError: Command 'tar --exclude=./sysroot-only -cf - -C /home/vvdn/LWT_Build/build/tmp/work/imx8mpevk-poky-linux/linux-imx/6.12.34+git/image -p -S . | tar -xf - -C /home/vvdn/LWT_Build/build/tmp/work/imx8mpevk-poky-linux/linux-imx/6.12.34+git/package' returned non-zero exit status 2. Subprocess output: got *at() syscall for unknown directory, fd 4 unknown base path for fd 4, path lib couldn't allocate absolute path for 'lib'. tar: ./usr/lib: Cannot mkdir: Bad address got *at() syscall for unknown directory, fd 4 unknown base path for fd 4, path lib couldn't allocate absolute path for 'lib'. got *at() syscall for unknown directory, fd 4 unknown base path for fd 4, path lib couldn't allocate absolute path for 'lib'. tar: ./usr/lib: Cannot mkdir: Bad address tar: ./usr/lib/modules: Cannot mkdir: No such file or directory Re: i.MX8MP_EVK: YOCTO Compilation Error do_package() (Issue: tar & *at()) It seems that I don't have the permission to download the attachment. Would you please resend it again? Re: i.MX8MP_EVK: YOCTO Compilation Error do_package() (Issue: tar & *at()) Hi @yipingwang  Awaiting for your prompt support in further debugging. Re: i.MX8MP_EVK: YOCTO Compilation Error do_package() (Issue: tar & *at()) On your ubuntu PC, use the command "sudo apt install tar=1.34+dfsg-1build3" Re: i.MX8MP_EVK: YOCTO Compilation Error do_package() (Issue: tar & *at()) @Sanjiv_MnsDid this resolve the issue ? Re: i.MX8MP_EVK: YOCTO Compilation Error do_package() (Issue: tar & *at()) Hi @abannish  Please try below commands this works for me... wget http://archive.ubuntu.com/ubuntu/pool/main/t/tar/tar_1.34+dfsg-1build3_amd64.deb sudo dpkg -i tar_1.34+dfsg-1build3_amd64.deb  sudo apt-mark hold tar Re: i.MX8MP_EVK: YOCTO Compilation Error do_package() (Issue: tar & *at()) Thanks! That solved the issue also in my side! FYI, everything worked perfectly until some autoupdate from the Ubuntu service...
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Licensing and open-source status for MR-VMU-TROPIC GitHub repository Hello,   I am having a look at the MR-VMU-TROPIC FMU base board. The documentation on GitBook explicitly states: "They are both opensource designs and may be copied and recreated as you wish."   However, the official GitHub repository currently lacks a LICENSE file, despite being described as an "Open-Source FMU base board" also there, which makes it difficult to use or adapt the design files safely.   I noticed there have been recent updates in the repository. Could the team add a standard open-source license file (such as the BSD-3-Clause license used on the TropicCommunityVMU) to the GitHub repository?   Thank you!   Re: Licensing and open-source status for MR-VMU-TROPIC GitHub repository Thank you for highlighting that issue. I will adress that internally. Re: Licensing and open-source status for MR-VMU-TROPIC GitHub repository A license file has been added to the github repo GitHub - NXP-Robotics/MR-VMU-TROPIC: Preview of TROPIC VMU single board RT106X · GitHub https://github.com/NXP-Robotics/MR-VMU-TROPIC/blob/main/LICENSE Thanx again for highlighting that! With kind regards, Gerald
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MR-VMU-TROPIC GitHub 仓库的许可和开源状态 你好,   我正在查看 MR-VMU-TROPIC FMU 底板。GitBook 上的文档明确指出:“它们都是开源设计,您可以随意复制和重新创建。”   然而,尽管官方 GitHub 仓库中也将其描述为“开源 FMU 底板”,但目前却缺少 LICENSE 文件,这使得安全地使用或修改设计文件变得困难。   我注意到代码库最近有更新。团队能否将标准开源许可证文件(例如TropicCommunityVMU上使用的 BSD-3-Clause 许可证)添加到 GitHub 存储库中?   谢谢!   Re: Licensing and open-source status for MR-VMU-TROPIC GitHub repository 感谢您指出这个问题。我会内部处理此事。 Re: Licensing and open-source status for MR-VMU-TROPIC GitHub repository GitHub 仓库中已添加许可证文件:GitHub - NXP-Robotics/MR-VMU-TROPIC:TROPIC VMU 单板 RT106X 预览 · GitHub https://github.com/NXP-Robotics/MR-VMU-TROPIC/blob/main/LICENSE 再次感谢您指出这一点! 此致敬礼, 杰拉尔德
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RT1xxx ENET: Does Correction Counter reset when writing ATCOR to change the Wrap-Around value? Hi, I wonder if the Correction Counter (in the ENET peripheral) is reset upon a write of ATCOR. Or maybe it is reset only if the value in ATCOR is changed? best regards Max i.MXRT 102x i.MXRT 105x
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S32K314 programming error Hello When I tried to write data to the DFLASH using debug mode, it failed. Below is a rough outline of my code. write 0xFFFFF800 to 0x40268350 wtire 0x10000000 to PFCPGM_PEARR_L register write 0xFFFFFFFF to Program DATA0 set MCR[ERS] to 1 MCR[ERS] choose sector Set MCR[EHV] to 1 wait MCRS[DONE] be 1 check MCRS[PEG] set MCR[EHV] to 0 SETMCR[ERS]to 0 after erase 11 sectors wtire 0x10000000 to PFCPGM_PEARR_L register write 256 bit data to DATA0~DATA7 set MCR[PGM] to 1 set MCR[EHV] to 1 read MCRS register get 0x0000C100 But when I looped for the second time wtire 0x10000000 to PFCPGM_PEARR_L register write 256 bit data to DATA0~DATA7 set MCR[PGM] to 1 set MCR[EHV] to 1 read MCRS register get 0x00008100 I'd like to know what might be causing this situation. Lika 回复: S32K314编程错误 To add to that, after confirming that the erase/programming was complete, I took the following steps. set 0 to MCR[EHV] set 0 to MCR[PGM/ERS]
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I.MX95 LVDS clock output can not be changed Hello everyone, Q1: I am working on single port LVDS display in the kernel lf-6.12y. I added my own panel config in driver/gpu/drm/panel/panel-simple.c, but the clock always be around 150Mhz when I was measuring the clock pins. But the other signals were working. But, In the lf-6.18y, the clock can output correctly, and in dual-port mode clock changing is also ok in the both versions. Is it a known problem or my mistake. Because some reasons I hope I can solve this problem in lf-6.12y.  The following are my settings panel-simple.c: static const struct display_timing lt9211_test_timing = { .pixelclock = { 35916000, 35916000, 35916000 }, .hactive = { 280, 280, 280 }, .hfront_porch = { 40, 40, 40, }, .hback_porch = { 60, 60, 60 }, .hsync_len = { 30, 30, 30 }, .vactive = { 1424, 1424, 1424 }, .vfront_porch = { 15, 15, 15 }, .vback_porch = { 17, 17, 17}, .vsync_len = { 4, 4, 4 }, .flags = DISPLAY_FLAGS_DE_HIGH, }; static const struct panel_desc lt9211_test = { .timings = &lt9211_test_timing, .bpc = 8, .num_timings = 1, .size = { .width = 292, .height = 111, }, .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, .bus_flags = DRM_BUS_FLAG_DE_HIGH, .connector_type = DRM_MODE_CONNECTOR_LVDS, }; my lvds config in the device-tree &{/}{     lvds1_panel {         //compatible = "3ascreen,sa123hwv-l51";        compatible = "lt9211_test";        backlight = <&lvds_backlight>;        status = "okay";        port {            panel_in: endpoint {                remote-endpoint = <&lvds1_out>;            };        };     }; Q2: Under some conditions, the LVDS common voltage will not be aligned between the data lanes and clock in the same hardware. Or some signal missing like LVDS1 D3P has signal but D3N doesn't. Do you have ideas why this happened? Could some programs cause this? Q3: Is any config can shift the LVDS clock phase. Thanks Re: I.MX95 LVDS clock output can not be changed Q1: It is likely a known lf-6.12y LVDS clock driver limitation/bug , not your panel-simple.c timing mistake. In single-port LVDS the driver/clock path is likely forcing or rounding to about 148.5/150 MHz . Since lf-6.18y works, the practical fix is to backport the LVDS/LDB clock changes from lf-6.18y to lf-6.12y , or patch the 6.12y LVDS driver/PLL clock table to allow your 35.916 MHz pixel clock. git diff lf-6.12.y..lf-6.18.y -- \ drivers/gpu/drm/bridge/imx/imx95-ldb.c drivers/phy/freescale/phy-fsl-imx8mp-lvds.c drivers/clk/imx/clk-imx95-blk-ctl.c \ arch/arm64/boot/dts/freescale/imx95.dtsi \ arch/arm64/boot/dts/freescale/imx95-*-lvds* Q2: If one LVDS pair side is missing, like D3P has signal but D3N has no signal , that is usually not caused by panel timing . Check: LVDS channel enablement: LVDS0/LVDS1 mismatch fsl,data-width / fsl,data-mapping PHY enablement connector or PCB open/short soldering issue termination/probing method possible damaged LVDS output pin Software can cause wrong channel/lane/data-width setup, but one side of a differential pair missing strongly suggests hardware, pad, routing, termination, or measurement issue . Q3: For i.MX8MP LVDS, there is no normal device-tree config to shift LVDS clock phase . Fix clock frequency/timing/PHY setup instead. Re: I.MX95 LVDS clock output can not be changed Thank you so much. The lvds patch is so helpful.
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SAI padding bits configuration on imx93 I'm having a hard time correctly configuring the sai link between the imx and the codec under linux. The codec is an AK4619, used in 4 channels TDM mode. Playback is ok at 48KHz / 32 bits TDM mode, MSB first and MSB justified. For capture, the AK4619 only supports 24 bits. The data is MSB justified, which means that non significant bits comes after the relevant bits (significative bits are 8-31). On the other side, the sai sets the FBT to 23, which means that the significative bits are 0-23. I tried to find the relevant settings, but could not. I understand that FBT tells where the relevant data starts, but i can't find which register sets the data size (which, in my case, is 24, as opposed to the word size which is 32). What register needs to be set, or what config must be set in the device tree ? Here's the relevant config i actually use : &sai3 { #sound-dai-cells = <0>; clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; assigned-clocks = <&clk IMX93_CLK_SAI3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; assigned-clock-rates = <24576000>; fsl,sai-mclk-direction-output; fsl,sai-asynchronous; status = "okay"; }; simple-audio-card,dai-link { link-name = "AK-4CHANNELS"; format = "i2s"; dai-tdm-slot-num = <4>; dai-tdm-slot-width = <32>; fsl,mclk-equal-bclk; cpu { sound-dai = <&sai3>; dai-tdm-slot-num = <4>; dai-tdm-slot-width = <32>; assigned-clocks = <&clk IMX93_CLK_SAI3>; }; codec { sound-dai = <&ak4619>; system-clock-frequency = <24576000>; assigned-clocks = <&clk IMX93_CLK_SAI3>; dai-tdm-slot-num = <4>; dai-tdm-slot-width = <32>; }; }; I've checked with a scope, and the data on the sai line looks correct. Any hints on this would be really appreciated. Re: SAI padding bits configuration on imx93 Thanks. The problem is that i don't know what to write in this register. The only doc i can find is julienblanc_0-1789720432684.pngjulienblanc_0-1789720432684.png I've highlighted the relevant line in my case. So yes, i should write 0b11111 in FBT, but how do i tell that only 24 bits are relevant ? My understanding is that i cannot use W0W and WNW as they tell the word size, which in my case is 32 bits. In can't find anything relevant in neither of the RCRx registers. Regards, Julien Re: SAI padding bits configuration on imx93 Hello, Did you try to use -f S32_LE with ALSA during recording/playback? This configuration is not done in device tree, if you want to configure it from the driver, you need to modify register TCR5/RCR5 here: https://github.com/nxp-imx/linux-imx/blob/b096ce610e956cc2596006343df8a2a26ed6e019/sound/soc/fsl/fsl_sai.h https://github.com/nxp-imx/linux-imx/blob/b096ce610e956cc2596006343df8a2a26ed6e019/sound/soc/fsl/fsl_sai.c Best regards. Re: SAI padding bits configuration on imx93 Actually, it seems that the extra bits do not cause any issue. I could get audio to work correctly after altering the driver to write the correct value in FBT. Best regards,
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S32平台S32设计工作室v3.4许可证已过期 我的 S32 Design Studio for S32 Platform v3.4 许可证已过期。 请问您能否延长我的激活码的有效期? 产品描述:S32平台S32设计工作室 v3.4 订单号: S32DS-3-4_184061557 许可证总数: 101 激活码: 878E-BE4B-A152-EB7E 谢谢! Re: S32 Design Studio for S32 Platform v3.4 License Expired 你好, 您的S32DS许可证已延期。请使用您之前的激活码重新激活S32DS。
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MRF13750H AWR 型号 你好, 我正在尝试使用贵公司网站上提供的官方设计文件,将 MRF13750H 晶体管模型导入 Cadence AWR Microwave Office。 下载完设计套件和晶体管模型后,尝试打开模型时出现错误。我已附上错误信息的截图。 Luis_V_0-1789581238483.pngLuis_V_0-1789581238483.pngLuis_V_0-1789581238483.png 我已经联系了Cadence的技术支持。他们的团队也尝试下载并打开该模型,并确认遇到了完全相同的问题。 请您核实这些文件,并告知我如何解决这个问题? 最好的, 路易斯·V. 射频 Re: MRF13750H AWR MODEL 你好 Luis_V 再会! 该错误是由于兼容性问题导致的。您尝试安装的模型比较老旧,是为早期版本的 AWR 设计环境设计的。目前尚无计划对其进行更新以适应新版本的软件。 如果您需要使用此型号,最实用的解决方案是安装一个较旧版本的 AWR,例如 2015 年左右的版本(例如 AWR v11 或 v12),该版本与此型号兼容。这样应该可以避免遇到 GetIAwrUserIO DLL 错误。 对于可能由此导致的不便,我们深感抱歉。 希望这些信息对您有所帮助,如果您还需要其他帮助,请告诉我。 祝你今天过得愉快,一切顺利。 Re: MRF13750H AWR MODEL 你好,拉法, 我正在联系 Cadence 公司,看看他们是否可以提供旧版本的 AWR。与此同时,您能否帮我联系一下设计 MRF13750H-915MHz 板的工程师,或者其他可以帮我收集一些数据的人?我这里有NXP的这款产品,我们需要用它。 此外,您之前提到过您可以在您那边打开 ADS/AWR 来查看 T 型接头不连续性、斜接弯头、开路效应等。您能否给我发送一个窗口截图,以便我检查微带线的尺寸和特性?在等待 Cadence 的回复期间,如果您能运行负载牵引分析来找出源阻抗和负载阻抗值,我将不胜感激。 最好的, 路易斯·维拉纽瓦 Re: MRF13750H AWR MODEL 你好 Luis_V 再会! 由于 NXP 已决定(暂时)缩减射频领域的业务,我们该部门的许多同事已经离开了公司,这意味着可用的人员减少了。所以,请告诉我您有什么问题,我会尽力解答;如果我无法解答,我会将此事上报给客户经理寻求支持,但我不能与您分享任何人的联系方式。 感谢您的理解。 祝你今天过得愉快,一切顺利。
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imx93 上的 SAI 填充位配置 我在 Linux 系统下配置 imx 和编解码器之间的 sai 连接时遇到了困难。 编解码器为 AK4619,采用 4 通道 TDM 模式。48KHz / 32 位 TDM 模式下播放正常,MSB 优先且 MSB 对齐。 对于捕获,AK4619 仅支持 24 位。数据采用最高有效位对齐,这意味着非有效位位于相关位之后(有效位为 8-31)。另一方面,sai 将 FBT 设置为 23,这意味着有效位为 0-23。 我尝试查找相关设置,但没有找到。我知道 FBT 指示相关数据的起始位置,但我找不到哪个寄存器设置数据大小(在我的情况下是 24,而不是字长 32)。 需要设置哪个寄存器,或者需要在设备树中设置哪些配置?以下是我实际使用的相关配置: &sai3 { #sound-dai-cells = <0>; clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; assigned-clocks = <&clk IMX93_CLK_SAI3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; assigned-clock-rates = <24576000>; fsl,sai-mclk-direction-output; fsl,sai-asynchronous; status = "okay"; }; simple-audio-card,dai-link { link-name = "AK-4CHANNELS"; format = "i2s"; dai-tdm-slot-num = <4>; dai-tdm-slot-width = <32>; fsl,mclk-equal-bclk; cpu { sound-dai = <&sai3>; dai-tdm-slot-num = <4>; dai-tdm-slot-width = <32>; assigned-clocks = <&clk IMX93_CLK_SAI3>; }; codec { sound-dai = <&ak4619>; system-clock-frequency = <24576000>; assigned-clocks = <&clk IMX93_CLK_SAI3>; dai-tdm-slot-num = <4>; dai-tdm-slot-width = <32>; }; }; 我用示波器检查过了,sai 线上的数据看起来是正确的。 任何提示都将不胜感激。 Re: SAI padding bits configuration on imx93 谢谢。 问题是我不知道该在这个登记簿里写些什么。我能找到的唯一一份文件是 julienblanc_0-1789720432684.pngjulienblanc_0-1789720432684.png 我已将我案例中的相关行高亮显示。所以,是的,我应该在 FBT 中写入 0b11111,但我如何知道只有 24 位是相关的呢?我的理解是,我不能使用 W0W 和 WNW,因为它们表示字长,而我的字长是 32 位。我在两个 RCRx 寄存器中都找不到任何相关信息。 此致, 朱利安 Re: SAI padding bits configuration on imx93 你好, 您在录制/播放时是否尝试过使用 ALSA 的 -f S32_LE 参数? 此配置并非在设备树中完成,如果要通过驱动程序进行配置,则需要在此处修改寄存器 TCR5/RCR5: https://github.com/nxp-imx/linux-imx/blob/b096ce610e956cc2596006343df8a2a26ed6e019/sound/soc/fsl/fsl_sai.h https://github.com/nxp-imx/linux-imx/blob/b096ce610e956cc2596006343df8a2a26ed6e019/sound/soc/fsl/fsl_sai.c 顺祝商祺! Re: SAI padding bits configuration on imx93 实际上,这些额外的部分似乎并没有造成任何问题。修改驱动程序,将正确的值写入 FBT 后,音频就能正常工作了。 顺祝商祺!
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S32 Design Studio for S32 プラットフォーム v3.4 ライセンスが切れました 私のS32 Design Studio for S32 プラットフォーム v3.4のライセンスが期限切れになりました。 私のアクティベーションコードのライセンスを延長してもらえますか? アイテム説明:S32 プラットフォーム v3.4向けS32 Design Studio 注文番号: S32DS-3-4_184061557 ライセンス総数: 101 アクティベーションコード: 878E-BE4B-A152-EB7E よろしくお願いします。 Re: S32 Design Studio for S32 Platform v3.4 License Expired こんにちは、 お客様のS32DSライセンスが延長されました。以前のコードを使用して、S32DSを再度有効化してください。
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NXP i.MX93 EVKのNPU温度と使用率を取得する方法 私はi.MX93 EVKを使っており、Ethos-UのNPU温度と稼働率(負荷)を実行時に監視したいのですが、このデータをどうやって取得できますか? 目的は、AIモデルの推論中にハードウェアパラメータを監視することです。 i.MX8MPlusで以下のパラメータを監視できます。i.MX93でも同様のことを実現したいです。 8Mプラス RAM=$(free -m | awk '/Mem:/ {print $3}') CPU_LOAD=$(vmstat 1 2 | tail -1 | awk '{print 100 - $15}') CPU_TEMP=$(awk '{print $1/1000}' /sys/class/thermal/thermal_zone0/temp 2>/dev/null || echo "N/A") GPU_TEMP=$(awk '{print $1/1000}' /sys/class/thermal/thermal_zone1/temp 2>/dev/null || echo "${CPU_TEMP}") GPU_LOAD=$(cat /sys/kernel/debug/gc/load 2>/dev/null | awk '/load/ {gsub("%","",$3); if (max=="" || $3>max) max=$3} END {if (max!="") print max "%"; else print "N/A"}') i.MX93 RAM=$(free -m | awk '/Mem:/ {print $3}') CPU_LOAD=$(vmstat 1 2 | tail -1 | awk '{print 100 - $15}') CPU_TEMP=$(awk '{print $1/1000}' /sys/class/thermal/thermal_zone0/temp) i.MX93 NPU(ethos-u)のGPU_LOADとGPU_TEMPをどうやって監視できますか? Linux Re: How to get NPU Temperature and utilization for NXP i.MX93 EVK こんにちは、@sonal-acldigital i.MX 8M Plusも i.MX 93も、NPU温度をリアルタイムで監視する方法を提供していません。 - imx8MP、thermal_zone0はCPUの温度を表し、thermal_zone1はSoCの温度を表します。 - imx93、thermal_zone0はCPUの温度を表します。 - NPU、 nputopのようなツールは存在しません。 パフォーマンスチューニングに関する情報については、セクション7.1.2を参照してください。「ハードウェアアクセラレータのプロファイリング」、 MLユーザーガイドに収録。 B.R Re: How to get NPU Temperature and utilization for NXP i.MX93 EVK @pengyong_zhang i.MX 8M Plusとi.MX 93の熱ゾーンについてご説明いただきありがとうございます。以下の点を明確にしていただけますか? i.MX8MPLUS 1. GPU温度: 個別のGPU温度を読み取る専用のシステムパス(/sys/class/thermal/thermal/thermal_zoneX/temp)はありますか?それともソックサーマルゾーン(thermal_zone1)だけでカバーされているのでしょうか? 2. GPU負荷: /sys/kernel/debug/gc/loadを読み込むことがGPU負荷の確認の標準的な方法ですか?それともMLユーザーガイドのセクション7.1.2に詳述されている手順も必要ですか? i.MX93: NPUの負荷と温度を監視するネイティブツール(nputopなど)がないため、次の点について質問させてください。推論の実行をNPUにオフロードした場合とCPUのみで実行した場合のCPU負荷の減少を測定することで、相対的なNPU使用率を導き出すことは妥当でしょうか? もしこの方法が推奨されていない場合、推論実行中のNPU活動を推定するために使える代替のドライバーノードやパフォーマンスカウンターはありますか? Re: How to get NPU Temperature and utilization for NXP i.MX93 EVK こんにちは、@sonal-acldigital 返信が遅くなり申し訳ありません。最近、ひどいウイルス性の風邪にかかり、しばらくの間高熱が続きました。今日やっと熱が下がった。 1.GPU温度を読み取る専用の経路はありません。 2. はい、/sys/kernel/debug/gc/loadによるGPU負荷監視が現在の方法です。 IMX93: NPU使用率は、プロファイリングを用いてご自身で計算する必要があります。 B.R
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I.MX95 LVDS 时钟输出无法更改 大家好, 问题1: 我正在内核 lf-6.12y 中开发单端口 LVDS 显示功能。我在 driver/gpu/drm/panel/panel-simple.c 中添加了自己的面板配置,但是当我测量时钟引脚时,时钟频率始终在 150Mhz 左右。但其他信号都正常。 但是,在 lf-6.18y 中,时钟可以正确输出,并且在双端口模式下,两个版本的时钟切换也都可以。这是已知问题还是我的操作失误?由于某些原因,我希望能在lf-6.12y版本中解决这个问题。 以下是我的设置 panel-simple.c: static const struct display_timing lt9211_test_timing = { 像素时钟= { 35916000, 35916000, 35916000 }, .hactive= { 280, 280, 280 }, .hfront_porch= { 40, 40, 40, }, .hback_porch= { 60, 60, 60 }, .hsync_len= { 30, 30, 30 }, .vactive= { 1424, 1424, 1424 }, .vfront_porch= { 15, 15, 15 }, .vback_porch= { 17, 17, 17}, .vsync_len= { 4, 4, 4 }, .flags= DISPLAY_FLAGS_DE_HIGH, }; static const struct panel_desc lt9211_test = { 时间= &lt9211_test_timing, .bpc= 8, .num_timings= 1, 。尺寸= { 。宽度= 292, 。高度= 111, }, .bus_format= MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, .bus_flags= DRM_BUS_FLAG_DE_HIGH, .连接器类型= DRM_MODE_CONNECTOR_LVDS, }; 设备树中的 lvds 配置 &{/}{ lvds1_panel { //兼容 = "3ascreen,sa123hwv-l51"; 兼容 = "lt9211_test"; 背光 = <&lvds_backlight>; 状态 = "正常"; 港口 { panel_in: 端点 { 远程端点 = <&lvds1_out>; }; }; }; Q2: 在某些情况下,同一硬件中的数据通道和时钟之间的 LVDS 公共电压将无法对齐。或者某些信号缺失,例如 LVDS1 D3P 有信号但 D3N 没有信号。你知道这是为什么吗?某些程序会导致这种情况吗? Q3: 是否有任何配置可以改变LVDS时钟相位? 谢谢! Re: I.MX95 LVDS clock output can not be changed 问题1:这很可能是LF-6.12Y LVDS时钟驱动程序的一个已知限制/错误,而不是你的panel-simple.c文件的问题。时机把握失误。在单端口LVDS中,驱动/时钟路径很可能强制或四舍五入到大约148.5/150。MHz。由于 lf-6.18y 可以正常工作,实际的解决方法是将 lf-6.18y 的 LVDS/LDB 时钟更改向后移植到 lf-6.12y,或者修补 6.12y LVDS 驱动程序/PLL 时钟表,以允许使用您的 35.916 MHz 像素时钟。 git diff lf-6.12.y..lf-6.18.y -- \ drivers/gpu/drm/bridge/imx/imx95-ldb.c drivers/phy/freescale/phy-fsl-imx8mp-lvds.c drivers/clk/imx/clk-imx95-blk-ctl.c \ arch/arm64/boot/dts/freescale/imx95.dtsi \ arch/arm64/boot/dts/freescale/imx95-*-lvds* Q2:如果 LVDS 对中的一侧缺失,例如 D3P 有信号但 D3N 没有信号,这通常不是面板时序造成的。查看: LVDS通道启用:LVDS0/LVDS1不匹配 fsl,数据宽度 / fsl,数据映射 PHY 使能 连接器或PCB开路/短路 焊接问题 终止/探测方法 LVDS 输出引脚可能损坏 软件可能会导致错误的通道/线路/数据宽度设置,但差分对的一侧缺失强烈表明存在硬件、焊盘、布线、端接或测量问题。 Q3:对于 i.MX8MP LVDS,没有常规的设备树配置来改变 LVDS 时钟相位。改为修复时钟频率/时序/PHY设置。 Re: I.MX95 LVDS clock output can not be changed 太感谢了。 lvds补丁太有用了。
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MRF13750H AWR MODEL Hello, I am trying to import the MRF13750H transistor model into Cadence AWR Microwave Office using the official design files provided on your website. After downloading both the design kit and the transistor model an error is generated when attempting to open the model. I have attached a screenshot of the error message. Luis_V_0-1789581238483.pngLuis_V_0-1789581238483.pngLuis_V_0-1789581238483.png I have already contacted technical support at cadence. Their team attempted to download and open the model as well, and they confirmed that they encountered the exact same issue. Could you please verify these files and let me know how to resolve this? Best, Luis V. RF Re: MRF13750H AWR MODEL Hello Luis_V Good day! The error is due to compatibility issues. The model you are trying to install is quite old and was designed for earlier versions of AWR Design Environment. Currently, there are no plans to update it for newer versions of the software. If you need to use this model, the most practical solution is to install an older version of AWR, such as one from around 2015 (for example, AWR v11 or v12), which is compatible with this model. This should allow you to work without encountering the GetIAwrUserIO DLL error. We apologize for any inconvenience this may cause. I hope this information has helped you, please let me know if you need help with anything else. Have a great day and best of luck. Re: MRF13750H AWR MODEL Hello Rafa, I am reaching out to Cadence to see if they can provide an older version of AWR. In the meantime, could you connect me with the engineer who designed the MRF13750H-915MHz Board or someone who can help me gather some numbers? I have this product from NXP and we need to use it. Additionally, you mentioned earlier that you could open ADS/AWR on your end to view the tee-discontinuities, mitered bends, open-end effects, etc. Would you be able to send me a screenshot of the window so I can check the microstrip dimensions and characteristics? I would also appreciate if you could run a load-pull analysis to find the source and load impedance values while I wait on Cadence. Best, Luis Villanueva Re: MRF13750H AWR MODEL Hello Luis_V Good day! Since NXP has decided to ramp down operations in the RF area (for the moment), many of our colleagues from that department have left the company, meaning there are fewer people available. So, please let me know what questions you have, and I will try to answer them; if I can't, I will escalate the matter to get support from an AE, though I cannot share anyone's contact details with you. Thanks for your understanding. Have a great day and best of luck.
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RT1xxx ENET:写入 ATCOR 以更改循环值时,校正计数器是否会重置? 您好, 我想知道在写入 ATCOR 时,校正计数器(在 ENET 外设中)是否会重置。 或者,也许只有当 ATCOR 中的值发生变化时才会重置? 顺祝商祺! 最大值 i.MX RT102x i.MX RT105x
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How to get NPU Temperature and utilization for NXP i.MX93 EVK I am using i.MX93 EVK and want to monitor the Ethos-U NPU temperature & utilization(load) at runtime how can I get this data ? The agenda is to monitor the HW-parameters during the inference of AI-models. I could monitor the below parameters using i.MX8MPlus I want to achieve the similar for i.MX93. 8MPlus RAM=$(free -m | awk '/Mem:/ {print $3}') CPU_LOAD=$(vmstat 1 2 | tail -1 | awk '{print 100 - $15}') CPU_TEMP=$(awk '{print $1/1000}' /sys/class/thermal/thermal_zone0/temp 2>/dev/null || echo "N/A") GPU_TEMP=$(awk '{print $1/1000}' /sys/class/thermal/thermal_zone1/temp 2>/dev/null || echo "${CPU_TEMP}") GPU_LOAD=$(cat /sys/kernel/debug/gc/load 2>/dev/null | awk '/load/ {gsub("%","",$3); if (max=="" || $3>max) max=$3} END {if (max!="") print max "%"; else print "N/A"}') I.mx93 RAM=$(free -m | awk '/Mem:/ {print $3}') CPU_LOAD=$(vmstat 1 2 | tail -1 | awk '{print 100 - $15}') CPU_TEMP=$(awk '{print $1/1000}' /sys/class/thermal/thermal_zone0/temp) How can I monitor the GPU_LOAD & GPU_TEMP for i.MX93 npu(ethos-u) ? Linux Re: How to get NPU Temperature and utilization for NXP i.MX93 EVK Hi @sonal-acldigital  Neither the i.MX 8M Plus nor the i.MX 93 offers a method to monitor NPU temperature in real time. - imx8MP, thermal_zone0 represents the cpu-thermal temperature ,thermal_zone1 represents the soc-thermal temperature. - imx93, thermal_zone0 represents the cpu-thermal temperature. - NPU, There is no such tool like nputop. For information on performance tuning, please refer to Section 7.1.2, "Profiling for Hardware Accelerators," in the ML User Guide. B.R Re: How to get NPU Temperature and utilization for NXP i.MX93 EVK @pengyong_zhang Thanks for clarifying the thermal zones for the i.MX 8M Plus and i.MX 93. Could you please clarify the following: i.MX8MPLUS 1. GPU Temperature: Is there a dedicated system path (like /sys/class/thermal/thermal_zoneX/temp) to read individual GPU temperatures, or is it covered solely under the soc-thermal zone (thermal_zone1)? 2. GPU Load: Is reading /sys/kernel/debug/gc/load the standard method for checking GPU load, or is the process detailed in Section 7.1.2 of the ML User Guide required for this as well? i.MX93: Since there is no native tool (like nputop) to monitor NPU load and temperature, we would like to ask: Is it valid to derive relative NPU utilization by measuring the reduction in CPU load when offloading inference execution to the NPU vs. running on the CPU alone? If this method isn't recommended, is there any alternative driver node or performance counter we can use to estimate NPU activity during an inference run? Re: How to get NPU Temperature and utilization for NXP i.MX93 EVK Hi @sonal-acldigital  Sorry for the late reply. I recently had a severe viral cold and had a high fever for a while. The fever just broke today. 1. There is no dedicated path to read the GPU temperature. 2. Yes, GPU load monitoring via /sys/kernel/debug/gc/load is the current method. IMX93: You need to calculate the NPU utilization yourself using profiling. B.R
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如何获取 NXP i.MX93 EVK 的 NPU 温度和利用率 我正在使用 i.MX93 EVK,想要监控 Ethos-U NPU 在运行时的温度和利用率(负载),请问如何获取这些数据? 本次议程旨在监测人工智能模型推理过程中的硬件参数。 我可以使用 i.MX8MPlus 监测以下参数,我想在 i.MX93 中实现类似的功能。 8MPlus RAM=$(free -m | awk '/Mem:/ {print $3}') CPU_LOAD=$(vmstat 1 2 | tail -1 | awk '{print 100 - $15}') CPU_TEMP=$(awk '{print $1/1000}' /sys/class/thermal/thermal_zone0/temp 2>/dev/null || echo "N/A") GPU_TEMP=$(awk '{print $1/1000}' /sys/class/thermal/thermal_zone1/temp 2>/dev/null || echo "${CPU_TEMP}") GPU_LOAD=$(cat /sys/kernel/debug/gc/load 2>/dev/null | awk '/load/ {gsub("%", "$3"); if (max== || $3>max) max=$3} END {if (max!=) print max "%"; else print "N/A"}') i.MX 93 RAM=$(free -m | awk '/Mem:/ {print $3}') CPU_LOAD=$(vmstat 1 2 | tail -1 | awk '{print 100 - $15}') CPU_TEMP=$(awk '{print $1/1000}' /sys/class/thermal/thermal_zone0/temp) 如何监测 i.MX93 npu(ethos-u) 的 GPU_LOAD 和 GPU_TEMP? Linux Re: How to get NPU Temperature and utilization for NXP i.MX93 EVK 你好@sonal-acldigital i.MX 8M Plus 和 i.MX 93 都没有提供实时监测 NPU 温度的方法。 - imx8MP,thermal_zone0 表示 CPU 温度,thermal_zone1 表示 SoC 温度。 - imx93,thermal_zone0 表示 CPU 温度。 - NPU,没有像 nputop 这样的工具。 有关性能调优的信息,请参阅第 7.1.2 节。《机器学习用户指南》中的“硬件加速器性能分析”。 B.R Re: How to get NPU Temperature and utilization for NXP i.MX93 EVK @pengyong_zhang感谢您澄清 i.MX 8M Plus 和 i.MX 93 的热区划分。请您澄清以下问题: i.MX8MPLUS 1. GPU 温度:是否有专门的系统路径(如 /sys/class/thermal/thermal_zoneX/temp)来读取单个 GPU 温度,还是仅包含在 soc-thermal 区域(thermal_zone1)中? 2. GPU 负载:读取 /sys/kernel/debug/gc/load 是检查 GPU 负载的标准方法吗?还是也需要按照 ML 用户指南第 7.1.2 节中详述的过程进行检查? i.MX93: 由于没有像 nputop 这样的原生工具来监测 NPU 负载和温度,我们想问:将推理执行卸载到 NPU 与单独在 CPU 上运行相比,通过测量 CPU 负载的减少量来推导出相对 NPU 利用率是否有效? 如果这种方法不推荐,是否有其他驱动节点或性能计数器可以用来估算推理运行期间的 NPU 活动? Re: How to get NPU Temperature and utilization for NXP i.MX93 EVK 你好@sonal-acldigital 抱歉回复晚了。我前段时间得了重感冒,还持续高烧了一段时间。今天刚退烧。 1.没有专用的路径来读取GPU温度。 2. 是的,目前通过 /sys/kernel/debug/gc/load 进行 GPU 负载监控的方法就是如此。 IMX93: 您需要使用性能分析自行计算 NPU 利用率。 B.R
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I.MX95 LVDSクロック出力は変更できません こんにちは、みんな、 Q1: カーネルのlf-6.12yでシングルポートのLVDSディスプレイを作っています。ドライバ/GPU/drm/panel/panel-simple.cで自分でパネル設定を追加しましたが、クロックピンを測定しているときはいつも150MHz前後でした。しかし、他の信号は正常に機能していた。 しかし、lf-6.18yではクロック出力は正しくでき、デュアルポートモードではクロック変更も両バージョンで問題ありません。これは既知の問題でしょうか、それとも私のミスでしょうか?なぜなら、いくつかの理由でこの問題をlf-6.12yで解決できればと思っているからです。 以下は私の設定です panel-simple.c: static const struct display_timing lt9211_test_timing = { .pixelclock= { 35916000, 35916000, 35916000 }, .hactive= { 280, 280, 280 }, .hfront_porch= { 40, 40, 40, }, .hback_porch= { 60, 60, 60 }, .hsync_len= { 30, 30, 30 }, .vactive= { 1424, 1424, 1424 }, .vfront_porch= { 15, 15, 15 }, .vback_porch= { 17, 17, 17}, .vsync_len= { 4, 4, 4 }, .フラグ= DISPLAY_FLAGS_DE_HIGH、 }; static const struct panel_desc lt9211_test = { タイミング= &lt9211_test_timing、 .bpc= 8、 .num_timings= 1、 。サイズ= { 。幅= 292、 。身長= 111、 }、 .bus_format= MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA、 .bus_flags= DRM_BUS_FLAG_DE_HIGH、 .connector_type= DRM_MODE_CONNECTOR_LVDS、 }; デバイスツリー内の私の lvds 設定 &{/}{ lvds1_panel { //compatible = "3ascreen,sa123hwv-l51"; compatible = "lt9211_test"; バックライト = <&lvds_backlight>; ステータス = "正常"; ポート { panel_in: エンドポイント { リモートエンドポイント = <&lvds1_out>; }; }; }; Q2: 特定の条件下では、同じハードウェア内でデータレーンとクロック間でLVDSの共通電圧が整列しないこともあります。あるいは、LVDS1のD3Pには信号があるがD3Nには信号がないなど、何らかの信号が欠落している場合もある。なぜこうなったのか、何かアイデアはありますか?一部のプログラムがこれを引き起こす可能性はありますか? Q3: どんな設定でもLVDSのクロック位相をシフトできますか? よろしくお願いします。 Re: I.MX95 LVDS clock output can not be changed Q1: これはおそらくあなたのパネルではなく、既知のlf-6.12y LVDSクロックドライバーの制限やバグである可能性が高いです。タイミングのミス。シングルポートのLVDSでは、ドライバ/クロック経路が約148.5/150に強制または丸められている可能性が高いですMHzlf-6.18yが動作するため、実用的な解決策はLVDS/LDBクロックの変更をlf-6.18yからlf-6.12yにバックポートするか、6.12y LVDSドライバー/PLLクロックテーブルをパッチして35.916 MHzピクセルクロックを可能にすることです。 git diff lf-6.12.y..lf-6.18.y -- \ ドライバ/GPU/DRM/ブリッジ/IMX/IMX95-LDB.C ドライバ/phy/freescale/phy-fsl-imx8mp-lvds.c ドライバ/clk/imx/clk-imx95-blk-ctl.c \ arch/arm64/boot/dts/freescale/imx95.dtsi \ arch/arm64/boot/dts/freescale/imx95-*-lvds* Q2: 例えばD3Pには信号があるのにD3Nに信号がない場合、通常はパネルタイミングが原因ではありません。チェック: LVDSチャネルのイネーブルメント:LVDS0/LVDS1のミスマッチ fsl、データ幅 / fsl、データマッピング PHYイネーブルメント コネクタまたは基板の断線/短絡 はんだ付けの問題 終端/プロービング方法 LVDS出力ピンが損傷している可能性があります ソフトウェアが誤ったチャネル/レーン/データ幅設定を引き起こすことがありますが、差動ペアの片側が欠けているとハードウェア、パッド、ルーティング、終端、または測定の問題を強く示唆しています。 Q3: i.MX8MP LVDSの場合、LVDSのクロック位相をシフトするための通常のデバイスツリー構成はありません。クロック周波数、タイミング、PHY設定を修正してください。 Re: I.MX95 LVDS clock output can not be changed 本当にありがとうございます。 LVDSパッチはとても役に立ちます。
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PN7160 NXP-NCI MCUxpresso for VS Code Example Project for MCXA156 Introduction This document provides a guide on how to integrate the FRDM-MCXA156 as a host for the PN7160 using the examples provided in the “PN7160 NXP-NCI MCUXpresso Example Project” package. The hardware required to follow this guide is: FRDM-MCXA156 development board as host MCU. OM27160A1/OM27160B1 (PN7160 EVK) as the NFC controller. MCUxpresso for VS code extension Software setup. PN7160 NXP-NCI MCUXpresso Example Project version: 1.2 MCXN947 SDK version: 26.06 PN7160 version: 12.50.11. Hardware connections. When using OM27160B1 (SPI Host Interface): The FRDM-MCXA156 schematic document is available on this page. In the case of SPI connections, to use PN7160 directly with the Arduino headers a rework is needed for the FRDM because SDO(MOSI) and SS (Chip select) are not connected as default (as shown in the next figure). You should move R59 and R60 from pad 2 to pad 3 to enable these connections. Habib_MS_0-1781809327131.png Note: You can connect the SPI pins available in Mikro bus header with jumpers, but in this example, the signals are routed through the pins enabled by the rework configuration. Once clarified this, these are the pins used in this example. Name PORT I2C0_SDA P0_16 I2C0_SCL P0_17 LPSPI1_SDI P2_16 LPSPI1_SDO P2_13 LPSPI1_SCK P2_12 LPSPI1_SS P2_6 IRQ P1_15 VEN P1_14 REQ P3_16   Software Changes This section describes the software changes required to run an “NXP-NCI2.0” example with the MCXA156, which consists in a detection loop that displays in a terminal information (like UID, SAK, and Product Type for MIFARE product-based cards) about any tag detected by the PN7160. To begin the integration, we first need to import a hello_world project from the FRDM-MCXA156 SDK (v26.06.00) into MCUXpresso IDE for VS Code. For this purpose, download and install the FRDM-MCXA156 repository (version 26.06) using the extension available in the Quickstart panel by selecting Import Repository. For more information about this process, you can consult the corresponding guide. Importing NCI2.0 examples Download the “PN7160 NXP-NCI MCUXpresso Example Project” zip from the product page and extract in a known folder. This will be useful for later use.  Importing base project 1. In the Quick Start panel click on “Import Example from Repository” in VS code. Habib_MS_1-1781809359168.png 2. Select “FRDM-MCXA156” in board setting.   Habib_MS_1-1785802139304.png 3. In the template will search for the “hello_world” example, select Freestanding Applications, chose the location and click on “import”. Habib_MS_0-1785802110562.png Importing SDK drivers Once the project is added to the workspace we will need to add the required drivers, which are the SPI driver in case the OM27160B1HN is being used, or the I2C driver if the OM27160A1HN is being used. For this we need to add the following code in the prj.cfg file. Habib_MS_0-1781809845396.png Spoiler (Highlight to read) CONFIG_MCUX_COMPONENT_driver.lpi2c=y CONFIG_MCUX_COMPONENT_driver.lpspi=y CONFIG_MCUX_COMPONENT_driver.lpi2c=y CONFIG_MCUX_COMPONENT_driver.lpspi=y Add the example source code to the newly created MCXA156 project Delete the hello_world.c of the project files folder of the MCXA156 project. From the “NXP-NCI2.0_iMXRT1170_examples” extracted just drag and drop in the project files folder the following files and folders. Habib_MS_0-1781809900813.png Habib_MS_1-1781809927413.png When you drag and drop a file into VS code a window will appear asking whether you want to link the file or copy it. Please select “Copy files.” Habib_MS_2-1781809983781.png The project folder should look like this: Habib_MS_3-1781810001861.png After dragging and dropping all the files, the CMakeLists.txt file is automatically updated to include all the copied .c files. An example of this is shown below: Habib_MS_4-1781810063910.png However, .h files are not automatically linked, so they must be added manually. Please copy and paste the following includes into the CMakeLists.txt file: Habib_MS_5-1781810096008.png Spoiler (Highlight to read) mcux_add_include( BASE_PATH ${CMAKE_CURRENT_LIST_DIR} INCLUDES tool TML NfcLibrary/inc NfcLibrary/NdefLibrary/inc INCLUDES NfcLibrary/NxpNci20/inc . ) mcux_add_include( BASE_PATH ${CMAKE_CURRENT_LIST_DIR} INCLUDES tool TML NfcLibrary/inc NfcLibrary/NdefLibrary/inc INCLUDES NfcLibrary/NxpNci20/inc . ) Preprocessor Interface macro Depending on the interface to be used to communicate with the PN7160, a preprocessor macro must be defined in the CMakelist.txt BOARD_NXPNCI_INTERFACE_SPI (For using SPI with OM27160B1) BOARD_NXPNCI_INTERFACE_I2C (For using I2C with OM27160A1) Additionally, it is necessary to add the macro called REMOVE_P2P_SUPPORT. Please make sure that this Macro is included. Spoiler (Highlight to read) mcux_add_macro( CC "BOARD_NXPNCI_INTERFACE_I2C=1\ REMOVE_P2P_SUPPORT=1") mcux_add_macro( CC "BOARD_NXPNCI_INTERFACE_I2C=1\ REMOVE_P2P_SUPPORT=1") Note: The following sections are exemplified using the SPI interface (BOARD_NXPNCI_INTERFACE_SPI macro). After making the modifications described below, the interface used by the example can be changed simply by setting the macro to BOARD_NXPNCI_INTERFACE_I2C. Board definitions In the board.h file we will add the following definitions in order to refer to the different peripherals and clocks to be used, you can find this file in the following path: {PrjRootDirPath}\ frdmmcxa156\frdmmcxa156\board.h Habib_MS_1-1781810404448.png Spoiler (Highlight to read) #ifdef BOARD_NXPNCI_INTERFACE_I2C #define BOARD_NXPNCI_I2C_CLOCK (CLOCK_GetLpi2cClkFreq(0U)) #define BOARD_NXPNCI_I2C_INSTANCE (LPI2C0) #define BOARD_NXPNCI_I2C_BAUDRATE (100000) #define BOARD_NXPNCI_I2C_ADDR (0x28) #endif #ifdef BOARD_NXPNCI_INTERFACE_SPI #define BOARD_NXPNCI_SPI_CLOCK (CLOCK_GetLpspiClkFreq(1U)) #define BOARD_NXPNCI_SPI_INSTANCE (LPSPI1) #define BOARD_NXPNCI_SPI_BAUDRATE (400000) #endif #define BOARD_NXPNCI_IRQ_PORT (GPIO1) #define BOARD_NXPNCI_VEN_PORT (GPIO1) #define BOARD_NXPNCI_DWL_PORT (GPIO3) #define BOARD_NXPNCI_IRQ_PIN (15U) #define BOARD_NXPNCI_VEN_PIN (14U) #define BOARD_NXPNCI_DWL_PIN (16U) #ifdef BOARD_NXPNCI_INTERFACE_I2C #define BOARD_NXPNCI_I2C_CLOCK (CLOCK_GetLpi2cClkFreq(0U)) #define BOARD_NXPNCI_I2C_INSTANCE (LPI2C0) #define BOARD_NXPNCI_I2C_BAUDRATE (100000) #define BOARD_NXPNCI_I2C_ADDR (0x28) #endif #ifdef BOARD_NXPNCI_INTERFACE_SPI #define BOARD_NXPNCI_SPI_CLOCK (CLOCK_GetLpspiClkFreq(1U)) #define BOARD_NXPNCI_SPI_INSTANCE (LPSPI1) #define BOARD_NXPNCI_SPI_BAUDRATE (400000) #endif #define BOARD_NXPNCI_IRQ_PORT (GPIO1) #define BOARD_NXPNCI_VEN_PORT (GPIO1) #define BOARD_NXPNCI_DWL_PORT (GPIO3) #define BOARD_NXPNCI_IRQ_PIN (15U) #define BOARD_NXPNCI_VEN_PIN (14U) #define BOARD_NXPNCI_DWL_PIN (16U) Code modifications to the TML component In the source tml.c source file the following modifications are made, you can find this file in the following path: {{PrjRootDirPath }>frdmmcxa156_hello_world\TML Habib_MS_2-1781810455046.png Spoiler (Highlight to read) static Status tml_Reset(void) { /* Set DWL_REQ low for NCI protocol */ GPIO_PortClear(BOARD_NXPNCI_DWL_PORT, 1U << BOARD_NXPNCI_DWL_PIN); GPIO_PortClear(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); Sleep(10); GPIO_PortSet(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); Sleep(10); return SUCCESS; } static Status tml_Reset(void) { /* Set DWL_REQ low for NCI protocol */ GPIO_PortClear(BOARD_NXPNCI_DWL_PORT, 1U << BOARD_NXPNCI_DWL_PIN); GPIO_PortClear(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); Sleep(10); GPIO_PortSet(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); Sleep(10); return SUCCESS; } Habib_MS_3-1781810501153.png Spoiler (Highlight to read) static void INTF_INIT(void) { lpspi_master_config_t masterConfig; LPSPI_MasterGetDefaultConfig(&masterConfig); masterConfig.baudRate = BOARD_NXPNCI_SPI_BAUDRATE; masterConfig.whichPcs = (lpspi_which_pcs_t) kLPSPI_Pcs1; masterXfer.configFlags = kLPSPI_MasterPcs1 | kLPSPI_MasterPcsContinuous | kLPSPI_MasterByteSwap; LPSPI_MasterInit(BOARD_NXPNCI_SPI_INSTANCE, &masterConfig, BOARD_NXPNCI_SPI_CLOCK); } static void INTF_INIT(void) { lpspi_master_config_t masterConfig; LPSPI_MasterGetDefaultConfig(&masterConfig); masterConfig.baudRate = BOARD_NXPNCI_SPI_BAUDRATE; masterConfig.whichPcs = (lpspi_which_pcs_t) kLPSPI_Pcs1; masterXfer.configFlags = kLPSPI_MasterPcs1 | kLPSPI_MasterPcsContinuous | kLPSPI_MasterByteSwap; LPSPI_MasterInit(BOARD_NXPNCI_SPI_INSTANCE, &masterConfig, BOARD_NXPNCI_SPI_CLOCK); } Habib_MS_4-1781810544149.png Spoiler (Highlight to read) static Status tml_Init(void) { gpio_pin_config_t in_config = {kGPIO_DigitalInput, 0}; gpio_pin_config_t out_config = {kGPIO_DigitalOutput, 0}; GPIO_PinInit(BOARD_NXPNCI_IRQ_PORT, BOARD_NXPNCI_IRQ_PIN, &in_config); GPIO_PinInit(BOARD_NXPNCI_VEN_PORT, BOARD_NXPNCI_VEN_PIN, &out_config); GPIO_PinInit(BOARD_NXPNCI_DWL_PORT, BOARD_NXPNCI_DWL_PIN, &out_config); INTF_INIT(); return SUCCESS; } static Status tml_DeInit(void) { GPIO_PortClear(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); return SUCCESS; } static Status tml_Init(void) { gpio_pin_config_t in_config = {kGPIO_DigitalInput, 0}; gpio_pin_config_t out_config = {kGPIO_DigitalOutput, 0}; GPIO_PinInit(BOARD_NXPNCI_IRQ_PORT, BOARD_NXPNCI_IRQ_PIN, &in_config); GPIO_PinInit(BOARD_NXPNCI_VEN_PORT, BOARD_NXPNCI_VEN_PIN, &out_config); GPIO_PinInit(BOARD_NXPNCI_DWL_PORT, BOARD_NXPNCI_DWL_PIN, &out_config); INTF_INIT(); return SUCCESS; } static Status tml_DeInit(void) { GPIO_PortClear(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); return SUCCESS; } Code modifications for ports, pins and clocks initialization In the file “hardware_init.c” in the board folder of the project, write the following function as shown, in order to add port and clock peripheral initializations. Habib_MS_5-1781810589344.png Spoiler (Highlight to read) /* * Copyright 2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*${header:start}*/ #include "pin_mux.h" #include "fsl_clock.h" #include "fsl_reset.h" #include "board.h" #include /*${header:end}*/ /*${function:start}*/ void BOARD_InitHardware(void) { CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); CLOCK_AttachClk(kFRO12M_to_LPI2C0); CLOCK_SetClockDiv(kCLOCK_DivLPSPI1, 1u); CLOCK_AttachClk(kFRO12M_to_LPSPI1); BOARD_InitPins(); BOARD_InitBootClocks(); BOARD_InitDebugConsole(); } /*${function:end}*/ /* * Copyright 2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*${header:start}*/ #include "pin_mux.h" #include "fsl_clock.h" #include "fsl_reset.h" #include "board.h" #include /*${header:end}*/ /*${function:start}*/ void BOARD_InitHardware(void) { CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); CLOCK_AttachClk(kFRO12M_to_LPI2C0); CLOCK_SetClockDiv(kCLOCK_DivLPSPI1, 1u); CLOCK_AttachClk(kFRO12M_to_LPSPI1); BOARD_InitPins(); BOARD_InitBootClocks(); BOARD_InitDebugConsole(); } /*${function:end}*/ In the pin_mux.c file modifies the function called BOARD_InitPins(); accordingly, this file can be seen in the following path: {PrjRootDirPath}\ frdmmcxa156\hello_world \pin_mux.c Spoiler (Highlight to read) void BOARD_InitPins(void) { CLOCK_EnableClock(kCLOCK_GateGPIO1); /* GPIO3: Peripheral clock is enabled */ CLOCK_EnableClock(kCLOCK_GateGPIO3); /* PORT0: Peripheral clock is enabled */ CLOCK_EnableClock(kCLOCK_GatePORT0); CLOCK_EnableClock(kCLOCK_GatePORT1); CLOCK_EnableClock(kCLOCK_GatePORT2); CLOCK_EnableClock(kCLOCK_GatePORT3); /* GPIO1 peripheral is released from reset */ RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn); /* GPIO3 peripheral is released from reset */ RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kLPSPI0_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kLPSPI1_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn); const port_pin_config_t port0_2_pin78_config = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Low internal pull resistor value is selected. */ kPORT_LowPullResistor, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive input filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain output is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Normal drive strength is configured */ kPORT_NormalDriveStrength, /* Pin is configured as LPUART0_RXD */ kPORT_MuxAlt2, /* Digital input enabled */ kPORT_InputBufferEnable, /* Digital input is not inverted */ kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORT0_2 (pin 78) is configured as LPUART0_RXD */ PORT_SetPinConfig(PORT0, 2U, &port0_2_pin78_config); const port_pin_config_t port0_3_pin79_config = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Low internal pull resistor value is selected. */ kPORT_LowPullResistor, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive input filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain output is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Normal drive strength is configured */ kPORT_NormalDriveStrength, /* Pin is configured as LPUART0_TXD */ kPORT_MuxAlt2, /* Digital input enabled */ kPORT_InputBufferEnable, /* Digital input is not inverted */ kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORT0_3 (pin 79) is configured as LPUART0_TXD */ PORT_SetPinConfig(PORT0, 3U, &port0_3_pin79_config); const port_pin_config_t port2_13_pin35_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_SDO */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 13U, &port2_13_pin35_config); const port_pin_config_t port2_12_pin34_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_SCK */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 12U, &port2_12_pin34_config); const port_pin_config_t port2_16_pin37_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_SDI */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 16U, &port2_16_pin37_config); const port_pin_config_t port2_6_pin28_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_PCS0 */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 6U, &port2_6_pin28_config); const port_pin_config_t port1_15_pin8_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as GPIO1 15 */ kPORT_MuxAlt0, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT1, 15U, &port1_15_pin8_config); const port_pin_config_t port1_14_pin7_config = { kPORT_PullUp, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as GPIO1 14 */ kPORT_MuxAlt0, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT1, 14U, &port1_14_pin7_config); const port_pin_config_t port3_16_pin59_config = { kPORT_PullUp, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as GPIO3 16 */ kPORT_MuxAlt0, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT3, 16U, &port3_16_pin59_config); const port_pin_config_t port0_16_pin83_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPI2C0 SDA */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT0, 16U, &port0_16_pin83_config); const port_pin_config_t port0_17_pin84_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPI2C0 SCL */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT0, 17U, &port0_17_pin84_config); } void BOARD_InitPins(void) { CLOCK_EnableClock(kCLOCK_GateGPIO1); /* GPIO3: Peripheral clock is enabled */ CLOCK_EnableClock(kCLOCK_GateGPIO3); /* PORT0: Peripheral clock is enabled */ CLOCK_EnableClock(kCLOCK_GatePORT0); CLOCK_EnableClock(kCLOCK_GatePORT1); CLOCK_EnableClock(kCLOCK_GatePORT2); CLOCK_EnableClock(kCLOCK_GatePORT3); /* GPIO1 peripheral is released from reset */ RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn); /* GPIO3 peripheral is released from reset */ RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kLPSPI0_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kLPSPI1_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn); const port_pin_config_t port0_2_pin78_config = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Low internal pull resistor value is selected. */ kPORT_LowPullResistor, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive input filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain output is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Normal drive strength is configured */ kPORT_NormalDriveStrength, /* Pin is configured as LPUART0_RXD */ kPORT_MuxAlt2, /* Digital input enabled */ kPORT_InputBufferEnable, /* Digital input is not inverted */ kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORT0_2 (pin 78) is configured as LPUART0_RXD */ PORT_SetPinConfig(PORT0, 2U, &port0_2_pin78_config); const port_pin_config_t port0_3_pin79_config = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, /* Low internal pull resistor value is selected. */ kPORT_LowPullResistor, /* Fast slew rate is configured */ kPORT_FastSlewRate, /* Passive input filter is disabled */ kPORT_PassiveFilterDisable, /* Open drain output is disabled */ kPORT_OpenDrainDisable, /* Low drive strength is configured */ kPORT_LowDriveStrength, /* Normal drive strength is configured */ kPORT_NormalDriveStrength, /* Pin is configured as LPUART0_TXD */ kPORT_MuxAlt2, /* Digital input enabled */ kPORT_InputBufferEnable, /* Digital input is not inverted */ kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ kPORT_UnlockRegister}; /* PORT0_3 (pin 79) is configured as LPUART0_TXD */ PORT_SetPinConfig(PORT0, 3U, &port0_3_pin79_config); const port_pin_config_t port2_13_pin35_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_SDO */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 13U, &port2_13_pin35_config); const port_pin_config_t port2_12_pin34_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_SCK */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 12U, &port2_12_pin34_config); const port_pin_config_t port2_16_pin37_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_SDI */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 16U, &port2_16_pin37_config); const port_pin_config_t port2_6_pin28_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPSPI1_PCS0 */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT2, 6U, &port2_6_pin28_config); const port_pin_config_t port1_15_pin8_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as GPIO1 15 */ kPORT_MuxAlt0, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT1, 15U, &port1_15_pin8_config); const port_pin_config_t port1_14_pin7_config = { kPORT_PullUp, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as GPIO1 14 */ kPORT_MuxAlt0, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT1, 14U, &port1_14_pin7_config); const port_pin_config_t port3_16_pin59_config = { kPORT_PullUp, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as GPIO3 16 */ kPORT_MuxAlt0, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT3, 16U, &port3_16_pin59_config); const port_pin_config_t port0_16_pin83_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPI2C0 SDA */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT0, 16U, &port0_16_pin83_config); const port_pin_config_t port0_17_pin84_config = { kPORT_PullDisable, kPORT_LowPullResistor, kPORT_FastSlewRate, kPORT_PassiveFilterDisable, kPORT_OpenDrainDisable, kPORT_LowDriveStrength, kPORT_NormalDriveStrength, /* Pin is configured as LPI2C0 SCL */ kPORT_MuxAlt2, kPORT_InputBufferEnable, kPORT_InputNormal, kPORT_UnlockRegister}; PORT_SetPinConfig(PORT0, 17U, &port0_17_pin84_config); } Configure the main.c as follows: Habib_MS_0-1781813861103.png Spoiler (Highlight to read) #include #include #include "board.h" #include "app.h" #include "pin_mux.h" #include "fsl_debug_console.h" extern void nfc_example (void); int main(void) { BOARD_InitHardware(); #ifdef BOARD_NXPNCI_INTERFACE_I2C PRINTF("\nRunning the NXP-NCI2.0 example (I2C interface)\n"); #else PRINTF("\nRunning the NXP-NCI2.0 example (SPI interface)\n"); #endif nfc_example(); } #include #include #include "board.h" #include "app.h" #include "pin_mux.h" #include "fsl_debug_console.h" extern void nfc_example (void); int main(void) { BOARD_InitHardware(); #ifdef BOARD_NXPNCI_INTERFACE_I2C PRINTF("\nRunning the NXP-NCI2.0 example (I2C interface)\n"); #else PRINTF("\nRunning the NXP-NCI2.0 example (SPI interface)\n"); #endif nfc_example(); } Building and Debugging the example For building the example, please click on this button and if you followed this guide accordingly the project should compile without errors: Habib_MS_1-1781813991676.png Habib_MS_2-1781813999778.png Open a serial terminal such as Teraterm with the following settings: Habib_MS_3-1781814017721.png  Start a debug session by clicking this button: Habib_MS_4-1781814064724.png Once running, the example should look as follows: Habib_MS_5-1781814084057.png  When tapping a card on the antenna, the card information will be shown: Habib_MS_6-1781814110924.png NFC Controller Solutions
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