How do I convert the voltage of digital signals? (Japanese blog)
0. Table of Contents
0. Table of Contents
1. What is a voltage level translator?
2. Digital signals
2.1 Various Digital Signals
2.2 CMOS and TTL: Logic level signals using simple voltage HIGH and LOW
2.3 Input/Output Voltage Specification: VOH/VOL and VIH/VIL
2.3.1 Output voltage specifications: VOH and VOL
2.3.2 Input voltage specifications: VIH and VIL
2.3.3 The relationship between VOH/VOL and VIH/VIL
3. Basic voltage level conversion method: One-way signal conversion
3.1 Examples where conversion is not necessary even if the chip's power supply voltage is different.
Column: How are the TTL values VIH(min) = 2.0V and VIL(max) = 0.8V determined?
3.2 Examples requiring conversion
3.2.1 Conversion using open-drain output
3.2.2 Conversion using standard logic (general-purpose logic) chips
4. Conversion of bidirectional signals requiring automatic direction switching.
4.1 Bidirectional conversion using a single MOS transistor
4.2 Bidirectional conversion using dedicated equipment
4.2.1 I²C signal voltage conversion chip
4.2.2 High-speed bidirectional open-drain signal-to-voltage conversion chip
4.2.3 Bidirectional push-pull signal-to-voltage converter chip
4.2.4 I3C signal voltage converter chip
4.2.5 Buffer-based conversion
5. Summary
5.1 Comparison of methods/part numbers introduced in the blog
6. Reference materials
1. What is a voltage level translator?
When connecting digital circuits, you can simply connect the signal lines directly... That's not the case; if the " logic level voltage " doesn't match, it may not work, become unstable, or in the worst case, damage the chip. That's where a voltage level translator (also called a voltage level shifter) comes in handy.
A voltage level translator is a circuit that allows signals to be exchanged between digital circuits with different power supply voltages.
For example, it is needed in the following cases:
3.3V microcontroller ↔︎ 5V sensor connection
Connecting a 1.8V FPGA to 3.3V peripheral devices
Figure 1: Differences in signal voltage
This blog explains the differences in voltage levels between various types of logic circuits used in digital circuits (*TTL, *LVTTL, *CMOS), and the important meanings of VOH / VOL / VIH / VIL for determining them. Furthermore, it explains which voltage level translator to choose from among various conversion methods.
Furthermore, this blog will look at specific examples of voltage level translators that automatically detect and convert the direction of a signal .
NXP also offers voltage level translators for SD cards/SIM cards and application-specific translators such as GTL↔︎TTL level conversion, but this blog will focus on products targeted at general-purpose or serial bus applications.
*TTL (Transistor-Transistor Logic) *LVTTL (Low Voltage Transistor-Transistor Logic) *CMOS (Complementary Metal-Oxide-Semiconductor) *GTL (Gunning Transceiver Logic)
2. Digital signals
2.1 Various Digital Signals
So-called "digital signals" are electrical representations of logic levels 1 and 0. Historically, there have been various circuit design methods for handling these logic levels 1 and 0. These include methods that represent logic levels with simple voltage HIGH and LOW, and methods that use voltage differences to represent HIGH/LOW.
TTL simply represents HIGH/LOW as 5V/0V. Further reducing the voltage of TTL to 3.3V/0V, such as LVTTL , are systems where the voltage level is determined based on a bipolar transistor circuit. Similarly, ECL (Electronic Classification) uses bipolar transistors but employs a negative power supply to implement low-amplitude, differential operation logic levels, resulting in higher speeds. GTL (Global Transistor Lapping) uses a reference voltage to transmit HIGH/LOW signals with low-amplitude single-ended signals, etc.
Furthermore, even with a simple HIGH/LOW representation, the 4000 series of CMOS general-purpose logic, developed with the aim of reducing power consumption, allowed the use of 3V to 18V as the HIGH level. https://en.wikipedia.org/wiki/Logic_family
This blog will explain how to handle voltage levels in TTL (LVTTL) and CMOS, which represent logic using simple HIGH and LOW voltages , among the various logic levels mentioned above. Other signal conversions utilize dedicated chips and are therefore not covered here.
In addition, in recent years, semiconductor technology has become smaller, faster, and more power-efficient, and the voltage used for power supplies has been decreasing. For this reason, voltage level translators, which bridge the signal voltage difference, have become particularly important.
Figure 2: Signal waveform - Voltage levels (HIGH/LOW) represent logic levels.
2.2 CMOS and TTL: Logic level signals using simple voltage HIGH and LOW
In digital circuits, simple voltage-based logic level signals using HIGH and LOW typically use the power supply voltage for HIGH and 0V for LOW. As long as the HIGH/LOW voltage levels are the same, the signals can be transmitted even if the power supply voltages are different.
For example, TTL (LVTTL) interprets an input signal as HIGH if it is 2.0V or higher, and LOW if it is 0.8V or lower. Because of this convention, the HIGH/LOW voltage levels of TTL signals do not change even if the power supply voltages are different. On the other hand, CMOS defines HIGH/LOW based on half the power supply voltage. Therefore, the HIGH/LOW voltage levels of CMOS change when the power supply voltage is different.
Figure 3: Input signal voltage specification
2.3 Input/Output Voltage Specification: V OH / V OL and V IH / V IL
In digital circuits, the voltages output as HIGH and LOW , and the voltage used to determine whether an input signal is HIGH or LOW, are specified. These are defined in the specifications of each chip used, so you need to check the datasheet.
V OH : High-level output voltage
VOL : Low-level output voltage
V IH : High-level input voltage
V IL : Low-level input voltage
2.3.1 Output voltage specifications: V OH and V OL
When considering the output, you must take into account the current required when outputting HIGH/LOW signals. The current will increase or decrease depending on the load.
The voltage that can be guaranteed at the maximum outflow current with HIGH output is called VOH (min) , and the voltage that can be guaranteed at the maximum inflow current with LOW output is called VOL (max) .
V OH (min) is the voltage output when the upper transistor in the circuit's output stage is turned ON. This transistor has a resistance called "ON resistance".
When a large current flows out of a transistor, a voltage is generated equal to "the transistor's resistance x the current flowing through it". This causes the output voltage to drop below the power supply voltage by that amount, resulting in a low VOH . Therefore, VOH (min) is the minimum voltage that can be guaranteed when the maximum expected outflow current is reached.
Figure 4: Digital signal output circuit (push-pull)
Figure 5: HIGH output voltage varies depending on the load.
VOL is the opposite. When the lower transistor in the output stage of the circuit is turned ON, if the incoming current is large, the output will rise above 0V due to the voltage generated by the ON resistance of the transistor, as described above. Taking this into consideration, VOL (max) is the maximum voltage that can be guaranteed when the maximum incoming current is anticipated.
Figure 6: LOW output voltage also changes depending on the load.
2.3.2 Input voltage specifications: V IH and V IL
The input has voltage levels to determine HIGH and LOW : V IH (min) and V IL (max) . If the voltage is above V IH (min), it is judged as HIGH; if it is below V IL (max), it is judged as LOW.
In CMOS inputs, half the power supply voltage serves as the reference for HIGH and LOW, but this is not directly used as V IH (min) and V IL (max). This is because the threshold can fluctuate due to variations between chips. Also, to mitigate glitches caused by noise on slow-rising signals appearing in the output, it is common practice to incorporate hysteresis into the input. For these reasons, V IH (min) and V IL (max) are defined with a certain voltage difference.
2.3.3 The relationship between VOH / VOL and VIH / VIL
For normal signal exchange to occur, the relationship between the output and input must satisfy the following equation.
HIGH level: V OH (min) > V IH (min)
LOW level: VOL (max) < VIIL (max)
If this relationship is maintained, the output circuit can correctly transmit HIGH/LOW signals to the next input circuit. Furthermore, the voltage difference between them, "V OH (min) - V IH (min)" and "V IL (max) - V OL (max)," becomes the " noise margin " and serves as a guideline for maintaining high noise immunity.
Figure 7: V OH (min) / V OL (max) and V IH (min) / V IL (max)
3. Basic voltage level conversion method: One-way signal conversion
3.1 Examples where conversion is not necessary even if the chip's power supply voltage is different.
Voltage level conversion is generally not necessary when the relationships "V OH (min) > V IH (min)" and "V OL (max) < V IL (max)" hold true. For example, although TTL and LVTTL use different power supply voltages for their respective chips, the input and output voltage specifications are the same .
In both TTL (5V) and LVTTL (3.3V), V OH (min) is 2.4V and V OL (max) is 0.4V. Since V IH (min)/V IL (max) are also 2.0V/0.8V in both cases, they can be connected to each other without any problems.
However, caution is required if the output voltage is higher than the power supply voltage of the input chip. If the output chip uses a 5V power supply and the input uses a 3.3V power supply, the input must support " 5V tolerant input ".
A 5V tolerant input is an input that can operate without problems even when a 5V HIGH signal is connected to the input of a chip that operates on a 3.3V power supply voltage. While typical chip inputs have ESD protection circuits to protect against static electricity, if this ESD protection circuit is configured as shown in the following diagram, a 5V input can cause current to flow back from the input to the 3.3V power supply, potentially damaging the chip. A 5V tolerant input is designed to prevent such problems. Tolerant inputs do not lack ESD protection; they incorporate an ESD protection circuit that is structured to handle signals higher than the power supply voltage without causing problems.
ESD protection diodes like the one shown in Figure 7 can also cause problems when the power to the input chip is turned off. In systems where the power to each chip is controlled individually, the output signal may feed back into the power supply even when the input chip is off, causing the input chip to operate.
Figure 7: ESD protection diode - non-tolerant input
Column: How are the V IH (min) = 2.0V and V IL (max) = 0.8V determined for TTL?
While the input threshold of CMOS is based on the midpoint of the power supply voltage (VCC/2), the V IH (min)/V IL (max) of TTL is 2.0V/0.8V, which is not a particularly neat ratio with respect to the power supply voltage (5V). This is related to the fact that the input stage of TTL is composed of bipolar transistors.
Example of the internal circuit of a standard TTL logic IC: SN7400 (2-input NAND). This information was included in the "Latest General-Purpose Logic Device Specifications Table 1988" (CQ Publishing).
A typical TTL gate's input stage consists of a multiple emitter input transistor and a subsequent phase splitter transistor, both connected in series. The "switching threshold," at which the gate actually begins to react, is determined by the forward voltage of the PN junctions in these two stages. Since the forward voltage of a single silicon PN junction is approximately 0.6 to 0.7V, the combined forward voltage of the two stages is approximately 1.3 to 1.5V, which is the effective switching threshold for a TTL gate.
However, this value of approximately 1.4V is merely a "typical value," and it will fluctuate from lot to lot and from condition to condition due to individual differences and variations in temperature. Therefore, the specified values V IH (min) and V IL (max) on the datasheet are defined as guaranteed values, with sufficient margins above and below this typical value of approximately 1.4V, meaning that "if it drops to this level, it can be reliably determined to be LOW (V IL (max) = 0.8V)" and "if it rises to this level, it can be reliably determined to be HIGH (V IH (min) = 2.0V)."
Furthermore, this value is not determined in isolation, but is designed taking into account the relationship between VOH and VOL , as explained in Section 2.3.3. In standard TTL, due to the output stage configuration, the HIGH output is not the power supply voltage, but a slightly lower voltage (lower by the voltage generated by the 130Ω resistor, transistor, and diode in the circuit example above) (VOH(min)=2.4V). When this is combined with VOL(max)=0.4V,
HIGH noise margin: V OH (min) − V IH (min) = 2.4 − 2.0 = 0.4V
Low-side noise margin: V IL (max) − V OL (max) = 0.8 − 0.4 = 0.4V
As shown, it is designed to ensure a noise margin of 0.4V symmetrically above and below. In other words, the 2.0V/0.8V figures for TTL, which may seem "odd" relative to the power supply voltage, are actually reasonable values derived from two requirements: the physical reality of the bipolar transistor junction voltage and the noise margin design.
This image shows an SN7420 (4-input NAND) with three input pins set to HIGH and one pin receiving a 100kHz triangular wave (ch1). The output under no load (ch2) is less than 4V when HIGH (Vcc=5V).
The circuit introduced in this column is an example of a standard TTL without a designation (such as 74 LS 00 or 74 HC 00, without LS/HC prefixes; sometimes called "vanilla TTL" in English), but the reason why the V IH /V IL specifications are the same (bipolar junction characteristics of the input stage) is common to other TTL families such as the 74LS.
3.2 Examples requiring conversion
While TTL and LVTTL connections are possible because the voltage levels are aligned, mismatches in logic levels often occur when connecting CMOS chips with different power supply voltages, or when connecting a CMOS chip to a TTL chip. This occurs when the aforementioned relationship "V OH (min) > V IH (min)" and "V OL (max) < V IL (max)" does not hold true, or when the difference becomes too small, resulting in insufficient noise margin.
A voltage level translator solves this problem.
Figure 9: Example of mismatched logic levels (1): Insufficient HIGH voltage input
Figure 10: Example of mismatched logic levels (2): Insufficient LOW voltage is input.
3.2.1 Conversion using open-drain output
There are ways to easily adjust voltage levels without using a voltage level conversion chip.
If the signal direction is fixed from the output chip to the input chip and does not switch, then this method involves making the HIGH output an open-drain output to match the input voltage. An open-drain output is a configuration in which the upper transistor of the output stage of a digital circuit is absent, and the HIGH voltage is obtained by a pull-up resistor connected to the power supply voltage of the input chip .
Figure 11: Digital signal output circuit (open drain)
Open drains are a simple and inexpensive method, but there are a few things to keep in mind .
First, the output side must be capable of open-drain output. Many microcontrollers' GPIO pins can provide this type of output through configuration.
First, the output side must be capable of open-drain output. Many microcontrollers' GPIO pins can provide this output through configuration. If the output is fixed to push-pull output and cannot be configured for open-drain output, an external transistor or similar device will be needed to convert it to open-drain output.
Furthermore, the selection of pull-up resistors is also important.
A pull-up resistor is necessary to obtain a HIGH voltage, but if the resistance value is too small, the current flowing when the output is LOW will be large (similar to a heavy load), which will increase power consumption and lead to an increase in VOL .
Conversely, if the value is too large, it will be affected by the capacitance of the wiring and pins, causing the rise time from LOW to HIGH to be slow, resulting in a decrease in communication speed.
3.2.2 Conversion using standard logic (general-purpose logic) chips
For simple voltage level conversion, you can also use standard logic. For example, Nexperia's 74AVCH4T245 is a general-purpose CMOS logic chip that can perform 4-bit bidirectional level conversion.
This chip can convert signals from 0.8V to 3.6V, and the signal direction can be switched using the DIR pin. The signal speed depends on the voltage being converted, but it can support speeds of approximately 100M to 380Mbps.
Figure 12: Example of standard logic - 74AVCH4T245
This chip enables high-speed bidirectional voltage conversion of signals, but the direction must be controlled by an external signal. While such control is possible with signals like READ/WRITE on a parallel bus, it is difficult to apply to communications like serial buses where the communication direction switches depending on the protocol.
Figure 13: Example of standard logic. The signal direction must be specified externally.
4. Conversion of bidirectional signals requiring automatic direction switching.
The "open-drain output" and "voltage conversion methods using standard logic chips" introduced so far mainly perform conversion in only one direction, or require switching of direction by an external signal.
Communication methods like I²C and I3C , where the direction of the signal changes dynamically, require " bidirectional voltage level conversion " that automatically detects and switches the direction. Controlling the direction of such signals externally is difficult, and it is challenging to implement this with the buffer chips mentioned above.
Furthermore, since I²C is an open-drain signal, it is not possible to connect standard open-drain logic buffers in opposite directions. Figure 14 shows an example of this, where open-drain buffers are connected in opposite directions. There is no problem when both sides of the buffer are HIGH, but once one of them goes LOW, the buffers will keep pulling the other input LOW and will not be able to return to HIGH.
Figure 14: A typical open-drain buffer cannot automatically switch between bidirectional communication.
4.1 Bidirectional conversion using a single MOS transistor
Until now, simple circuits have sometimes been used for I²C signal-to-voltage conversion. We will present the simplest method, using a MOS transistor, as an example.
Figure 15: Example of conversion using a MOS transistor
Figure 15 is taken from the I²C specification version 2.1 (2000) and shows an example where two MOS transistors (TR1, TR2) are used to convert 3.3V and 5V signals, respectively. Although such a simple conversion example using only transistors has been removed from the current I²C specification due to the problems described later, it is included here to understand the principle .
The I²C signal lines, called SDA and SCL, are both open-drain bidirectional signals. Pull-up resistors are connected to the 3.3V and 5V sides, respectively.
In this circuit, when the 3.3V and 5V signals are HIGH, the gate (g) and source (s) of this transistor are at the same potential, so the source (s) and drain (d) are OFF, and the connection between them is broken. When 3.3V changes to LOW in this state, the 3.3V side transistor (between s and d) turns ON , and the 5V side signal also goes LOW .
When the 3.3V side changes to HIGH and the 5V side changes to LOW , the parasitic diode (body diode) connecting the 3.3V side to the 5V side first turns ON . When the diode turns ON, the source(s) voltage drops . As a result, the transistor turns ON , and the signal on the 3.3V side also becomes LOW .
While this very simple mechanism using a transistor as a switch allows for voltage level conversion, there are problems. Transistor variations affect the threshold voltage for signal conversion. Furthermore, with the increasing need to handle lower signal voltages, for example, at signal voltages of around 1V, such a circuit cannot operate because it cannot obtain a sufficient gate-to-source voltage (Vgs).
4.2 Bidirectional conversion using dedicated equipment
By using a dedicated voltage level translator IC , voltage level conversion for bidirectional communication buses such as I²C and I3C can be easily performed.
4.2.1 I²C signal voltage conversion chip
The PCA9306 and NVT20xx series ( NVT2001/02 , NVT2003/06 , NVT2008/10 ) are voltage level translators specifically designed for bidirectional signal conversion. These chips can handle multiple signal lines (multi-bit signal lines) simultaneously. While they are designated as I²C signal voltage conversion chips, they can also be used for other purposes (such as SPI and other push-pull signals) if the signal specifications match .
The PCA9306 and NVT20xx series share the same internal structure, and the pull-up resistor only needs to be connected to the higher voltage side if the voltage difference to be converted is 1V or more .
Figure 16 shows its internal structure and connection to external chips (excerpted from Fig. 2 of Application Note AN11127 : "Bidirectional voltage level translators NVT20xx and PCA9306" ). This chip contains the number of signal lines (bits) + 1 MOS transistors. Each transistor has a structure in which the source and drain are interchangeable.
The transistors in the signal transmission path are called pass transistors , and the remaining one is called a reference transistor .
Figure 16: NVT20xx (PCA9306) - Diagram illustrating chip operation.
Looking at the circuit, the gate and drain of the reference transistor are shorted and connected to the higher voltage power supply via a 200kΩ resistor. The remaining terminal of the reference transistor, the source, is connected to the lower voltage power supply. With this connection, the reference transistor acts as a single diode , and its gate voltage is one diode higher than the lower voltage power supply .
The remaining pass transistor has its drain connected to the high-voltage signal line and a 1kΩ pull-up resistor, its source connected to the low-voltage signal line, and its gate connected to the gate of the reference transistor. When both the high and low signals of the pass transistor are HIGH, the high-voltage side becomes the voltage pulled up by the 1kΩ resistor .
A pass transistor forms a circuit known as a "source follower." The terminal on the lower voltage side (source terminal) has a voltage that is lower than the voltage applied to the gate by the amount of Vgs required to turn the transistor ON . In other words, it has the same voltage as the low-voltage power supply. The transistor is in a semi-ON state (operating in the linear region), neither ON nor OFF.
In this state, when either the high or low signal becomes LOW , the voltage difference between the gate and the signal terminal causes the transistor to turn ON (operating in the saturation region where it is fully ON), and the other terminal also becomes LOW .
The signal speed that this series can handle is affected by the pull-up resistor and the capacitance of the signal line. The datasheet states that the PCA9306 can handle up to 2MHz. The NVT20xx series can handle signal speeds up to 33MHz with a 192Ω pull-up resistor and a capacitance of 50pF. For signals around 1MHz, it will work without problems even if you don't worry too much about the pull-up resistor and capacitance (assuming it's within the range typically used for I²C). However, when using this chip to handle higher-speed signals in a push-pull configuration, a thorough understanding of its characteristics and careful component selection are necessary.
Details of the operation of this type of voltage level translator are described in the article " The Internals and Operation of the PCA9306 ".
4.2.2 High-speed bidirectional open-drain signal-to-voltage conversion chip
We introduce the NTS030x series ( NTS0302JK , NTS0304E ) as high-speed bidirectional open-drain signal conversion chips.
This chip can perform 2-bit or 4-bit bidirectional signal conversion and can handle signals up to 2Mbps (1MHz) for open-drain signals and 20Mbps (10MHz) for push-pull signals.
Figure 17: NTS030x - Internal Chip Block Diagram
Figure 17 shows the internal structure of one signal bit in the NTS030x.
In the diagram, transistor T3 is a pass-through transistor , and a gate terminal bias voltage is applied to it, so it turns ON when either the signal labeled A or B goes LOW.
When both A and B are HIGH, T3 turns OFF, and since A and B are connected to their respective power supplies with relatively large pull-up resistors (10kΩ), they will have their respective voltages.
This chip has T3, as well as T1 and T2 . These T1 and T2 are used for a function called " edge rate accelerator ." We will focus on one of them, T1, and explain its operation.
T1 is placed on the A side, with its source terminal connected to the A signal and its drain terminal connected to the A side power supply. The gate terminal is connected to the block labeled "ONE-SHOT AND SLEW RATE CONTROL" that controls it.
The "ONE-SHOT AND SLEW RATE CONTROL" block is connected to the B signal on the opposite side and detects the change from LOW to HIGH in the B signal . When this is detected, T1 is temporarily turned ON, bypassing the 10kΩ pull-up resistor and allowing current to flow, thereby accelerating the change from LOW to HIGH in the A signal . By speeding up the rise time of the signal in this way, it becomes possible to handle faster signals.
Incidentally, the slew rate when T1 is turned ON is controlled, taking into consideration the suppression of ringing caused by a sudden increase in current.
The other T2 uses the same mechanism but in the reverse direction, and is applied to the B-side signal as well.
The NTS series has another user-friendly feature .
In the case of the MOS transistors and PCA9306/NVT20xx described so far, there was a problem in that if one power supply was turned off, the signal of the other would be set to LOW. To solve this problem, the NTS030x operates so that when both power supplies are not ON, the signal pins are set to a high impedance state to prevent them from affecting each other . By using this function, it becomes possible to partially control the ON/OFF state of the system's power supply .
The NTS010x series ( NTS0102 , NTS0104 ) is equivalent to the NTS030x series, but lacks slew rate control functionality to handle higher-speed signals.
An evaluation board, NTS0304EUK-ARD, is available for the NTS0304E to allow for quick and simple operational verification. For an overview of the NTS0304EUK-ARD board and how to operate it, please refer to this video , "How to operate the NTS0304EUK-ARD" .
4.2.3 Bidirectional push-pull signal-to-voltage converter chip
Furthermore, for use with push-pull signals only, there is the NTB010x series ( NTB0102 , NTB0104 ), which offers a faster option.
When stable in a HIGH or LOW state, the signal is driven through a 4kΩ resistor. Similar to the NTS030x series, it has a one-shot function on both the HIGH and LOW sides, and has a mechanism that uses this to change the signal on the opposite side when there is a change in the signal at either terminal.
This mechanism enables signal-to-voltage conversion at speeds of 70-80 Mbps while also having an automatic signal direction detection function.
Figure 17: NTB010x - Internal Chip Block Diagram
4.2.4 I3C signal voltage converter chip
I3C has a specification that switches between open-drain and push-pull communication modes . In open-drain mode, it is compatible with I²C and operates at frequencies up to 4MHz . In push-pull mode, a 12.5MHz clock is used. Since the signal voltage is usually in the range of 1V to 3.3V, a voltage level translator that operates according to the signal specifications is required when there is a voltage difference.
Figure 18 shows the internal block diagram of one bit of the P3A1604 . As shown in the figure, this chip incorporates a mechanism to accelerate not only the LOW→HIGH change but also the HIGH→LOW change, as well as a pull-up resistor that can be switched ON/OFF.
Figure 18: P3A1604 - Chip internal block diagram
The P3A1604 is a 4-bit I3C voltage level translator. A 2-bit version, the P3A9606 , is also available.
4.2.5 Buffer-based conversion
Another method for converting bidirectional signals is to use a dedicated buffer. The primary purpose of a buffer is to enhance driving capability and separate the capacitance of connected signal lines, but there are also products that support voltage conversion.
As explained in this blog, simple buffers cannot mutually buffer bidirectional open-drain signals. Therefore, various buffer products with special features for bidirectional open-drain signals are available.
I will explain more about buffers on a later occasion.
5. Summary
Voltage level translators are essential components for safely and reliably exchanging signals between digital circuits with different power supply voltages. Understanding the definitions of logic levels such as TTL, LVTTL, and CMOS, as well as the relationships between VOH/VOL/VIH/VIL, allows you to select the appropriate connection and conversion method.
For unidirectional conversion, open-drain outputs or standard logic ICs can be used, while for bidirectional conversion, MOS transistors or dedicated ICs (such as the PCA9306/NVT/NTS/NTB/P3A series) can be used. Voltage level translators with automatic signal direction detection capabilities are particularly useful for buses requiring bidirectional communication, such as I²C and I3C.
Furthermore, recent advancements in semiconductor technology have led to lower voltages and higher speeds, requiring more precise voltage level control. While there are many methods and options for voltage level conversion, it is important to select the optimal method and components according to the application, taking into account signal specifications, speed, and system power management.
5.1 Comparison of methods/part numbers introduced in the blog
Method/Part Number
Purpose
Number of bits
Direction change
Open wiring compatible
Low voltage side [V]
High voltage side [V]
Bitrate [bps]
Conversion with open-drain output
General purpose
1
unidirectional
-
-
-
-
Standard logic (e.g., 74AVCH4T245)
General purpose (parallel bus, etc.)
4 + 4
External control
Not supported
0.8 ~ 3.6
0.8 ~ 3.6
100M ~ 380M
Bidirectional conversion using a single MOS transistor
I²C, General Purpose
1
automatic
correspondence
Depending on the transistor specifications
~ 1M
PCA9306
I²C, General Purpose
2
automatic
correspondence
1.0 ~ 3.6
1.8 ~ 5.5
4M (2MHz, depending on conditions)
NVT2001
I²C, General Purpose
1
automatic
correspondence
1.0 ~ 3.6
1.8 ~ 5.5
4M (2MHz @ open drain), 66M (33MHz @ optimized conditions)
NVT2002
I²C, General Purpose
2
automatic
correspondence
1.0 ~ 3.6
1.8 ~ 5.5
4M (2MHz @ open drain), 66M (33MHz @ optimized conditions)
NVT2003
I²C, General Purpose
3
automatic
correspondence
1.0 ~ 3.6
1.8 ~ 5.5
4M (2MHz @ open drain), 66M (33MHz @ optimized conditions)
NVT2006
I²C, General Purpose
6
automatic
correspondence
1.0 ~ 3.6
1.8 ~ 5.5
4M (2MHz @ open drain), 66M (33MHz @ optimized conditions)
NVT2008
I²C, General Purpose
8
automatic
correspondence
1.0 ~ 3.6
1.8 ~ 5.5
4M (2MHz @ open drain), 66M (33MHz @ optimized conditions)
NVT2010
I²C, General Purpose
10
automatic
correspondence
1.0 ~ 3.6
1.8 ~ 5.5
4M (2MHz @ open drain), 66M (33MHz @ optimized conditions)
NTS0302JK
I²C, SPI, General Purpose
2
automatic
correspondence
0.95 ~ 3.6
1.65 ~ 5.5
2M @ Open Drain, 20M @ Push Pull
NTS0304E
I²C, SPI, General Purpose
4
automatic
correspondence
0.95 ~ 3.6
1.65 ~ 5.5
2M @ Open Drain, 20M @ Push Pull
NTS0102
I²C, SPI, General Purpose
2
automatic
correspondence
1.65 ~ 3.6
2.3 ~ 5.5
50M @ Push-Pull
NTS0104
I²C, SPI, General Purpose
4
automatic
correspondence
1.65 ~ 3.6
2.3 ~ 5.5
50M @ Push-Pull
NTB0102
SPI, General Purpose
2
automatic
Not supported
1.2 ~ 3.6
1.65 ~ 5.5
70M ~ 80M
NTB0104
SPI, General Purpose
4
automatic
Not supported
1.2 ~ 3.6
1.65 ~ 5.5
70M ~ 80M
P3A9606
I3C, I²C, SPI, General Purpose
2
automatic
correspondence
0.72 ~ 1.98
0.72 ~ 1.98
(12.5MHz)
P3A1604
I3C, I²C, SPI, General Purpose
4
automatic
correspondence
0.72 ~ 1.98
1.62 ~ 3.63
6.8M @ Open Drain, 40M @ Push Pull
Table 1: Comparison of methods/part numbers introduced in the blog
6. Reference materials
Product introduction page: Voltage Level Converter
NXP System Management I2C, I3C, SPI Selector Guide
I2C Bus Specifications and User Manual (Rev5.0) (Japanese version)
I2C Bus Specifications and User Manual (Rev7.0) English version)
NXP Community Blog: I3C Bus Overview – The Next Serial Bus
Japanese Webinar Video: "The Basics of the Next-Generation Interface 'I3C' That You Need to Know Now"
Qiita @teddokano: PCA9306's internals and operation
Change history: 2025-08-28: First Edition 2025-08-28: Added information about NTS0304EUK-ARD and a link to the blog with the video. 2026-04-10: Correction of low voltage side [V] and high voltage side [V] in Table 1. 2026-06-20: Section 3.1 "Column: VIH (min) of TTL" Added "How are VIL(max) = 2.0V and VIL(max) = 0.8V determined?". Added internal circuit example of standard TTL logic IC: SN7400 (2-input NAND) and output waveform of SN7420.
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We are currently unable to respond to comments left in the "Comment" section of this post. We apologize for the inconvenience, but please refer to " Technical Questions to NXP - How to Contact Us( Japanese Blog) " when making an inquiry. (If you are already an NXP distributor or have a relationship with NXP, you may ask your representative directly.) This blog explains the differences in voltage levels between various types of logic circuits used in digital circuits (*TTL, *LVTTL, *CMOS), and the important meanings of VOH , VOL , VIH , and VIL for identifying them.
Furthermore, we will explain which voltage level translator to choose from among the various conversion methods.
We will take a closer look at the conversion of bidirectional open-drain signals , which requires special handling.
Interface Introduction Japanese Blog
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