Example S32R274 PIT ISR

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Example S32R274 PIT ISR

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Example S32R274 PIT ISR

This example content a basic FMPLL initialization and configuration of Mode Entry module and Clock Generation module. By default active is core 2 -> e200z4

Demonstration of PIT triggering an interrupt on timeout.
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* Test HW: MPC57xx + S32R274RRUEVB
* Maskset: 1N58R
* Target : internal_FLASH
* Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4

********************************************************************************
Revision History:
1.0 Apr-02-2019      b21190        (Vlna Peter) Initial Version
1.1 Sep-19-2019     nxa13250    (Vlna Peter) Added PIT + interrupts
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Last update:
‎09-08-2020 12:26 AM
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