MPC5xxx ナレッジベース

ディスカッション

******************************************************************************** * Detailed Description: * This example initializes SMPU_0 and SMPU_1 to cover all memory resources for * all masters. * Simple test case is used in this example: after initialization, SMPU * configuration is changed to disable write access to last 4kB of RAM. * Once this area is written by CPU, exception will occur due to access * violation. * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N81M * Target : SRAM * Fsys: 160 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit * ECC error in internal SRAM (user must choose it in the option at the end of * main function). * Error Injection Module is used to generate a non-correctable (or single-bit) * ECC error in RAM. The bad data is accessed then, so the IVOR1 exception (or * ERM combined interrupt service routine) is generated and handled. * Example also offers useful macros for EIM and ERM modules. * The example displays notices in the terminal window (USBtoUART bridge J21) * (19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: eSCI_A is USBtoUART bridge (connector J21) * ********************************************************************************

This config tool simplifies PLL setting calculation and clock configuration for MPC5744P device. Follow these steps Note: Macros have to be enabled! 1. Enter frequency of used XOSC and desired PLL0 and PLL1 output. - put values into cells B11, Q10 and Q17 of the "Clocks" sheet - check if it is Valid or Invalid - "PLLconfig" sheet shows possible PLLs configurations 2. Configure System and AUX clock selectors and its Dividers - check calculated frequency of System/Peripheral clocks - if Invalid change source clock and Divider value to keep Max freq 3. Copy generated code by pressing "Copy Code" button

******************************************************************************** * Detailed Description: * * * This example shows usage of FlexPWM and Sine Wave generator (SGEN) modules. * The setting is selected in the way to have a PWM output signal synhronized with * SWG output signal. This is necessary for resolver usage in motor control appls. * The CTU_0 is triggered from FlexPWM_0's. The PMWB output rising edge is used here. * The CTU generates the eTIMER1_TRG signal, that is a trigger signal for the * SGEN module. The delay between PWMB and SGEN trigger is changed so you can see * the generated sinusoidal signal change phase against the PWMB output. * * See attached Excel sheet for calculation of parammeters used here (AUX0_clk_DIV0, * AUX0_clk_DIV1, SGEN_IOFREQ, PWM_PRESCALER, PWM_MODULO). * * This example is set for 9.765625KHz SGEN/PWM frequency. * * Note because the SGEN trigger input is an asynchronous signal, it must be held high * for at least 2 SGEN clock cycles in order to capture the input trigger. * As the CTU generates the trigger as a pulse of single CTU clock width, the CTU clock must be * half of the SGEN clock at least. * * Use the AUX0_clk_DIV0 to test this behaviour. * * * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N65H * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P11.8 - D[7] .. SGEN output * connected to FEC PHY's MIIMODE input on motherboard, * to see full amplitude remove J26 * * P8.12 - A[11] .. FlexPWM A[0] output * P8.11 - A[10] .. FlexPWM B[0] output * * ********************************************************************************

This example performs LED toggling using hardware vector mode. *UPDATE* - Internal RAM function was added, fixed exceptions, * * Detailed Description: * - 1 second LED1 toggle using emios interrupt * - LED2 toggle using irq 0 interrupt via sw_button1 * - 1 second LED3 toggle using Decrementer via IVOR10 * - hardware vector mode configuration for interrupts * * ------------------------------------------------------------------------------ * Test HW: MPC5566 EVB MOTHERBOARD, PPC5566 MVR132 * Target : Internal Flash, Internal RAM * Fsys: 80 MHz PLL with 8 MHz crystal reference * * ------------------------------------------------------------------------------ * EVB connections and jumper configuration * * MPC5566 EVB MOTHERBOARD * * LED1 D17 * LED2 A17 * LED3 C16 * For SW1 is used pin 2 and it is connected to AF19 * *********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows usage of FlexPWM to generate independent * PWM signals from Submodule0. The PWMX output is set for 50% duty. * PWMA/PWMB outputs vary its duty cycles. * The DMA module is used to reload VAL2-5 registers. * * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N65H * Target : RAM, internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * * EVB connection: * P8.12 - A[11] .. FlexPWM A[0] output * P8.11 - A[10] .. FlexPWM B[0] output * P11.10 - D[9] .. FlexPWM X[0] output * ********************************************************************************

The example does exactly the same operation like this example: https://community.freescale.com/docs/DOC-105380 ...but SSD flash driver is used now. ******************************************************************************** * Detailed Description: * * Unlock, erase and program of flash mid block 0x00FB_8000 - 0x00FB_FFFF. * Used SSD flash drivers: * http://www.freescale.com/files/product/software/C55_JDP_SSD.exe * Version of the driver is v1.0.0 * ------------------------------------------------------------------------------ * Test HW: X - PC5748G - MB (rev C) * MCU: PPC5748GMMN6A * Maskset: 1N81M * Fsys: 160 MHz * Debugger: Lauterbach Trace32 * * Target: Internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC564AKIT324S it initializes EBI for mounted external SRAM. * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW: XPC564AKIT208S and XPC564AKIT324S * MCU: SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys: 150/132/120/12 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * * * This example demonstrate functionality of XBIC_0 error injection * capability on XBAR_0. The fault is generated on Core access to SRAM. * After fault generation it is propagated to FCCU unit as NCF[38]. * * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N65H * Target : internal_FLASH * Fsys: 16MHz IRC * ********************************************************************************

******************************************************************************** * Detailed Description: * * * This example demonstrate functionality of XBIC_1 error injection * capability. The fault is generated on DMA transfer to SRAM. * After fault generation it is propagated to FCCU unit as NCF[59]. * * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N65H * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * ********************************************************************************

The purpose of the example is to present advantage of streaming mode feature. Example initializes eQADC module, converts specified command queue and displays results into terminal window. Used analog inputs ANB_0 and ANB_1 requires external connection to converted voltage (potentiometer) to see some valid numbers. Following channels are being converted: CH0 = signal ANB_0 (connect pot USER_DEV_RV2(J4-7) --> ANB_0 (J19-3)) CH1= signal ANB_1 (connect pot USER_DEV_RV3(J4-8) --> ANB_1 (J19-4)) CH2 = may be left open (example configures the pin to be pulled-up) CH3 = may be left open (example configures the pin to be pulled-down) Result are being filled to 2 result queues to see loop switching in the terminal window when advance trigger occurs (results are displayed in two columns, 1st column is related to Rqueue0, 2nd to Rqueue1). Advance trigger occurs when EVB's USER switch 1 is being pressed (considering USER_DEV_1D(J4-2) --> TPU_A0 (J22-1)). Repeat trigger is initiated automatically by PIT3 timer in 1 sec intervals. eQADC command filled by eDMA, results drained by interrupt service routines. For detailed description SEE ATTACHED document.

******************************************************************************** * Detailed Description: * Initializes eQADC module, converts specified command queue and displays * results into terminal window when EOQ is reached. Used analog inputs ANA_0 and * ANA_1 requires external connection to converted voltage (potentiometer) to * see some valid numbers. For simplicity, ADC module is not calibrated. * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU: PPC5674FMVYA264 * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 264/200/150/60 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: Potentiometers --> ADC inputs * USER_DEV_RV2(J4-7) --> ANA_0 (J18-3) * USER_DEV_RV3(J4-8) --> ANA_1 (J18-4) * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, converts specified command queue and displays * results into terminal window when EOQ is reached. Used analog inputs ANA_0 and * ANA_1 requires external connection to converted voltage (potentiometer) to * see some valid numbers. For simplicity, ADC module is not calibrated. * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU: PPC5674FMVYA264 * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 264/200/150/60 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: Potentiometers --> ADC inputs * USER_DEV_RV2(J4-7) --> ANA_0 (J18-3) * USER_DEV_RV3(J4-8) --> ANA_1 (J18-4) * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi bit ECC error in * internal SRAM or FLASH (user can choose it in the option at the end of main * function) and how to handle this error with respect to constraints given by * MPC5675K architecture (ECSM/RGM/FCCU relation and ECC error handling through * reset). The example is only possible to run in internal_FLASH target. Power- * -on-reset is required after downloading the code into MCU's flash. The example * displays notices in the terminal window (setting specified below). No other * external connection is required. * Example also shows impact of enabled cache (macro OPTIMIZATIONS_ON). * * ------------------------------------------------------------------------------ * Test HW: MPC5675KEVB * MCU: PPC5675KFMMSJ in Lock-Step mode * Fsys: 180/150 MHz CORE_CLK * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * * ECSM Error Generation Register EEGR is used to generate a non-correctable * or single bit ECC error in RAM. The bad data is accessed then, so the IVOR1 * exception is generated and handled. * This file shows also ECSM_combined_isr and how to correct the wrong data. * Use macro Induce_ECC_error_by_DMA_read to select whether ECC error will be * injected by DMA read or CPU read. * At the end of main file you can choose if single bit or multi bit is injected * and select particular ME/EE setup by comment/uncomment of particular function * calls. * * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU: PPC5674FMVYA264 * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 264/200/150/60 MHz * ********************************************************************************

******************************************************************************** * Detailed Description: * * Unlock, erase and program of flash mid block 0x00FB_8000 - 0x00FB_FFFF. * ------------------------------------------------------------------------------ * Test HW: X - PC5748G - MB (rev C) * MCU: PPC5748GMMN6A * Maskset: 1N81M * Fsys: 160 MHz * Debugger: Lauterbach Trace32 * * Target: Internal_FLASH * ********************************************************************************

/* * Queue.h * * Created on: May 28, 2015 * Author: ShuLizhong */ #ifndef QUEUE_H_ #define QUEUE_H_ #ifdef _cplusplus extern "C" { #endif /*If you want to change the queue type(QUEUE_TYPE) and queue max size(QUEUE_MAX_SIZE), you should define it at front of include queue.h file. eg: ******in xxx.h file***** code**** #define QUEUE_TYPE Other type(unsigned int) #define QUEUE_MAX_SIZE Other size(100) #include "qeue.h" code**** */ #ifndef QUEUE_TYPE #define QUEUE_TYPE unsigned char #endif #ifndef QUEUE_MAX_SIZE #define QUEUE_MAX_SIZE 100 #endif #define bool unsigned int typedef enum { OK, FULL, EMPTY }QUEUE_STATUS; typedef struct { unsigned int tail; unsigned int head; unsigned int size; unsigned int length; QUEUE_TYPE data[QUEUE_MAX_SIZE]; }Queue_tag,*pQueue_tag; __inline void InitQueue(pQueue_tag q) { q->tail = q->head = q->size = 0; q->length = QUEUE_MAX_SIZE; } __inline QUEUE_STATUS EnQueue(pQueue_tag q,QUEUE_TYPE data) { if(q->size++ == QUEUE_MAX_SIZE) return FULL; q->data[q->tail] = data; q->tail = (q->tail+1) % QUEUE_MAX_SIZE; return OK; } __inline QUEUE_STATUS DeQueue(pQueue_tag q, QUEUE_TYPE *data) { if(q->size-- == 0) return EMPTY; *data = q->data[q->head]; q->head = (q->head+1) % QUEUE_MAX_SIZE; return OK; } __inline bool IsQueueEmpty(pQueue_tag q) { return q->size == 0; } __inline bool IsQueueFull(pQueue_tag q) { return q->size == QUEUE_MAX_SIZE; } __inline unsigned int GetQueueSize(pQueue_tag q) { return q->size; } __inline unsigned int GetQueueLength(pQueue_tag q) { return q->length; } /*__inline unsigned int DeMoreBytesFromQueue(pQueue_tag q,QUEUE_TYPE *data,unsigned int len) { unsigned int i = 0; len++; return 0; }*/ #ifdef _cplusplus } #endif #endif /* QUEUE_H_ */