Example MPC5777C-1b+2b_RAM_ECC_error_injection GHS614

cancel
Showing results for 
Search instead for 
Did you mean: 

Example MPC5777C-1b+2b_RAM_ECC_error_injection GHS614

Example MPC5777C-1b+2b_RAM_ECC_error_injection GHS614

********************************************************************************

* Detailed Description:

* Purpose of the example is to show how to generate Multi-bit or Single-bit

* ECC error in internal SRAM (user must choose it in the option at the end of

* main function).

* Error Injection Module is used to generate a non-correctable (or single-bit)

* ECC error in RAM. The bad data is accessed then, so the IVOR1 exception (or

* ERM combined interrupt service routine) is generated and handled.

* Example also offers useful macros for EIM and ERM modules.

* The example displays notices in the terminal window (USBtoUART bridge J21)

* (19200-8-no parity-1 stop bit-no flow control on eSCI_A).

* No other external connection is required.

*

* ------------------------------------------------------------------------------

* Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C

* MCU:             PPC5777CMM03 2N45H CTZZS1521A

* Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz

* Debugger:        Lauterbach Trace32

* Target:          internal_FLASH

* Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A

* EVB connection:  eSCI_A is USBtoUART bridge (connector J21)

*

********************************************************************************

Labels (1)
Attachments
Comments

How have you selected the values for the test array in this example ? davidtosenovjan

static vuint32_t test[2] __attribute__ ((aligned (8))) =
{
    0xBABADEDA,
    0xABBAABBA
};

Please provide below info..
1. Is mandatory to have test address aligned to 8 bytes? Why?

2. In example code after configuring EIM, Read operation is used to generate the ECC error. can we use write operation? How it will differ?

3. How error injection will differ when I use 32-bit read/write compared to 64-bit read/write when test address not aligned to 8 bytes?

Regards,

Veeru

Hi, 

I have the same question. Did you get the answer for it, and why is it 8 byte alligned?

Also when we execute EIM.CH[EIM_chnl_PRAMC_0].EICHD_WORD1.R = 0x00000003;

is this instruction changing the bit in test[] ??

and what is happening in this function  Fix_2bit_error_RAM_data() is it actually correcting or just replacing with random data so as to remove the error?

Thank You,

Michael Jihan

 davidtosenovjan  Please Help

Hi, these are random data. ECC handling is customer specific, this is only example.

Version history
Revision #:
1 of 1
Last update:
‎09-17-2015 11:55 PM
Updated by: