Trusted Firmware for Cortex-A (TF-A) is an implementation of EL3 secure firmware. TF-A replaces PPA in secure firmware role.
Note: Please note the steps listed in this topic can only be performed with LSDK 18.12 and newer releases.
To migrate to the TF-A boot flow from the previous boot flow (with PPA), you need to compile the TF-A binaries, bl2_<boot_mode>. pbl and fip.bin , and flash these binaries on the specific boot medium on the board.
For SD/eMMC boot, you need to compile the following TF-A binaries.
TF-A binary name
Components
bl2_sd.pbl/bl2_emmc.pbl
BL2 binary: Platform initialization binary
RCW binary for SD/emmc boot
fip.bin
BL31: Secure runtime firmware
BL32: Trusted OS, for example, OPTEE (optional)
BL33: U-Boot/UEFI image
Follow these steps to compile and deploy TF-A binaries ( bl2_sd. pbl/bl2_emmc.pbl and fip.bin) on the SD/eMMC card.
Compile RCW binary
Compile U-Boot binary
[Optional] Compile OPTEE binary
Compile TF-A binaries ( bl2_sd. pbl/bl2_emmc.pbl and fip.bin) for SD/eMMC boot
Program TF-A binaries to the SD/eMMC card
Step 1: Compile RCW binary
You need to compile the RCW binary to build the bl2_sd.pbl/bl2_emmc.pbl binary.
Clone the rcw repository and compile the RCW binary.
$ git clone https://source.codeaurora.org/external/qoriq/qoriq-components/rcw
$ cd rcw
$ git checkout -b <new branch name> <LSDK tag> . For example, $ git checkout -b LSDK-20.04 LSDK-20.04
Compile RCW for Rev 1 or Rev 2 board.
For LX2160ARDB Rev1: $ cd lx2160ardb
For LX2160ARDB Rev2: $ cd lx2160ardb_rev2
If required, make changes to the rcw files.
$ make
The compiled RCW binary for SD/eMMC boot on LX2160ARDB for core frequency 2000 MHz, platform frequency 700 MHz and DDR memory data rate 2900 MT/s, with serdes1 = 19 serdes2 = 5 serdes3 = 2, rcw_2000_700_2900_19_5_2.bin is available at:
rcw/lx2160ardb/XGGFF_PP_HHHH_RR_19_5_2 (For LX2160ARDB Rev 1)
rcw/lx2160ardb_rev2/XGGFF_PP_HHHH_RR_19_5_2 (For LX2160ARDB Rev 2)
Note: See the rcw/lx2160ardb/README or rcw/lx2160ardb_rev2/README file for an explanation of the naming convention for the directories that contain the RCW source and binary files.
Step 2: Compile U-Boot binary
You need to compile the u-boot.bin binary to build the fip.bin binary.
Clone the u-boot repository and compile the U-Boot binary for TF-A.
$ git clone https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot.git
$ cd u-boot
$ git checkout -b <new branch name> LSDK-<LSDK version> . For example, $ git checkout -b LSDK-20.04 LSDK-20.04
$ export ARCH=arm64
$ export CROSS_COMPILE= aarch64-linux-gnu-
$ make distclean
$ make lx2160ardb_tfa_defconfig
$ make
Note: If the make command shows the error "*** Your GCC is older than 6.0 and is not supported" , ensure that you are using Ubuntu 18.04 64-bit version for building the LSDK 18.12 and above U-Boot binary.
The compiled U-Boot binary, u-boot .bin , is available at u-boot / .
Step 3: [Optional] Compile OPTEE binary
You need to compile the tee.bin binary to build fip.bin with OPTEE. However, OPTEE is optional, you can skip the procedure to compile OPTEE i f you want to build the FIP binary without OPTEE.
Clone the optee_os repository and build the OPTEE binary.
$ git clone https://source.codeaurora.org/external/qoriq/qoriq-components/optee_os
$ cd optee_os
$ git checkout -b <new branch name> LSDK-<LSDK version> . For example, $ git checkout -b LSDK-20.04 LSDK-20.04
$ export ARCH=arm
$ export CROSS_COMPILE=aarch64-linux-gnu-
$ make CFG_ARM64_core=y PLATFORM=ls-lx2160ardb
$ aarch64-linux-gnu-objcopy -v -O binary out/arm-plat-ls/core/tee.elf out/arm-plat-ls/core/tee.bin
The compiled OPTEE image, tee.bin , is available at optee_os/out/arm-plat-ls/core/.
Step 4: Compile TF-A binaries for SD/eMMC boot
Clone the atf repository and compile the TF-A binaries, bl2_sd. pbl/bl2_emmc.pbl and fip.bin .
$ git clone https://source.codeaurora.org/external/qoriq/qoriq-components/atf
$ cd atf
$ git checkout -b <new branch name> LSDK-<LSDK version> . For example, $ git checkout -b LSDK-20.04 LSDK-20.04
$ export ARCH=arm64
$ export CROSS_COMPILE=aarch64-linux-gnu-
Build BL2 binary with OPTEE.
For SD boot: $ make PLAT=lx2160ardb bl2 SPD=opteed BOOT_MODE=sd BL32= <path_to_optee_binary>/ tee.bin pbl RCW= <path_to_rcw_binary> / rcw_2000_700_2900_19_5_2.bin
For eMMC boot: $ make PLAT=lx2160ardb bl2 SPD=opteed BOOT_MODE=emmc BL32= <path_to_optee_binary>/ tee.bin pbl RCW= <path_to_rcw_binary> / rcw_2000_700_2900_19_5_2.bin
The compiled BL2 images, bl2.bin and bl2_sd.pbl/bl2_emmc.pbl are available at atf/build/lx2160ardb/release/ .
For any update in the BL2 source code or RCW binary, the bl2_sd.pbl/bl2_emmc.pbl binary needs to be recompiled.
To compile the BL2 binary without OPTEE:
For SD boot: $ make PLAT=lx2160ardb bl2 BOOT_MODE=sd pbl RCW= <path_to_rcw_binary>/ rcw_2000_700_2900_19_5_2.bin
For emmc boot: $ make PLAT=lx2160ardb bl2 BOOT_MODE=emmc pbl RCW= <path_to_rcw_binary>/ rcw_2000_700_2900_19_5_2.bin
Build FIP binary with OPTEE and without trusted board boot.
$ make PLAT=lx2160ardb fip BL33= <path_to_u-boot_binary> /u-boot.bin SPD=opteed BL32= <path_to_optee_binary> /tee.bin
The compiled BL31 and FIP binaries, bl31.bin , fip .bin , are available at atf/build/lx2160ardb/release/ .
For any update in the BL31, BL32, or BL33 binaries, the fip.bin binary needs to be recompiled.
To compile the FIP binary without OPTEE and without trusted board boot:
For SD boot: $ make PLAT=lx2160ardb fip BOOT_MODE=sd BL33= <path_to_u-boot_binary>/ u-boot.bin
For eMMC boot: $ make PLAT=lx2160ardb fip BOOT_MODE=emmc BL33= <path_to_u-boot_binary>/ u-boot.bin
To compile the FIP binary with trusted board boot, refer the read me at <atf repository>/plat/nxp/README.TRUSTED_BOO
Step 5: Program TF-A binaries to SD/eMMC card
Boot LX2160ARDB from FlexSPI. Ensure that the switches are set to boot the board from FlexSPI. For booting from FlexSPI:
SW1[1:8] = 1111 100X [X is 0 for FlexSPI NOR flash0 and X is 1 for FlexSPI NOR flash1]
SW2[1:8] = 0000 0110
SW3[1:8] = 1111 1100
SW4[1:8] = 1011 1000
Boot from FlexSPI NOR flash0: => qixis_reset
For LX2160ARDB Rev 1 , in boot log, you'll see:
Board: LX2160ACE Rev1.0-RDB, Board version: B, boot from FlexSPI DEV#0
For LX2160ARDB Rev 2, in boot log, you'll see:
Board: LX2160ACE Rev2.0-RDB, Board version: B, boot from FlexSPI DEV#0
Set up Ethernet connection
When board boots up, U-Boot prints a list of enabled Ethernet interfaces.
DPMAC2@xlaui4, DPMAC3@xgmii [PRIME], DPMAC4@xgmii, DPMAC5@25g-aui, DPMAC6@25g-aui, DPMAC17@rgmii-id, DPMAC18@rgmii-id, e1000#0
Set server IP address to the IP address of the host machine on which you have configured the TFTP server.
=> setenv serverip <ipaddress1>
Set ethact and ethprime as the Ethernet interface connected to the TFTP server.
Note: See LX2160ARDB Ethernet port mapping for the mapping of Ethernet port names appearing on the chassis front panel w ith the port names in U-Boot and Linux.
=> setenv ethprime <name of interface connected to TFTP server>
For example:
=> setenv ethprime DPMAC3@xgmii
=> setenv ethact <name of interface connected to TFTP server>
For example:
=> setenv ethact DPMAC3@xgmii
Set IP address of the board. You can set a static IP address or, if the board can connect to a dhcp server, you can use the dhcp command.
Static IP address assignment: => setenv ipaddr <ipaddress2> => setenv netmask <subnet mask>
=> setenv gatewayIP <gateway IP>
Dynamic IP address assignment: => dhcp
Save the settings. => saveenv
Check the connection between the board and the TFTP server.
=> ping $serverip
Using DPMAC3@xgmii device
host 192.168.1.1 is alive
Load TF-A binaries for SD boot from the TFTP server
Note: For details about the flash image layout for TF-A binaries, refer LSDK memory layout for TF-A boot flow.
Flash bl2_sd.pbl :
=> tftp 82000000 bl2_sd.pbl
=> mmc dev 0; mmc write 82000000 8 <blk_cnt>
Here, blk_cnt refers to number of blocks in SD card that need to be written as per the file size.
For example, when you load bl2_sd.pbl from the TFTP server, if the bytes transferred is 103353 (193b9 hex), then blk_cnt is calculated as "103353/512 = 201 (C9 hex)" + "few sectors for rounding up so that last block is not missed" . So, if you round up by 10 (A hex) sectors, for this example, mmc write command will be: => mmc write 82000000 8 D3
Flash fip.bin :
=> tftp 82000000 fip.bin
=> mmc dev 0; mmc write 82000000 800 <blk_cnt>
Here, blk_cnt refers to number of blocks in SD card that need to be written as per the file size.
Fo r example, when you load fip.bin from the TFTP server, if the bytes transferred is 1178967 (11fd57 hex) , then blk_cnt is calculated as "1178967 /512 = 2302 (8FE hex)" + "few sectors for rounding up so that last block is not missed". So, if you round up by 10 (A hex) sectors, for this example, mmc write command will be: => mmc write 82000000 800 908
Boot from SD card : => qixis_reset sd
LX2160ARDB will boot with TF-A. In the boot log, you will see:
=> NOTICE: BL2: v1.5(release):LSDK-20.04
NOTICE: BL2: Built : 22:01:10, Aug 20 2020
NOTICE: UDIMM 18ADF2G72AZ-3G2E1
NOTICE: DDR4 UDIMM with 2-rank 64-bit bus (x8)
NOTICE: 32 GB DDR4, 64-bit, CL=22, ECC on, 256B, CS0+CS1
NOTICE: BL2: Booting BL31
NOTICE: BL31: v1.5(release):LSDK-20.04
NOTICE: BL31: Built : 22:02:07, Aug 20 2020
NOTICE: Welc
U-Boot 2019.10 (Aug 14 2020 - 17:43:28 +0530)
SoC: LX2160ACE Rev2.0 (0x87360020)
Clock Configuration:
CPU0(A72):2000 MHz CPU1(A72):2000 MHz CPU2(A72):2000 MHz
CPU3(A72):2000 MHz CPU4(A72):2000 MHz CPU5(A72):2000 MHz
CPU6(A72):2000 MHz CPU7(A72):2000 MHz CPU8(A72):2000 MHz
CPU9(A72):2000 MHz CPU10(A72):2000 MHz CPU11(A72):2000 MHz
CPU12(A72):2000 MHz CPU13(A72):2000 MHz CPU14(A72):2000 MHz
CPU15(A72):2000 MHz
Bus: 700 MHz DDR: 2900 MT/s
Reset Configuration Word (RCW):
00000000: 50777738 24500050 00000000 00000000
00000010: 00000000 0c010000 00000000 00000000
00000020: 02e001a0 00002580 00000000 00000096
00000030: 00000000 00000000 00000000 00000000
00000040: 00000000 00000000 00000000 00000000
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 00027000 00000000
00000070: 08b30010 00150020
Model: NXP Layerscape LX2160ARDB Board
Board: LX2160ACE Rev2.0-RDB, Board version: B, boot from SD
Load TF-A binaries for eMMC boot from the TFTP server
Note: For details about the flash image layout for TF-A binaries, refer LSDK memory layout for TF-A boot flow.
Flash bl2_emmc.pbl :
=> tftp 82000000 bl2_emmc.pbl
=> mmc dev 1; mmc write 82000000 8 <blk_cnt>
Here, blk_cnt refers to number of blocks in SD card that need to be written as per the file size.
For example, when you load bl2_emmc.pbl from the TFTP server, if the bytes transferred is 103353 (193b9 hex), then blk_cnt is calculated as "103353/512 = 201 (C9 hex)" + "few sectors for rounding up so that last block is not missed" . So, if you round up by 10 (A hex) sectors, for this example, mmc write command will be: => mmc write 82000000 8 D3
Flash fip.bin :
=> tftp 82000000 fip.bin
=> mmc dev 1; mmc write 82000000 800 <blk_cnt>
Here, blk_cnt refers to number of blocks in SD card that need to be written as per the file size.
Fo r example, when you load fip.bin from the TFTP server, if the bytes transferred is 1178967 (11fd57 hex) , then blk_cnt is calculated as "1178967/512 = 2302 (8FE hex)" + "few sectors for rounding up so that last block is not missed". So, if you round up by 10 (A hex) sectors, for this example, mmc write command will be: => mmc write 82000000 800 908
Boot from eMMC card : => qixis_reset emmc
LX2160ARDB will boot with TF-A. In the boot log, you will see:
=> NOTICE: BL2: v1.5(release):LSDK-20.04
NOTICE: BL2: Built : 22:01:10, Aug 20 2020
NOTICE: UDIMM 18ADF2G72AZ-3G2E1
NOTICE: DDR4 UDIMM with 2-rank 64-bit bus (x8)
NOTICE: 32 GB DDR4, 64-bit, CL=22, ECC on, 256B, CS0+CS1
NOTICE: BL2: Booting BL31
NOTICE: BL31: v1.5(release):LSDK-20.04
NOTICE: BL31: Built : 22:02:07, Aug 20 2020
NOTICE: Welc
U-Boot 2019.10 (Aug 14 2020 - 17:43:28 +0530)
SoC: LX2160ACE Rev2.0 (0x87360020)
Clock Configuration:
CPU0(A72):2000 MHz CPU1(A72):2000 MHz CPU2(A72):2000 MHz
CPU3(A72):2000 MHz CPU4(A72):2000 MHz CPU5(A72):2000 MHz
CPU6(A72):2000 MHz CPU7(A72):2000 MHz CPU8(A72):2000 MHz
CPU9(A72):2000 MHz CPU10(A72):2000 MHz CPU11(A72):2000 MHz
CPU12(A72):2000 MHz CPU13(A72):2000 MHz CPU14(A72):2000 MHz
CPU15(A72):2000 MHz
Bus: 700 MHz DDR: 2900 MT/s
Reset Configuration Word (RCW):
00000000: 50777738 24500050 00000000 00000000
00000010: 00000000 0c010000 00000000 00000000
00000020: 02e001a0 00002580 00000000 00000096
00000030: 00000000 00000000 00000000 00000000
00000040: 00000000 00000000 00000000 00000000
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 00027000 00000000
00000070: 08b30010 00150020
Model: NXP Layerscape LX2160ARDB Board
Board: LX2160ACE Rev2.0-RDB, Board version: B, boot from eMMC
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