For the CM33 of LPC55S6x family, the trust zone module is integrated, the memory space and peripherals are classified as security and non-security space. In order to generate interrupt in non-security mode, the NVIC module including the NVIC_ITNSx register must be initialized in security mode so that interrupt module can generate interrupt in non-security mode. The example demos that MRT0 module generates interrupt in non-security mode, the NVIC module is initialized at security mode, MRT0 is initialized at non-security mode. The project is based on MCUXpresso IDE ver11.1 tools, LPC55S69-EVK board and SDK_2.x_LPCXpresso55S69 SDK package version 2.11.1.

This content was originally contributed to lpcware.com by Dirceu Rodrigues Introduction My work evaluating the SCT peripheral with the Hitex LPC4350 board (ARM Cortex-M4/M0) included the generation of non standard PWM signals for use in Power Electronics. At the end, some results would be compared with solutions based on LPC1114 (Cortex-M0), for example.  The first idea was to apply a concept that I had used when developing universal controllers for laser printer fuser, at 2001. This is a gate drive for MOSFET / IGBT isolated by pulse transformers. Two pulses Gate Drive – LPC1114 solution The circuit is implemented with pulse transformers (20 kHz PWM frequency) using the gate-source capacitance as memory. A Schottky diode avoids the stored charge to leak through windings. Thus, it's possible to achieve duty-cycles near to 0 and 100 %, simply applying 1 µs pulses shifted in time - one for charge, other for discharge. A very simplified schematic is shown in Figure 1.       Figure 1. Simplified circuit. My solution for the LPC1114 - Cortex-M0, uses two timers in a different scheme: Phase-out or lead/lag the counter values. With CT32B0 and CT32B1 32 bit timers, the behavior, including the pulsed outputs, is better understood looking on Figures 2 and 3 for duty-cycles of 75% and 25%. As opposed to common solutions, for each timer, the MR0 and MR1 matching registers values are constant. The difference between them is equivalent to pulse width (1 µs). The MR0 value also defines the period. The duty-cycle it’s determined through the expression:   DC = TC1 / MR0                                   (1) Where, TC1 is the CT32B1 timer value when this one, for the CT32B0, is zero.      In order to change the duty-cycle, the code in foreground task establishes a new TC1 and enables the CT32B0 overflow interrupt, where  this value is effectively loaded on CT32B1 timer in a safe point (to avoid jitter and other dangerous edges on outputs). Also, the CT32B0 ISR disables itself at the end, ensuring low interrupt overhead. For safety, the first applied pulse is a “discharge pulse”. This solution was proven driving a 930 W (120V/8.7 A) single-phase induction motor and it can be seen in reference [1], using a synchronous AC version of circuit shown in Figure 1 (no diode, four mosfets).      Figure 2. LPC1114 Two Pulses Gate Drive solution - DC 75%.  Figure 3. LPC1114 Two Pulses Gate Drive solution - DC 25%.      Two pulses Gate Drive – LPC4350 SCT solution The equivalent SCT implementation for the Two Pulses Gate Driver has the advantage of saving one timer. The pulse generation can be accomplished through a Mealy finite state machine plus the companion SCT counter. The LPC4350 generates 1 µs pulses with repetition rate of 20 kHz on CTOUT_4 and CTOUT_5 outputs. Two pushbuttons allow that a falling edge on CTIN_2 input, start the timer and a low value on CTIN_6, stop it. The counter operates as a unified 32 bit timer (UNIFY = 1) counting up and down (BIDIR = 1). ADC0 input is used to read the voltage on R26 potentiometer. So, the firmware can convert it in PWM change. As for LPC1114, the LPC4350 core and SCT runs in 48 MHz. Register MATCH 0 defines half-period. The difference between MATCH 2 and MATCH 1 registers is equivalent to pulse width (1 µs). In other words: PULSE_WIDTH = MATCH 2 - MATCH 1                       (2) Despite this difference be constant, now the MATCH 2 and MATCH 1 contents must change at the same time. Figures 4 and 5 show the waveforms for duty-cycles 15 % and 85 %. For example, the duty-cycle can be determined through the expression: DC = 1 – (MATCH 1 + 0.5*PULSE_WIDTH )/ MATCH 0        (3) Figure 4. SCT Two Pulses Gate Drive solution - DC 15%. Note: In companion source code, the PULSE_WIDTH is referred as PULSE_LENGTH. Figure 5. SCT Two Pulses Gate Drive solution – DC 85%. In order to achieve this behavior, one simple Finite State Machine with two states has been defined (Table 1): STATE Meaning 0 CTOUT_4 pulse generation 1 CTOUT_5 pulse generation Table 1. Definition of states. Figure 6 illustrates the relationship between the counter, states and interrupts. The PWM updating scheme takes advantage of following SCT property (as stated on User Manual): “A MATCH register is loaded from the corresponding MATCHREL register when BIDIR is 1 and the counter reaches 0”. In this application, the ADC0 interrupts MCU in a 24 Hz rate, triggered by TIMER0 MR0 (EM0 rising edge). The code on this ISR determines the new MATCH 1, saves it on global variable match1 and enables the SCT interrupt associated with event “counter reach limit” - in fact, event for MATCH 0. Here note, as stated in expression (3), that DC depends only on MATCH1, since MATCH 0 is constant. The ISR code for MATCH 0 event, updates MATCHREL 1 and MATCHREL 2 registers based on variable match1. Also disables the associated interrupt for low overhead. When counter reaches 0, the MATCH 1, 2 registers will be reloaded from the MATCHREL 1, 2 values automatically. This procedure should avoid jitter and other dangerous edges on outputs. Note that MATCH registers are never handled by software when counter is running. The new desired values are indirectly loaded on MATCHREL registers. The first values for MATCH registers are intentionally unreachable (> MATCH 0). This ensures that only ADC readings brought useful values to them. The on board potentiometer generates a voltage from 0 V to 3.3 V, which translates to 0 – 1023 range by the 10 bit AD converter. The MIN_MATCH1 and MAX_MATCH1 predefined values equates to 36 and 1116 (equivalent to duty-cycle 5 % and 95 % DC). Therefore, the software relates ADC0 voltage to with match1 variable approximately through the expression: match1 = [(MAX_MATCH1 - MIN_MATCH1)*ADC0] / 1024 +            (4)                                                  MIN_MATCH1 Note: In the companion source code, the division by 1024 is performed with a 10 bit right shift.           Figure 6. PWM updating scheme - DC 50%. Table 2 lists the eight states comprising the state machine for the current application. The companion state transition diagram is showed on Figure 7. Here, note other SCT important property, as stated on User’s Manual: “If more than one event associated with the same counter occurs in a given clock cycle, only the state change specified for the highest-numbered event among them takes place”. This applies to events 6 and 7. In normal operation, the event 6 happens periodically in State 1; but when a pushbutton press causes a low level on CTIN_6, the event 7 is fired on State 1 and counter is stopped. The state is driven to 0, with the outputs cleared (until one falling edge on CTIN_2 initiates the counting). EVENT ID Happens in state Conditions Actions 0 0 Falling edge on CTIN_2 Start counter 1 0 Counter reach MATCH 1 when counting up Set CTOUT_4 (pulse rise) 2 0 Counter reach MATCH 2 when counting up Clear CTOUT_4 (pulse fall) 3 0 Counter reach MATCH 0 Limit counter (defines the half period) Int. to update MATCHREL 1/ 2 Change to STATE 1 4 1 Counter reach MATCH 2 when counting down Set CTOUT_5 (pulse rise) 5 1 Counter reach MATCH 1 when counting down Clear CTOUT_5 (pulse fall) 6 1 Counter reach MATCH 3 (0) MATCH 1/ 2 automatic reloading Change to STATE 0 7 1 Counter reach MATCH 3 (0) AND Low value on CTIN_6 Stop counter MATCH 1/ 2 automatic reloading Change to STATE 0 Table 2. Definition of states. Figure 7. State transition diagram. Conclusion The PWM generation carried out by two short pulses shifted in time is a good alternative when isolation and duty-cycles far from 50% are required - specially driving gate charge devices like Mosfet/IGBT. The main advantage over opto-isolated implementations is not necessary create an auxiliary power supply.  Regarding to the architecture, the designer can use microcontrollers equipped with UP/DOWN timers (bidirectional), but is required some external glue logic in order to generate those short pulses. In comparison with the LPC1114 presented solution, the SCT version consumes just one timer/counter. As shown, the SCT peripheral is very independent, resulting in low (or no) MCU intervention after an initial configuration. This simple application used only two inputs, two outputs, two states and eight events. For more complex designs, the SCT provides up to 8 inputs, 16 outputs, 16 events and 32 states. I’ve future plans to make other power electronics applications based on SCT, including a small dot matrix printer controller. Code Red company   provides a tool to draw state diagrams and automatically generate code for the SCT engine, called Red State [2] (not used in this application). Finally, I would like to thank David Donley from NXP, who assisted me by answering my technical enquiries about the State Configurable Timer and suggesting improvements on code. References     [1]    http://www.youtube.com/DirceuRodriguesJr     [2]    http://www.code-red-tech.com/lpcxpresso

NXP’s Arm® Cortex®-M33 based LPC551x MCU Family Enhanced Security & Performance Efficiency

In this document, I will explain how to create a project to use the SPIFI library version 1.03 with the LPC4370. For this we will need the following tools: MCUXpresso IDE 10.2. Link LPC-LINK2 to use it as an evaluation board for the LPC4370. Link External debugger. In my case, I used another LPC-LINK2 board. LPCOpen v2_12 for the LPC4370, this version comes with the installation of MCUXpresso IDE. SPIFI library v1.3. Link Code Example lpcopen_2_12_lpcxpresso_ngx_xplorer_1830_SPIFI_v1.0. Link First, download and install all the tools needed. In your workspace of MCUXpresso we will import (1) three projects of the LPCOpen v2_12 for the LPC4370: periph_blinky, lpc_board_nxp_lpclink2_4370 and lpc_chip_43xx.  The LPCOpen zip file is in the next path of your PC: C:\nxp\MCUXpressoIDE_10.2.1_795\ide\Examples\LPCOpen (2) Extract the files of the zip named lpclibspifi_lpcxpresso_1.03_68 that we downloaded before. The folder that we need is spifilib_m4f. Drag and drop this folder into the Project Explorer on your workspace of the LPC4370, after choosing copy and you should see the spifilib_m4f in your Project Explorer. Once you imported correctly the SPIFI library, select the library (1) on the project explorer window and build it (2). Once you do this you should see that a new folder called Debug appear (3). Now we need to edit the properties of the periph_blinky example to add the library spifilib_m4f to the project. To do this, right click on the project and click properties. Once in the properties window click on C/C++ Build (1) > Settings (2) > Includes (under the section MCU C Compiler) (3). In the includes window click Add… (1) > Workspace (2) > spifilib_m4f (3) > inc (4) > click OK (5) on the window Folder Selection > click OK (6) on the window Add directory path. You should see the following on the include paths. Now, go to the libraries (1) option under the section MCU Linker, on the section Libraries (-I) click Add… (2) finally write the name of the library (spifilib_m4f) (3) and click OK (4). Under the section Library search path (-L) click Add… (1) > Workspace (2) > spifilib_m4f (3) > Debug (4) > OK (5). If you see the same as shown in the below image you are good to go so click Apply and close. To check if you did the below steps correct let’s do the following. On the project periph_blinky in the file systick.c include the file spifilib_api.h and compile the project. If the project compiles without problems it means that you imported correctly the spifi library. If you found problems please stop and repeat all the steps mentioned before. Now that we added successfully the library we can start to migrate the example for the LPC1830 that we download before. First, unzip the file lpcopen_2_12_lpcxpresso_ngx_xplorer_1830_SPIFI_v1.0. Once you unzipped the file go to the following path: spifilib_blinky > example > src. Open the file named Blinky.c and copy all the content of the file. Now go to the file systick.c on your workspace of MCUXpresso within the project periph_blinky, delete all the content of this file and paste what you copied before. Do not compile at this point or you will receive multiple errors! Go back to the path spifilib_blinky > example > src on your PC. Drag and drop the file called spifi_setup.c into the folder src of your project periph_blinky on your Workspace. Open the file that we just copy into our workspace and go to line 46 of the code. Here we are creating a buffer of 64KB that we will use later to write in the SPIFI. The __BSS(RAM3) is to save this buffer in the RAM block three of memory. The problem here is that the block of RAM3 in the LPC4370 is not big enough to store the buffer of 64KB (see below image), so let’s change this for either RAM or RAM2 that are big enough to store the buffer. Now that we added the spifi_setup file let’s go back to the systick.c file and add the external declaration for the function spifiSetUp. At this point, if we compile the project we shouldn’t see any problems, only some warnings because of the functions and variables that we are not using. We are almost done, we are missing the most important thing. With this demo you will be writing, deleting and reading the SPIFI memory, this means that you cannot be executing form the SPIFI flash memory. You need to move to the RAM memory all the functions that are going to make this. This is the reason why in the file systick.c we don’t have any function that interacts directly with the SPIFI, this will make much easier the work of moving all the functions that interact with the SPIFI memory to RAM. The function spifiSetUp is the one that will make all the tests on the SPIFI and it is in the spifi_setup file, so we will need to move this entire file to RAM along with the SPIFI library. We will use three different scripts to move the library and the file spifi_setup to RAM. You can learn more about this in the following community post: https://community.nxp.com/thread/389110. First, right click on the folder of the project > new > folder, the name of the folder must be linkscripts. According to the sections Relocating particular objects into RAM and Relocating particular libraries into RAM of the community post mentioned before we need to create three files in this new folder: main_text.ldt, main_rodata.ldt and main_data.ldt. To do this, right click on the folder linkscripts > new > file. Here is the content that you should have on the three files that we just created. Do not include on the files the text that is in bold, that's just for reference! File main_data.ldt *libspifilib_m4f.a:(.text*) *libspifilib_m4f.a:(.rodata .rodata.* .constdata .constdata.*) *spifi_setup.o(.text*) *spifi_setup.o(.rodata .rodata.* .constdata .constdata.*) . = ALIGN(${text_align}); *(.data*) File main_rodata.ldt *(EXCLUDE_FILE(*libspifilib_m4f.a: *spifi_setup.o) .rodata) *(EXCLUDE_FILE(*libspifilib_m4f.a: *spifi_setup.o) .rodata.*) *(EXCLUDE_FILE(*libspifilib_m4f.a: *spifi_setup.o) .constdata) *(EXCLUDE_FILE(*libspifilib_m4f.a: *spifi_setup.o) .constdata.*) . = ALIGN(${text_align}); File main_text.ldt *(EXCLUDE_FILE(*libspifilib_m4f.a: *spifi_setup.o) .text*) After finishing with the three files you are done with the demo! It’s important to mention that if you want to go inside the function spifiSetUp while debugging you need to set a breakpoint inside the function. While debugging we can see that before calling the function spifiSetUp we are running from the SPIFI flash memory and once we enter to the function we are running from RAM memory. Once we run the demo successfully we should see the following in a terminal and the LED1 will be blinking. Hope this guide is helpful! Best Regards, Victor.

Contents     Introduction to OPAMP. ........................................1     Usage of LPC5536-OPAMP. ................................2 2.1 Follower OPAMP. .................................................2 2.2 Non-inverting OPAMP. .........................................3 2.3 Differential OPAMP. ..............................................3     Test Preparation of LPC5536-EVK. ......................4     Test Result ............................................................5 4.1      Follower Test ....................................................6 4.2      Non-inverting Test ............................................7 4.2.1 Error Analysis. ...................................................7 4.2.2 Gain Error and Output Offset Error ...................8 4.2.3 OPAMP Output Error .........................................9 4.4 Differential Test ...................................................10     Conclusion. .........................................................11   The Article shows the OPAMP performance test that the precision of LPC5536-OPAMP matches the description in the product data sheet. The gain error is less than 5%, and the input offset voltage is less than 5mV, which can meet the presicion need to a certain extent. It is worth mentioning that the output error of LPC5536-OPAMP is very small at low magnification. For example, the full-range error is just single-digit mV at the magnifications of 2X and 5X in non-inverting mode. For scenarios requiring higher precision, users can connect the external high-precision resistors to achieve higher output precision.  The article includes detailed test steps and EVK board settings. For detail, see attached article.  

经常有客户在使用LPC55S69的过程中遇到读 Flash进入异常HardFault中断的现象。如果在Flash Mass Erase之后从未对Flash扇区进行过写操作，直接用指针通过AHB读Flash地址会导致程序跳入HardFault 中断而无法继续正常运行。 原因    刚出厂的LPC55Sxx FLASH处于全零的全擦除状态，没有设置ECC。当芯片通过LinkServer 和MCUXpresso IDE建立连接时，先擦除要下载代码用到的扇区，再把代码下载到对应位置，并对相应存储区的ECC值同时进行更新。代码以外的区域仍然是无ECC设置的擦除状态。 当LPC55Sxx 通过AHB总线直接读取Flash内存区域时（例如，mytemp = *(uint32_t*)0x4000）要对Flash ECC进行校验。这一指令对于读有效代码区是没有问题的， 因为这一区域的ECC在下载代码时早已设置好。但是一旦读取没有代码的扇区，由于没有检测到正确的ECC，导致Flash读取失败，并跳转到下图中的HardFault_Handler()异常中断：   我们在Sector Erase后通过AHB读取Flash内存内容，也会遇到同样的HardFault异常跳转，出问题的原因都是一样的。 解决方法 针对这一问题我们有如下两种解决方法： 先执行Flash写操作，再读取Flash 与Flash 擦除操作不同，执行Flash写操作后对应的ECC值也同步更新。这样，ECC校验通过后，通过下面的代码就可以对Flash直接进行AHB读取。 volatile uint32_t mytemp; …… mytemp = *(uint32_t*)0x1000;//read memory content 0x1000 to mytemp 请注意：0x1000必须是一个已经写过的地址。 如果Flash的某个扇区处于被擦除的状态，我们只需要在通过AHB总线读取内存区域之前对该区域执行写操作，这样ECC校验位更新正确后，就可以正常读Flash。 Flash的写操作可以参考MCUXpresso SDK自带的flashiap例程，函数FLASH_Program。   使用Flash控制指令读取Flash区内容 使用Flash控制指令进行读操作不会导致硬件错误（请参阅UM11126 “Command listing (CMD)”章节）。这是用户手册中推荐的读Flash正确打开方式。 请注意：CPU只有在频率低于100MHz时，才能进行Flash操作（读，写，擦除，校验，等等），当CPU频率超过100MHz时是不能实现上述操作的。 目前，官方没有提供上用控制指令读取Flash内容的例程，因此需要您根据下面步骤创建自己的读Flash程序。 开发环境： IDE: MCUXpresso IDE v11.1.0 SDK MCUXpresso SDK v2.7.0 步骤： 在MCUXpresso IDE中导入一个基础例程，如led_blinky 在下图所述选项中添加iap组件   选择iap1,点击OK   点击完OK之后，fsl_iap_ffr.h, fsl_iap.c, fsl_iap.h文件将自动添加到工程中   在source文件夹中添加附件中的memory.h和memory.c文件   4) 使用Flash 控制指令时，需要在源文件中添加memory.h, fsl_iap.h   5) 调用memory初始化和memory读取函数   6）调试，单步执行（step over）到memory_read()，查看结果  

This document explains how to start with LPCXpresso845-MAX Evaluation Board building, running and debugging example codes. Introduction   Based on the ARM Cortex-M0+ core, LPC84x is a low-cost, 32-bit MCU family operating at frequencies of up to 30 MHz. The LPC84x MCU family supports up to 64 KB of flash memory and 16 KB of SRAM. There is no LPCOpen nor SDK for LPC84x, however there is an example code bundles (register level) available for this family. The example code bundles offer a fastest, and simplest way for user to learn how to program each peripheral before progressing to more advance features of the peripheral. New users of LPC84x can step through the Example Code like a tutorial. Each project contains concise and accurate explanations in Readme files and comments in source files help the user to start/debug quickly. LPC845 Example Code Bundle is available for KEIL, MCUXpresso and IAR IDEs and you can download it from next link:   http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/lpc-cortex-m-mcus/lpc800-series-cortex-m0-plus-mcus/low-cost-microcontrollers-mcus-based-on-arm-cortex-m0-plus-cores:LPC84X?tab=Design_Tools_Tab Build, run and debug an example   This section describes the steps required to build, run, and debug an example application. 1. Download the LPC845 Example Code Bundle MCUXpresso from the next link:  http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/lpc-cortex-m-mcus/lpc800-series-cortex-m0-plus-mcus/low-cost-microcontrollers-mcus-based-on-arm-cortex-m0-plus-cores:LPC84X?tab=Design_Tools_Tab 2. Open MCUXpresso IDE. 3. Select "Import project(s) …" from the Quickstart Panel. 4. Click the "Browse" button and point to the LPC845-Example-Code-Bundle-MCUXpresso.zip, which should be downloaded previously, and then click “Next” button. 5. By default all the projects are selected, however you can select only the desired example project. In order to build the example project, it is necessary to add in the workspace the following projects: common peripherals_lib utilities_lib For this document, we are using the Multi_Timer_Blinky example project. 6. Build the project using the hammer icon on Quickstar Panel.  7. Connect the development platform to your PC via USB cable. If connecting for the first time, allow some seconds for the devices to enumerate.   8. This example runs from Flash. To run this code you have two options: a) Download and Debug.    b) Load to flash using the “run” IDE icon and press the reset button on the board. Note: It may be necessary to power-cycle the board in order to regain control of the reset button after programming. At this moment, you can be able to run or debug the example project. I hope this helps!!!

Link to board: http://www.lpcware.com/content/devboard/android-open-accessory-aoa-kit Android Demos There are three demos available for download on the Embedded Artists website http://embeddedartists.com/products/app/aoa_kit.php The code bundle contains the following: Demo 1: Android Open Accessory demo which lets you control and monitor the AOA Board (LPC1769 side) from an Android device. Demo 2: Android Open Accessory demo which lets an Android device detect CAN nodes (such as the LPC11C24 side of the AOA board) in a CAN network. The CAN nodes can be controlled and monitored from the Android device. Demo 3: Android Open Accessory demo which lets an Android device detect Xbee nodes in an Xbee network. The Xbee nodes can be controlled and monitored from the Android device. FreeRTOS has been ported to the board and a demo is available that show how to use it. lwIP v1.4.0 has been ported to the board. The httpserver_raw (webserver) application from the lwIP contrib package is available with a small modification to use the on-board SD-card interface instead of the ROM based file system. FatFs file system module has been ported to the board. The lwIP demo (based on httpserver_raw) is using this module to access files on an SD card. nxpUSBlib is available and used in the AOA demos. How to setup the projects in LPC Xpresso Make sure that the latest version of the LPCXpresso IDE is installed. Download the package of sample application projects into the Eclipse workspace. The package can be downloaded (as a zip-file) from Embedded Artists’ support page after registering the product. The zip-file contains all project files and is a simple way to distribute complete Eclipse projects. Start the LPCXpresso IDE and select a new (and empty) workspace directory. Select the Import and Export tab in the Quickstart Panel and then Import archived projects (zip), see Figure 1 below. Browse and select the downloaded zip file containing the archived sample applications. Select all sub-projects to be imported, see Figure 2 below. By default the NXP USB library has been configured for USB device only. This needs to be changed to USB host. Right click on the nxpUSBlib project and select Build Configuration, then Set Active. In the list select LPC17xx_Host. See Figure 3. The projects are now imported. Click (to select) the project to work with. Click Build in the Quickstart Panel (under Start Here). See Figure 4 There is also a video on how to setup Demo 1 and get it running by connecting your android device. (Getting started video provided by Embedded Artists) http://www.youtube.com/watch?v=l3f2ss1IdV0&feature=player_embedded

  需求： 客户需要对Image文件做出完整性检测，利用IDE固有功能添加这类信息简便且可靠，以往有类似的link提到了这些配置，对于LPC55系列，需要做一些更新。 CRC Checksum Generation with MCUXpresso IDE - NXP Community Solution 基于MCUX环境 下载 SRecord http://srecord.sourceforge.net/ srec_cat.exe是下载后我们主要使用的工具，通过为其添加一个系统变量名，将SRecord目录加入系统路径     重启MCUX IDE之后可以在工程配置中看到该变量：       创建一个脚本文件crc_add.txt，放在debug目录下，用于填充app后的flash空余位置为0xFF, 并后续生成CRC32值并放置0x00037FFC位置。最终生成的srec文件为包含所有内容的image。           # srec_cat command file to add the CRC and produce application file to be flashed # Usage: srec_cat @filename #first: create CRC checksum lpcxpresso55s06_hello_world_image_length_MCUX.srec # input file #-fill 0xFF 0x00000000 0x00038000 # fill blank code area with 0xff from 0x00000000 to 0x00038000 (0x00038000是把LPC55S06的末尾地址稍往前提，实际因为0x0003D7FF） -fill 0xFF 0x00000000 0x00037FFC #填充0-0x37FFC区间的未用地址为0xff -crop 0x00000000 0x00037FFC # just keep code area for CRC calculation below , 保留这段区间的内容，排除除此范围内的其他数据 #-CRC16_Big_Endian 0x00037FFE -CCITT # calculate big endian CCITT CRC16 at given address.， 为以上空间数据计算CRC16，并放置在0x00037FFE地址，2字节 -CRC32_Little_Endian 0x00037FFC -CCITT #CRC32 -crop 0x00037FFC 0x00038000 # keep the CRC itself #second: add application file lpcxpresso55s06_hello_world_image_length_MCUX.srec # input file -fill 0xFF 0x00000000 0x00037FFC # fill code area with 0xff -crop 0x00000000 0x00037FFC #-crop 0x10000000 0x10000170 0x10000172 0x10010000 #keep all except CRC #finally, produce the output file -Output # produce output lpcxpresso55s06_hello_world_image_length_MCUX_crc.srec      创建一个crc_file_convert.txt文件，也放在debug目录下，用于将上一步生成的最终image的srec文件转换为bin文件，用于生成或者比对 # srec_cat command file to add the CRC and produce application file to be flashed # Usage: srec_cat @filename #third: create bin file lpcxpresso55s06_hello_world_image_length_MCUX_crc.srec -o lpcxpresso55s06_hello_world_image_length_MCUX_crc.bin -binary 在IDE的Post build栏目添加如下命令：     arm-none-eabi-size "${BuildArtifactFileName}"   默认自带的统计image size功能 arm-none-eabi-objcopy -v -O binary "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.bin"    将image转成bin文件，用于后续使用和比对 arm-none-eabi-objcopy -v -O srec "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.srec" & srec_cat.exe @CRC_add.txt 填充image，计算CRC32，整合成新的srec image srec_cat.exe @CRC_file_convert.txt  将上一步得到的srec image转化为bin文件，用于后续使用和比对   《hello_world_image_length_MCUX》例程会自行统计应用程序的CRC32值，并于IDE产生的CRC32值做比对   这里需要注意的是，由于MCUX IDE是借助于外部工具来填充flash和计算CRC32，所以默认IDE调试和下载选择afx文件并不包含这些信息。当校验程序开始运行，会发生： 读写未写入的flash，对于LPC55系列会发生hardfault CRC32值并不存在 所以测试这个程序需要单独下载包含所有的srec文件或者bin文件，而不是默认的afx文件。      

In newer version of LPC Boot ROM , checksum is added in location 7 ( offset 0x0000001C in vector table ) of Boot ROM. For some LPC device, for example LPC8N04, older Boot ROM version 0.12 (equipped in Rev B board) doesn’t contain checksum but newer version 0.14( equipped in Rev C board ) adds it. Boot ROM checksum is a criteria for valid user code. Bootloader can jump to user code only when detects checksum value correct. Otherwise, it stays at boot code.   Scenario: User may have this annoying problem: the program runs well if download code to LPC flash with debugger. However power off and on again, the code won’t run any more. If you also experience same in field, you may consider the possibility of Boot ROM checksum failed. This document tells how overcome this problem. 1. calculate checksum value by hand 2. calculate checksum value with Keil elfdwt.exe For detail, see attached article.

Description This is a demonstration-only design of a Point Of Sale (POS) system using the NXP LPC2214FBD144. Fiscal Cash Register (FCR) is a kind of POS machine which is popularized by governments, in particular, in China. A tax control function is added to the POS machine for revenue supervision. Considering the national standard and function expansion and complexity, an ARM MCU is used in the application market. The LPC2214 is the central control unit of the system. The system consists of an LCD, NAND flash, keypad, printer, RTC, IC card, etc. The FCR demonstration system is divided into two boards. The first is the NXP LPC22xx development board. On this board, general peripheral resources are integrated such as external flash and SRAM, keypad, ethernet, LCD, USB, CF card, and IDE. This can be considered as the motherboard used for the overall application. The FCR-specific resources such as NAND flash, UART, printer, and IC card are on the extended board. If more resources are needed, just replace the extended board. In the system, the LCD module is needed to display the operation and the keypad is used to send commands to the system. NAND flash is used to store the business data and the DOT Matrix printer is used to print the invoice. The IC card is used for security. The POS demo system demonstrates the functions which are important in a complete FCR system. The demo system can be used for software development and can help in reducing the development cycles and time to market. Block Diagram Products Below are recommended microcontrollers for use in implementing this design to a system. More Information Images Working Prototype Point of sale Schematics Example Codehttp://www.lpcware.com/sites/default/files/example.code__3.zip Disclaimer This design example shows possible hardware and software techniques used to implement the design. It is imperative that the viewer use sound engineering judgment in determining the fitness of this design example for any particular application. This design example may include information from 3rd parties and/or information which may require further licensing or otherwise. Additional hardware or software design may be required. NXP Semiconductors does not support or warrant this information for any purpose other than an informational design example. schematics.zip 151.79 KB example.code_.zip 602.53 KB

This article mainly introduces how to config CTIMER match 3 trigger ADC in LPC804, includes how to config related registers, and the code under SDK. Other LPC serials, also can refer to this DOC. 1.How To Configure ADC Part. 2.How to Configure CTIMER Part 3.Project Basic Information 4.Reference   Project is attached, it base on MCUXpresso IDE v11.1.1,  LPCXpresso804 board.  

For the LPC8xx family, the peripheral module input or output signals are not connected to external pads fixedly as most processor does . With SWM module, the peripheral module input or output signals can be routed to any external GPIO pins via software configuration There is special requirement that one peripheral output signal functions as the input signal of another peripheral, in the case, the peripheral output signal and the peripheral input signal can be routed to the same pad via SWM so that the input and output signals are connected internally without external cable. The LPC802 has ACOMP module, CTimer module and SWM module, per customer requirement, the ACOMP output signal and CTimer0 capture 0 input signal can be routed to the same GPIO pin without external connection so that the ACOMP output signal can trigger CTimer0 capture 0 event internally. In the doc, I give the code to configure the CTimer, ACOMP and the SWM, explain the configuration,introduce the tools, board and result.  

Previously, I wrote two articles about LPC55xx AHB read ( How to fix AHB Read HardFault Error) and LPC55xx FLASH alignment (Why FLASH Program cannot Success? ). In this article, we will go on investigating LPC55xx erased memory state. For most of NXP MCU, the erased FLASH state is 0xFF. Writing action is to change 1 to 0. However for LPC55, when we perform mass erase or section erase, we see the related memory turns to all 0 in MCUXpresso IDE debugger Memory view. This all-0-erased-status confuses many LPC55 beginners. Is this real memory state? The answer is yes, IDE debugger display is correct. LPC55xx FLASH uses 0x00 as erased value, which is opposite to most of the other FLASH devices which use 0xFF as erased value) There is no way to verify the erased FLASH state with code in runtime. NXP enhanced LPC55xx FLASH with ECC added. This means that there is now a functional block between the read entity (for example the CPU) and the FLASH itself. When erasing, both the erased FLASH and its ECC are set as 0. The reading can’t be successful if the erased memory and its ECC don’t match. Thus we can’t read memory in erased state. AHB read hardfault error is produced if do so.  Because of ECC mechanism, you can't read FLASH until you have written to it. see  How to fix AHB Read HardFault Error The User's Manual mentions the reading and writing operation in UM11126 chapter 5.7.13: When writing, parity is automatically computed and stored alongside user data. When reading, data and parity are used to reconstruct correct data, even in the case of a 1-bit error. When reading an erased location, an uncorrectable error is flagged. Use the “blank check” command to test for successful erase. The LinkServer debug in MCUXpresso IDE takes some precautions to avoid this problem while programming the FLASH before starting a debug session. That’s the reason we can see erased memory state in debugger memory view window, Admittedly, this is something not really pre-eminent in the documentation. The only reference we could spot is in UM11126. See below: “ The selected pages are checked for the erased condition (all 0 including parity)”   Thanks for the valuable comment from Radu Theodor Lazarescu.

1.     Problem description When we debug a new designed LPC55 custom board through SWD, if IDE throws out error messages such as connection failure or no available device being found, normally we must check below two points: Whether the debug circuit design is correct.（https://community.nxp.com/t5/LPCXpresso-IDE-FAQs/Design-Considerations-for-Debug/m-p/469565#M44） Whether LPC55 power supply system is correct. Regarding to the second point of power supply system, we received many feedback from customers that even they read UM for times they still can’t well-understand LPC55xx DCDC power supply system. Therefore we prepare this article to analyze LPC55xx power supply circuit and introduce detection method. 2.     Problem Analysis The difference of power supply circuit between LPC55xx series and other LPCs is that LPC55xx uses DCDC circuit inside to provide core voltage. It lowers the input 1.8V-3.6V voltage to around 1.1V to supply LPC55xx internal system. The DCDC converter is efficient and reduces the internal power consumption. The disadvantage is that it generates a certain ripple. LPC55xx power supply circuit is as follows: In order to analyze, We divide LPC55xx power supply circuit into 4 regions and will introduce them one by one according to the different functions.   1)  Input voltage: In this part, VBAT_PMU provides input voltage to RTC and internal analog components. VBAT_DCDC provides input voltage to internal DCDC circuit. 2)  A set of filter capacitors: To filter out the burrs and glitch at the voltage input. 3)  DCDC circuit: Work with LPC55xx internal DCDC circuit together to generate 1.1V output voltage. 4)  VDD_PMU: Provides the 1.1V output voltage of the DCDC circuit to the LPC55xx core. Note: The design of region 3 is to work with the internal DCDC converter. The inductance L1 of 4μ7H and the capacitance C1 of 22μF are calculated by LPC55xx internal circuit. When designing, we must strictly follow the parameters recommended in the manual, otherwise DCDC circuit can’t work normally. 3.     DCDC Circuit Detection LPC55xx power supply system current direction is shown in the diagram below. See arrow in red. In order to ensure the normal operation of the DCDC circuit, the following two detection points are recommended. 1)  Detection point 1: External 1.8 to 3.6V voltage input, normally it’s 3.3V. 2)  Detection point 2: Output of the DCDC converter. If the DCDC works normally, we can get 1.1V voltage output here. The output voltage supplies power to the core components such as the central processing unit through the VDD_PMU. If DCDC convert input is correct but output wrong, we suggest checking inductor L1 and the capacitor C1 and related solder issue. If the voltage of two detection points are correct, the power supply circuit problem can be ruled out. 4.     summary: For custom designed LPC55xx board, if SWD design is correct and power supply system works well, IDE can connect, download and debug target without issue.  

The documentation is only valid for the LPC55xx and LPC55Sxx families. In power down mode, some of peripherals for LPC55xx are power off, which means that the peripherals lose it’s power in power-down mode, so it is required to reinitialize the peripherals after waking-up from  power down mode. The DOC lists the peripherals which lose power in power down mode and are required to initialize, introduces the procedure to enter the power down mode, and  the procedure to reinitialize the peripherals after waking-up from power down mode. The doc is attached and power scheme is also attached.

Hello Community! This document is provided as a hands-on lab guide.  The intent of the lab is to demonstrate how to program the LPCXpresso804 board with the MCUXpresso IDE making use of the SDK examples and the PLU module drivers. The PLU configuration tool will be used to create a new schematic design that will be programmed to the PLU. Setup The following items need to be installed on your computer to complete the lab: Software: •    SDK_2.4.1_LPCXpresso804: -    Copy link into browser: https://mcuxpresso.nxp.com/en/select?device=LPCXpresso804 -    Select ‘MCUXpresso IDE’ or ‘All Toolchains’ in the Toolchain IDE drop-down -    Select ‘Download SDK’ •    MCUXpresso IDE version 10.2.1: -    Can be installed at following link: https://www.nxp.com/mcuxpresso/ide •    PLU configuration tool -    Can be installed at this link: https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1060-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1060?tab=Design_Tools_Tab   Hardware: •    LPCXpresso804 Development Board (OM40001): https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso804-for-the-lpc804-family-of-mcus:OM40001?tab=Design_Tools_Tab •    PLU Shield Board •    1 Micro USB cable Hope this guide is helpful! Any comments are welcome. Best Regards, Carlos Mendoza Technical Support Engineer

The article introduces the RSA theory, how to get the RSA parameter, how to encrypt/decrypt with the RSA algorithms. RSA is an asymmetric cryptographic algorithm and widely used in encryption/decryption application and signature application. It completes encryption and decryption operations by encrypting the message with the public key and decrypting with the private key. In order to support security requirements, it is also used in many places in the LPC55 series, such as: -  RSA digitally signs the application code with the private key, and verifies the authenticity of the code through RSA signature verification in secure boot. This is implemented in LPC55 secure boot. For the LPC family, the mbedtls library is used to implement the RSA algorithms with software.

        The all LPC MCU contain In-System Programming which is able to programming or reprogramming the on-chip memory by using the bootloader software (Flash Magic) with the UART, CAN, USB, SPI, or other peripherals etc. The UART is available in all LPC MCU, whereas other peripheral interfaces may be only supported in particular sort of MCU. The article introduces the CAN ISP implementation for the NXP’s LPC microcontroller family.     Overview        Taking the LPC11Cxx as an example, The C_CAN bootloader is activated by the ROM reset handler automatically if meets CAN ISP option. The C_CAN bootloader initializes the on-chip oscillator and the CAN controller for a CAN bit rate of 100 kbit/s and sets its own CANopen Node ID to a fixed value. The bootloader then waits for CANopen SDO commands and responds to them. These commands allow to read and write anything in a so-called Object Dictionary (OD). The OD contains entries that are addressed via a 16-bit index and 8-bit subindex. The command interface is part of this OD. In a word, these C_CAN ISP command handler allows to perform all functions that are otherwise available via the UART ISP commands, and the Table 1 summarizes the commanders. Table 1  CAN ISP SDO communication         The CAN ISP node listens for CAN 2.0A (11-bit) messages with the identifier of 0x600 plus the Node ID 0x7D equaling to 0x67D. The node sends SDO responses with the identifier 0x580 plus Node ID equaling to 0x5FD. The SDO communication protocols“expedited”and “segmented” are supported. This means that communication is always confirmed: Each request CAN message will be followed by a response message from the ISP node. However, the SDO block transfer mode is not supported. Fig1 CAN ISP object directory    CAN ISP Implementation           Hrdware preparation          LPCXpresso board LPC11C24 : OM13093 Fig 2 OM13093          PCAN-USB     Fig 3 PCAN-USB          Hardware assembling         Software preparation          Starting the Flash Magic, then follow the below figures to programing and executing the application demo. Fig 5           Result        Hex file: periph_blinky.hex (Froming the LPCopen library) Fig 6 Led is blinking

This is a quick introduction that shows how to interface a popular GPS module to the LPC845 Breakout Board using the UART drivers from the MCUXpresso SDK. This example reads and parses GPS data from the module when the user button is pressed and outputs the information to a host computer console via the board's VCOM interface.    UART Protocol The UART function uses two TPU channels to provide a 2-wire (TxD and RxD) asynchronous serial interface. One TPU channel is configured to function as the serial transmitter (TxD), and another TPU channel is configured to function as a serial receiver (RxD).    Adafruit Flora Wearable GPS The module used for this example is built around the MTK3339 chipset, a no-nonsense, high-quality GPS module that can track up to 22 satellites on 66 channels, has an excellent high-sensitivity receiver. It can do up to 10 location updates a second for high speed, high sensitivity logging or tracking. Power usage is very low, only 20 mA during navigation. Adafruit took this module and mounted it on one of their super-compact Flora boards, which are very easy to connect up to the LPC845 Breakout:     Figure 1. Flora Wearable GPS.   GPS Module Example NXP provides example packages that include projects to use the principal's peripherals that the board include: ADC, I2C, PWM, USART, Captouch, and SPI.   What we need: LPC845 Breakout Board MCUXpresso IDE V10.3.0 SDK_2.5.0_LPC845 NXP example packages Adafruit Flora Wearable GPS Micro USB cable   Once downloaded, we import the library project into the workspace using the ''Import project(s) from file system... from the Quickstart panel in MCUXpresso IDE:     Figure 2. Import projects   Then browse the examples packages archive file:     Figure 3. Select Example package.   Press next, and see that are a selection of projects to import, in this case, only keep select the LPC845_BoB_GPS how it looks in the picture below:     Figure 4. Select GPS project   Connections Now, with the project already in the workspace is time to set up the connection between the LPC845 Breakout board and the GPS module, as shown in the table below:     Table 1. LPC845 to GPS module.   The Flora module has the signals clearly printed on their silkscreen which really helps .     Figure 5. LPC845 Breakout Board to GPS module connections.   Once the connections are made, its time to build and run the example code, use the build and debug button inside the IDE. Now open a terminal program and connect to the COM port the board enumerated as. Configure the terminal with these settings:  115200 baud rate.   No parity.  8 data bits  1 stop bit   Place the GPS module outside. Once the GPS has located the satellite data, the red LED on the GPS will stop blinking. If you see the LED blinking once a second, it does not yet have a fix! It can take many minutes to get a fix if the module sees any satellites immediately. Once it has a fix, press the user button (K1) to display the GPS data in the serial monitor, which includes the current date and time in UTC. It will also give you your latitude, longitude and approximate altitude with the Serial monitor. Figure 6. GPS Print Out.