Symptoms Many LPC55 users experienced connection failure when using ISP USB0 for firmware update. In practice, we don’t suggest user updating firmware via ISP USB0 for LPC55(S)6x/ 2x,LPC55(S)1x/0x parts. Diagnosis LPC55 USB0 is Full Speed USB port. The default setting of CMPA turns off the USB0 port. Some users may reconfigure CMPA to enable ISP USB0 in order to use ISP USB0 BOOT, but this is not recommended in practice. LPC55 ISP USB0 uses internal FRO as clock source. According to LPC55 data sheet, the FRO accuracy is only +-2%, while the FS USB data rate tolerance specification is +-2500ppm(+-0.25%). Obviously, the LPC55 FRO spec can’t meet the USB0 clock accuracy requirement. See below extraction from NXP manuals. Fig 1. The accuracy of FRO ( Extracted from LPC55S69 Datasheet )   Fig 2. The accuracy requirement of USB FS( Extracted from TN00063 )  Some users may wonder why USB0 can use internal FRO as clock source in the user application?  Whenever internal clock source FRO is used as USB0 clock source, we must calibrate FRO in source code for communication. That’s to say, trim FRO to an accurate frequency. We can see FRO trim in many MCUXPressoSDK USB demos. When using FRO as the USB0 clock source, in order to ensure the USB0 clock accuracy, we must use the USB0 SOF frame synchronization to calibrate the FRO in order to ensure the accuracy of FS USB clock source (reference design of TN00063, TN00063-LPC5500 Crystal-less USB Solution). Unfortunately, the BOOT ROM of LPC55 does not support USB SOF calibrating FRO. As a result, even if we enable ISP USB0, the FRO clock drift can still cause USB0 communication failure under non-room temperature conditions. Solution Since ISP USB0 is not recommended for firmware update, the user manual no longer announces the enablement bit of ISP USB0 in CMPA. If you need to use USB0 for firmware update, we recommend using ISP USB1 (High Speed USB), because USB1 uses accurate external clock source which can ensure the ISP USB1 working stable. In addition, the communication protocol of ISPUSB complies with BLHOST specification. For details, see:  blhost User's Guide - NXP  

This document describes how to create a new LPC project using LPCOpen v2.xx, LPCXpresso v8.2.2 and LPC11U24 LPCXpresso board. In addition describes how to create 2 simple example codes. Blinking LED. Set the LED using a push bottom.  LPCOpen LPCOpen is an extensive collection of free software libraries (drivers and middleware) and example programs that enable developers to create multifunctional products based on LPC microcontrollers. After install LPCXpresso, the LPCOpen packages for supported board(s)/device(s) can be found at the path: <install_path>\lpcxpresso\Examples\LPCOpen > This directory contains a number of LPCOpen software bundles for use with the LPCXpresso IDE and a variety of development boards. Note that LPCOpen bundles are periodically updated, and additional bundles are released. Thus we would always recommend checking the LPCOpen pages to ensure that you are using the latest versions. This example was created using the LPC11U24 LPCXpresso board in this case the drivers selected is lpcopen_v2_00a_lpcxpresso_nxp_lpcxpresso_11u14.zip Importing libraries In order to create a new project, it is necessary to first import the LPCOpen Chip Library for the device used and optionally the LPCOpen Board Library Project. For do that it is necessary to follow these steps: 1. Click on Import project(s). 2. Select the examples archive file to import. In this case, the projects imported are contained within archives .zip.  3. For this example the LPC11U14 LPCXpresso board is selected. Click Open. Then click Next 4. Select only the LPCOpen Chip Library and LPCOpen Board Library Project. Click Finish. The same steps are required for any LPC device and board you are used. Creating a new LPC project.   The steps to create a new LPC project are described below: 1. In Quickstar Panel, click "New project"   2. Choose a wizard for your MCU. In this case LPC1100/LPC1200 -> LPC11Uxx -> LPCOpen-C Project This option will link the C project to LPCOpen. Then click Next.   3. Select the Project name and click Next.   4. Select the device used (LPC11U24 for this case) and click Next.   5. Select the LPCOpen Chip Library and LPCOpen Board Library, these projects must be present in the workspace.   6. You can set the following option as default clicking Next, then click Finish.   7. At this point, a new project was created. This project has a src (source) folder, the src folder contains: cr_startup_lpc11uxx.c: This is the LPC11Uxx Microcontroller Startup code for use with LPCXpresso IDE. crp.c: Source file to create CRP word expected by LPCXpresso IDE linker. sysinit.c: Common SystemInit function for LPC11xx chips. <name of project> my_first_example: This file contains the main code.     8. LPCXpresso creates a simple C project where it is reading the clock settings and update the system core clock variable, initialized the board and set the LED to the state of "On". 9. At this point you should be able to build and debug this project.   Writing my first project using LPCXpresso, LPCOpen and LPC11U24.   This section describes how to create 2 simple example codes. Blinking LED. Set the LED using a push bottom. The LPCOpen Chip Library (in this case lpc_chip_11uxx_lib) contains the drivers for some LPC peripherals. For these examples, we will use the GPIO Driver. The LPCOpen Board Library Project (in this case nxp_lpcxpresso_11u14_board_lib) contains files with software API functions that provide some simple abstracted functions used across multiple LPCOpen board examples. The board_api.h contains common board definitions that are shared across boards and devices. All of these functions do not need to be implemented for a specific board, but if they are implemented, they should use this API standard.   After create a new project using LPCXpresso and LPCOpen, it is created a simple C project where it is initialized the board and set the LED to the state of "On" using the Board_LED_Set function.   int main(void) {   #if defined (__USE_LPCOPEN)     // Read clock settings and update SystemCoreClock variable     SystemCoreClockUpdate(); #if !defined(NO_BOARD_LIB)     // Set up and initialize all required blocks and     // functions related to the board hardware     Board_Init();     // Set the LED to the state of "On"     Board_LED_Set(0, true); #endif #endif       // TODO: insert code here       // Force the counter to be placed into memory     volatile static int i = 0 ;     // Enter an infinite loop, just incrementing a counter     while(1) {         i++ ;     }     return 0 ; }       a. Blinking LED. In board_api.h file there is an API function that toggle the LED void Board_LED_Toggle(uint8_t LEDNumber);  LEDNumber parameter is the LED number to change the state. The number of the LED for the LPCXpresso LPC11U24 is 0. It is easy to create a delay function using FOR loops. For example: void Delay (unsigned int ms) {         volatile static int x,y;           while (ms)         {                 for (x=0; x<=140; x++)                 {                         y++;                 }                 ms--;         } } In order to have the LED blinking, it is necessary to call these functions in an infinite loop. while(1) {                 Board_LED_Toggle(0);                 Delay (10000);         } Complete code (Blinking LED). int main(void) { #if defined (__USE_LPCOPEN)         // Read clock settings and update SystemCoreClock variable         SystemCoreClockUpdate(); #if !defined(NO_BOARD_LIB)         // Set up and initialize all required blocks and         // functions related to the board hardware         Board_Init();         // Set the LED to the state of "On"         Board_LED_Set(0, true); #endif #endif          while(1) {                 Board_LED_Toggle(0);                 Delay (10000);         }         return 0 ; }  void Delay (unsigned int ms) {         volatile static int x,y;         while (ms)         {                 for (x=0; x<=140; x++)                 {                         y++;                 }                 ms--;         } }      b. Set the LED using a push bottom. For this example it is necessary to configure a pin as input.  The gpio_11xx_1.h file contains all the function definitions for the GPIO Driver. The example uses the pin 16 of port 0 to connect the push bottom. The function Chip_GPIO_SetPinDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) sets the GPIO direction for a single GPIO pin to an input. In order to configure the Port 0, pin 16 as input we can use this function: Chip_GPIO_SetPinDIRInput(LPC_GPIO, 0, 16); Then, it is necessary to check the status of this pin to turn-on/turn-off the LED. The function Chip_GPIO_GetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin) gets a GPIO pin state via the GPIO byte register. This function returns true if the GPIO is high, false if low. State_Input=  Chip_GPIO_GetPinState (LPC_GPIO, 0, 16);   Complete code (Set the LED using a push bottom). int main(void) {         bool State_Input;   #if defined (__USE_LPCOPEN)     // Read clock settings and update SystemCoreClock variable     SystemCoreClockUpdate(); #if !defined(NO_BOARD_LIB)     // Set up and initialize all required blocks and     // functions related to the board hardware     Board_Init();     Chip_GPIO_SetPinDIRInput(LPC_GPIO, 0, 16);     // Set the LED to the state of "On"     Board_LED_Set(0, false);  #endif  #endif      while(1) {           State_Input=  Chip_GPIO_GetPinState (LPC_GPIO, 0, 16);              if (State_Input==0){                 Board_LED_Set(0, true);             }             else {                 Board_LED_Set(0, false);             }     }     return 0 ; }   I hope this helps!! Regards Soledad

    Writing this post just want to remind the customer of RAM allocation when use the on-chip CAN drivers in LPC11C24. Otherwise, when meet the abnormal issues, it is difficult to locate the root reason and it also causes a waste of time.      Now, take a real customer question as an example, to highlight the RAM allocation importance when using the on-chip CAN API in LPC11C24. Problem description     Customer used the LPC11C24 on-chip CAN API to realize the CAN frames sending and receiving, the CAN code was from the official lpcopen, and it worked OK when he just used the CAN code. But when customer added the UART code, they found the code always enter hardfault after a short time running. They test the UART code which without the CAN code directly, the UART code worked perfectly. It means, independent UART code and independent CAN code are all working normally, but when combine the UART and on-chip CAN code together, the code will enter hardfault. Problem analysis From the Cortex M0 devices generic user guide, we can get the information about the hard fault:     Faults are a subset of exceptions, see Exception model. All faults result in the HardFault exception being taken or cause lockup if they occur in the NMI or HardFault handler. The faults are:      execution of an SVC instruction at a priority equal or higher than SVCall      execution of a BKPT instruction without a debugger attached      a system-generated bus error on a load or store      execution of an instruction from an XN memory address      execution of an instruction from a location for which the system generates a bus fault      a system-generated bus error on a vector fetch      execution of an Undefined instruction      execution of an instruction when not in Thumb-State as a result of the T-bit being previously cleared to 0      an attempted load or store to an unaligned address Now we debug the problem project to check, which detail code line caused this hardfault problem. When the code enters the hardfault handler, check the MSP address in the flash, then find the LR register, which will link to the code before entering in the hardfault handler, the following are the according debug result:   The LR register is 0X1FFF2C1F, it means before enter in hardfault handler, the code runs to this address code. Now, check the 0X1FFF2C1F in the memory map.    We can find the address is in the ROM area, because we just use the ROM CAN driver, UART is just the pure register control code, then we can get the problem still relate to the on-chip CAN driver, not the UART code. But we can’t see or debug the detail ROM CAN driver directly, we still can’t find the root problem.    Even we know the problem is not caused by the UART, but another important clue which relates to the UART function also influence the test result after I do a lot of testing. In the customer code, he defines the UART user transmit and receive buffer like this: #define UART_SRB_SIZE 128    // Send #define UART_RRB_SIZE 32    // Receive /* Transmit and receive buffers */ static uint8_t rxbuff[UART_RRB_SIZE], txbuff[UART_SRB_SIZE];   On one occasion, I tried changing #define UART_SRB_SIZE 128 To  #define UART_SRB_SIZE 32 Just minimize the txbuff size, I found the code won’t enter in the hardfault handler any more. It seems very strange and contradiction with the hardfault handler enter point which is test before.    I also check the generated code size, the used RAM and flash size is:   text       data        bss        dec        hex    filename    7672          0        244       7916       1eec    pscan.axf LPC11C24 RAM is 8K, here just 244 Bytes, the stack also use the whole RAM, so the 8K RAM size should be enough to use.   In this situation, I check the project’s .map file about the txbuff with 128 and 32 respectively.    1)txbuff with 128Bytes Rxbuff and txbuff occupy the RAM address from 0X10000048 to 0X100000E8.     2)txbuff with 32Bytes Rxbuff and txbuff occupy the RAM address from 0X10000048 to 0X10000088. We can find the txbuff start address is the same, just the end address has difference.    With these information, we checked the LPC11C24 user manual chapter C_CAN on-chip drivers again, we found a significant description:      0X10000050 to 0X100000B8 is used by the on-chip CAN API RAM, and from the issue project, memory map file, we can find rxbuff and txbuff RAM address is 0X10000048 to 0X100000E8, it already occupies the whole CAN API RAM, this is the key point. Minimize the txbuff, then rxbuff and txbuff occupy the RAM address from 0X10000048 to 0X10000088, this address doesn’t occupy the whole on chip CAN API RAM, in this situation, the problem doesn’t happen, I think the used CAN API may in the RAM address 0X10000089-0X100000B8.    Anyway, just minimize the buffer size can’t solve the problem from the root side. We must follow the user manual to keep the RAM address from 0x10000050 to 0x100000b8 won’t be used by any other application code.   Problem solutions      From the above chapter, we can find the root problem is the application code occupies the on-chip CAN RAM, to solve the problem, we need to modify the linker file, to prevent the usage of on-chip CAN RAM range.      Because the customer is using the LPCXPresso IDE, then we take this IDE as an example, to protect the RAM address 0x10000050 to 0x100000b8. From the above, we can get that the LPCX11C24 have 8Kbytes RAM, normally, customer will define it just in one, now we divide the RAM to two pieces. 1) RAM2: Location 0X10000000, size 0X100 2) RAM: Location 0X10000100, size 0X1F00 In the LPCXpresso, Project Properties -> C/C++ Build -> MCU settings, then modify it like this:     Then generate the code, and check the map file again.   RAM address from 0x10000000 to 0X10000FF is not used by any other application code. All the application code RAM is using from address 0x10000100. After long time testing, we find the hardfault problem never happens, on customer side, it also works OK. In conclusion, when customer want to use the on-chip CAN API, they need to protect the RAM address from 0x10000050 to 0x100000b8 in the linker file.    

In this document, I will explain how to create a project to use the SPIFI library version 1.03 with the LPC4370. For this we will need the following tools: MCUXpresso IDE 10.2. Link LPC-LINK2 to use it as an evaluation board for the LPC4370. Link External debugger. In my case, I used another LPC-LINK2 board. LPCOpen v2_12 for the LPC4370, this version comes with the installation of MCUXpresso IDE. SPIFI library v1.3. Link Code Example lpcopen_2_12_lpcxpresso_ngx_xplorer_1830_SPIFI_v1.0. Link First, download and install all the tools needed. In your workspace of MCUXpresso we will import (1) three projects of the LPCOpen v2_12 for the LPC4370: periph_blinky, lpc_board_nxp_lpclink2_4370 and lpc_chip_43xx.  The LPCOpen zip file is in the next path of your PC: C:\nxp\MCUXpressoIDE_10.2.1_795\ide\Examples\LPCOpen (2) Extract the files of the zip named lpclibspifi_lpcxpresso_1.03_68 that we downloaded before. The folder that we need is spifilib_m4f. Drag and drop this folder into the Project Explorer on your workspace of the LPC4370, after choosing copy and you should see the spifilib_m4f in your Project Explorer. Once you imported correctly the SPIFI library, select the library (1) on the project explorer window and build it (2). Once you do this you should see that a new folder called Debug appear (3). Now we need to edit the properties of the periph_blinky example to add the library spifilib_m4f to the project. To do this, right click on the project and click properties. Once in the properties window click on C/C++ Build (1) > Settings (2) > Includes (under the section MCU C Compiler) (3). In the includes window click Add… (1) > Workspace (2) > spifilib_m4f (3) > inc (4) > click OK (5) on the window Folder Selection > click OK (6) on the window Add directory path. You should see the following on the include paths. Now, go to the libraries (1) option under the section MCU Linker, on the section Libraries (-I) click Add… (2) finally write the name of the library (spifilib_m4f) (3) and click OK (4). Under the section Library search path (-L) click Add… (1) > Workspace (2) > spifilib_m4f (3) > Debug (4) > OK (5). If you see the same as shown in the below image you are good to go so click Apply and close. To check if you did the below steps correct let’s do the following. On the project periph_blinky in the file systick.c include the file spifilib_api.h and compile the project. If the project compiles without problems it means that you imported correctly the spifi library. If you found problems please stop and repeat all the steps mentioned before. Now that we added successfully the library we can start to migrate the example for the LPC1830 that we download before. First, unzip the file lpcopen_2_12_lpcxpresso_ngx_xplorer_1830_SPIFI_v1.0. Once you unzipped the file go to the following path: spifilib_blinky > example > src. Open the file named Blinky.c and copy all the content of the file. Now go to the file systick.c on your workspace of MCUXpresso within the project periph_blinky, delete all the content of this file and paste what you copied before. Do not compile at this point or you will receive multiple errors! Go back to the path spifilib_blinky > example > src on your PC. Drag and drop the file called spifi_setup.c into the folder src of your project periph_blinky on your Workspace. Open the file that we just copy into our workspace and go to line 46 of the code. Here we are creating a buffer of 64KB that we will use later to write in the SPIFI. The __BSS(RAM3) is to save this buffer in the RAM block three of memory. The problem here is that the block of RAM3 in the LPC4370 is not big enough to store the buffer of 64KB (see below image), so let’s change this for either RAM or RAM2 that are big enough to store the buffer. Now that we added the spifi_setup file let’s go back to the systick.c file and add the external declaration for the function spifiSetUp. At this point, if we compile the project we shouldn’t see any problems, only some warnings because of the functions and variables that we are not using. We are almost done, we are missing the most important thing. With this demo you will be writing, deleting and reading the SPIFI memory, this means that you cannot be executing form the SPIFI flash memory. You need to move to the RAM memory all the functions that are going to make this. This is the reason why in the file systick.c we don’t have any function that interacts directly with the SPIFI, this will make much easier the work of moving all the functions that interact with the SPIFI memory to RAM. The function spifiSetUp is the one that will make all the tests on the SPIFI and it is in the spifi_setup file, so we will need to move this entire file to RAM along with the SPIFI library. We will use three different scripts to move the library and the file spifi_setup to RAM. You can learn more about this in the following community post: https://community.nxp.com/thread/389110. First, right click on the folder of the project > new > folder, the name of the folder must be linkscripts. According to the sections Relocating particular objects into RAM and Relocating particular libraries into RAM of the community post mentioned before we need to create three files in this new folder: main_text.ldt, main_rodata.ldt and main_data.ldt. To do this, right click on the folder linkscripts > new > file. Here is the content that you should have on the three files that we just created. Do not include on the files the text that is in bold, that's just for reference! File main_data.ldt *libspifilib_m4f.a:(.text*) *libspifilib_m4f.a:(.rodata .rodata.* .constdata .constdata.*) *spifi_setup.o(.text*) *spifi_setup.o(.rodata .rodata.* .constdata .constdata.*) . = ALIGN(${text_align}); *(.data*) File main_rodata.ldt *(EXCLUDE_FILE(*libspifilib_m4f.a: *spifi_setup.o) .rodata) *(EXCLUDE_FILE(*libspifilib_m4f.a: *spifi_setup.o) .rodata.*) *(EXCLUDE_FILE(*libspifilib_m4f.a: *spifi_setup.o) .constdata) *(EXCLUDE_FILE(*libspifilib_m4f.a: *spifi_setup.o) .constdata.*) . = ALIGN(${text_align}); File main_text.ldt *(EXCLUDE_FILE(*libspifilib_m4f.a: *spifi_setup.o) .text*) After finishing with the three files you are done with the demo! It’s important to mention that if you want to go inside the function spifiSetUp while debugging you need to set a breakpoint inside the function. While debugging we can see that before calling the function spifiSetUp we are running from the SPIFI flash memory and once we enter to the function we are running from RAM memory. Once we run the demo successfully we should see the following in a terminal and the LED1 will be blinking. Hope this guide is helpful! Best Regards, Victor.

Hello Community! This document is provided as a hands-on lab guide.  The intent of the lab is to demonstrate how to program and use the LPC8N04 development board by using the LPC8N04 board support package demo application and make use of the read, write and energy harvesting capabilities of the NFC tag. Setup The following items are needed to complete the lab: Software: •    LPC8N04 Board Support Package MCUXpresso, can be downloaded at this link: https://www.nxp.com/downloads/en/lab-test-software/LPC8N04-MCUXpresso-BSP.zip •    MCUXpresso IDE version 10.2.1, can be installed from here: https://www.nxp.com/mcuxpresso/ide •    LPC8N04 NFC Demo Android application, can be installed at the link below: https://play.google.com/store/apps/details?id=com.nxp.lpc8nxxnfcdemo   Hardware: •    LPC8N04 Development Board for LPC8N04 MCU (OM40002): https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc800-series-cortex-m0-plus-mcus/lpc8n04-development-board-for-lpc8n04-mcu:OM40002 •    Android Phone with NFC •    1 Micro USB cable   Hope this guide is helpful! Any comments are welcome.   Best Regards, Carlos Mendoza Technical Support Engineer

The ADC of LPC55xx supports scan mode, in scan mode, once ADC triggering (either hardware or software) can convert multiple analog channels. The document gives an example that the CTImer2 module triggers ADC and ADC converts two analog channels for each triggering. The doc introduces the CTimer configuration, ADC triggering control register configuration, and ADC Command buffer chain and ADC result reading , in this way, the CTimer can trigger ADC, the ADC can convert multiple channels. The example and the doc are attached. The Example is developed based on SDK example lpcxpresso55s69_lpcadc_interrupt example, the tools is MCUXprsso IDE ver11.7, the SDK package is SDK_2.x_LPCXpresso55S69 ver2.11.1  

For the LPC8xx family, the peripheral module input or output signals are not connected to external pads fixedly as most processor does . With SWM module, the peripheral module input or output signals can be routed to any external GPIO pins via software configuration There is special requirement that one peripheral output signal functions as the input signal of another peripheral, in the case, the peripheral output signal and the peripheral input signal can be routed to the same pad via SWM so that the input and output signals are connected internally without external cable. The LPC802 has ACOMP module, CTimer module and SWM module, per customer requirement, the ACOMP output signal and CTimer0 capture 0 input signal can be routed to the same GPIO pin without external connection so that the ACOMP output signal can trigger CTimer0 capture 0 event internally. In the doc, I give the code to configure the CTimer, ACOMP and the SWM, explain the configuration,introduce the tools, board and result.  

The power measurement board includes eight measurement channels which support for eight programmable gain amplifiers(LTC6915) and two ADC converters(AD7175). The measurement board measures the voltage drop across sampling resistor, and send to the ADC after the voltage drop is processed by amplifier and make it available via SPI. Microcontroller LPC55S69 collects the data from the measurement circuit and send it to the host computer via USB VCOM port. The MCU can control the gain value of programmable gain amplifiers by SPI when different power circuit are measured. The host computer connects to the power measurement board through the USB virtual serial port, the MCU initializes and configures the measurement unit by SPI, and starts to measure the inside current and monitor the voltage. MCU adjust the gain parameter and then transmit current and voltage data to MCU by SPI, then MCU transmits the data to the host computer for processing and display through the virtual serial port. The voltage drop of the measured circuit to be measured is firstly amplified by the programmable amplifier LTC6915, and MCU monitor the state which whether the data is abnormal at the same time. R0 is the sampling resistor, LTC6915 is a selectable programmable amplifier, the gain can be set to 14 kinds, PGA gain parameter is adjusted when the current changes. ADC7175 is the 24-bit high-precision ADC, which is more advantageous in the application of small current measurement. When the MCU switches the low power mode to the normal mode, and the LTC6915 will reduce the gain value by SPI. The power measurement board provides easy connection method by two-wires cable. For example, the MIMXRT1180EVK and MIMXRT1020EVK are connected with power measurement board. The USB virtual COM is used for data transfer, and display by PMT(power management tool) or other PC GUI, the measurement power data include current, voltage and power. There are more detailed descriptions in the attachment.

1.     Problem description When we debug a new designed LPC55 custom board through SWD, if IDE throws out error messages such as connection failure or no available device being found, normally we must check below two points: Whether the debug circuit design is correct.（https://community.nxp.com/t5/LPCXpresso-IDE-FAQs/Design-Considerations-for-Debug/m-p/469565#M44） Whether LPC55 power supply system is correct. Regarding to the second point of power supply system, we received many feedback from customers that even they read UM for times they still can’t well-understand LPC55xx DCDC power supply system. Therefore we prepare this article to analyze LPC55xx power supply circuit and introduce detection method. 2.     Problem Analysis The difference of power supply circuit between LPC55xx series and other LPCs is that LPC55xx uses DCDC circuit inside to provide core voltage. It lowers the input 1.8V-3.6V voltage to around 1.1V to supply LPC55xx internal system. The DCDC converter is efficient and reduces the internal power consumption. The disadvantage is that it generates a certain ripple. LPC55xx power supply circuit is as follows: In order to analyze, We divide LPC55xx power supply circuit into 4 regions and will introduce them one by one according to the different functions.   1)  Input voltage: In this part, VBAT_PMU provides input voltage to RTC and internal analog components. VBAT_DCDC provides input voltage to internal DCDC circuit. 2)  A set of filter capacitors: To filter out the burrs and glitch at the voltage input. 3)  DCDC circuit: Work with LPC55xx internal DCDC circuit together to generate 1.1V output voltage. 4)  VDD_PMU: Provides the 1.1V output voltage of the DCDC circuit to the LPC55xx core. Note: The design of region 3 is to work with the internal DCDC converter. The inductance L1 of 4μ7H and the capacitance C1 of 22μF are calculated by LPC55xx internal circuit. When designing, we must strictly follow the parameters recommended in the manual, otherwise DCDC circuit can’t work normally. 3.     DCDC Circuit Detection LPC55xx power supply system current direction is shown in the diagram below. See arrow in red. In order to ensure the normal operation of the DCDC circuit, the following two detection points are recommended. 1)  Detection point 1: External 1.8 to 3.6V voltage input, normally it’s 3.3V. 2)  Detection point 2: Output of the DCDC converter. If the DCDC works normally, we can get 1.1V voltage output here. The output voltage supplies power to the core components such as the central processing unit through the VDD_PMU. If DCDC convert input is correct but output wrong, we suggest checking inductor L1 and the capacitor C1 and related solder issue. If the voltage of two detection points are correct, the power supply circuit problem can be ruled out. 4.     summary: For custom designed LPC55xx board, if SWD design is correct and power supply system works well, IDE can connect, download and debug target without issue.  

  [LPC546xx] Understanding ECRP   Code protection is usually considered at the last step during developing stage. The purpose is to protect our code being hacked when the product is released to market. For example, using ECRP to disable SWD debug interface, disable ISP, disable mass erase, etc. 1.    ECRP vs Legacy CRP   ECRP (Enhanced Code Read Protection) is versus legacy CRP on early LPC devices. We can consider ECRP as an advanced version of CRP. Comparing with CRP, ECRP adds new protection features: − Block ISP via Pins − Block ISP using IAP − Block SWD − Mass Erase enable/disable − Sector protection This table lists the difference of ECRP vs. CRP from Anti-Tampering and Flexible view. 2.    Understand and implement ECRP ECRP allows user to tenable below features: − Protect FLASH from ISP Erase/Write − Protect FLASH from IAP Erase/Write − Enable/Disable ISP Entry from bootloader − Enable/Disable ISP Entry from IAP call − Enable/Disable SWD Enable/Disable It looks easy but it is important to know that ECRP feature is controlled by both FLASH and OTP configuration! The most restrictive combination in both setting is needed 2.1          Where is FLASH ECRP: ECRP is at 0x20 of vector table, it’s uint32_t type. We write to this address to set FLASH ECRP protection. The valid bits of FLASH_ECRP is 0-17bit, and the default value is 0xFFFF_FFFF. For detail, please see UM.   2.2          Where is OTP ECRP OPT is a non-volatile and write-once register. OTP is not FLASH and it can be ONLY written by IAP function. OPT ECRP configuration is at OPT bank 3. The default OTP ECRP value is 0.   2.3          FLASH ECRP + OTP ECRP Decides the Protection. See this table to show the combination. Here OTP ECRP is always set with higher priority than FLASH ECRP! Here is typical ECRP settings 2.4        Be Attention! The part is permanently disabled when On-chip Image(s) are ruined SWD access prohibited ISP entries prohibited Please be attention when testing ECRP feature, mis-operation may make the chip brick!

This is an example of how to use the CTimer to trigger the LPADC conversion in the LPC55s28. I attached the example in MCUXpresso.    

LPC: Regarding to Internal Clock Calibration In MCU development, using the internal crystal oscillator as a clock source instead of the external crystal oscillator can save costs. But the clock frequency generated by the internal crystal oscillator is affected by temperature and MCU frequency more than external crystal oscillator. Many customers have questions about the internal clock accuracy, whether the internal clock can be used for USB transmission, and how to calibrate the internal clock. This article mainly explains this. 1. Calibrate internal clock by FREQTRIM Normally, we can only calibrate the internal clock by adjusting the FREQTRIM value. The internal clock frequency is affected by temperature, MCU frequency and other factors. The FRO control register can calibrate the internal clock, as follows:   The FREQTRIM register value ranges from 0 to 255, and each adjustment step is about 0.1% of the internal clock frequency. There is no precise formula to express the relationship between the FREQTRIM value and the FRO frequency. The ideal FREQTRIM value can only be determined by adjusting FREQTRIM in code and observing FRO output waveform with oscilloscope. Test and observation: The following is the test result. It shows how FRO frequency varies with FREQTRIM increasing from 0-255. Test result of first development board:     Test result of second development board:   The following two points can be seen from test results: - There is no linear relationship between the FRO clock frequency and the FREQTRIM register value, and there is no precise formula to express the relationship between them; - Even for chips of the same part number, the internal clock frequency changes are slightly different, with the FREQTRIM register value changing, but the trend is same. Therefore, there is no precise formula to guide internal clock frequency calibration. You can only adjust the FREQTRIM register value repeatedly, just like adjusting the focus of a projector. Use an oscilloscope to check the frequency of the internal clock pin to find the most suitable FREQTRIM register value. There is same solution for FRO clock frequency calibration about other LPC chips.   2. LPC51U68: Software calibration USB transmission when using internal clock source The Full Speed USB module of LPC51U68 has a unique FRO automatic calibration function, which automatically adjusts the FREQTRIM value to achieve FRO calibration by measuring the USB SOF bit. Once FRO is calibrated, the corresponding system clock and peripheral clock are calibrated. This solution is only applicable to LPC51U68, please refer to the user manual for other chips. The following is the FRO clock accuracy described in LPC51U68 User Manual, which is ±1%:   For Full Speed USB, the USB data transmission accuracy requirement is ±0.25%, and the FRO clock accuracy is not satisfied. NXP provides a software solution to calibrate FRO by measuring the first packet of frame (SOF), which can meet the transmission accuracy in Full Speed mode.   The solution download link is as follows: https://www.nxp.com/docs/en/application-note/TN00035.zip  

LPC55xx系列的MCUXpresso SDK使用FLASH API来实现FLASH驱动。 一些用户在执行如下FLASH写操作时可能会遇到如下的问题： status = FLASH_Program(&flashInstance, destAdrss, (uint8_t *)s_bufferFF, 8);       执行完上述代码后，对应的地址区间数据没有变化，写入失败，返回错误代码101，如下图所示, 错误代码101看上去有点陌生，这在之前的LPC产品中并不常见，我们在用户手册中搜索FLASH driver status code，可以查找到错误代码101为FLASH 对齐操作错误（Alignment Error）。   对齐操作错误是什么？我们先来看程序是如何对FLASH_Program函数进行定义的。 FLASH写函数定义如下： status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes); 新用户经常会忽略掉用户手册中对于这个API的介绍“the required start and the lengthInBytes must be page size aligned”，这句话的意思是在执行FLASH_Program函数时，写入的起始地址和数据长度必须512字节对齐，所以如果我们把代码 status = FLASH_Program(&flashInstance, destAdrss, (uint8_t *)s_bufferFF, 8); 更正为 status = FLASH_Program(&flashInstance, destAdrss, (uint8_t *)s_bufferFF, 512); FLASH_Program函数就可以运行成功。   请注意：在2.6.x版本的SDK中，FLASH_Program函数的注释将参数的起始地址和数据长度错误的表述为字对齐，2.7.0版本的SDK已经对注释进行了修正。即使你想要操作一个字节，lengthInBytes也是512字节对齐。   最后：建议用户在遇到关于FLASH API操作失败的相关问题，一定要查看用户手册中的FLASH驱动状态码，我们可以从UM11126中的第九章节FLASH API部分找到它，如下图所示。  

Symptoms Some users cannot access MCU peripherals normally by add peripheral initialization code to MCUXpresso SDK TrusZone demo. For example, when add Flash operation code in the security world, the program code jumps to HardFault_Handler after running to function FLASH_INIT(), and the execution of Flash erase and Flash program operations fails also, as follows: Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Diagnosis As shown in figure 2 and figure 3, when the program code runs to code return VERSION_FLASH_API_TREE->flash_init(config), it automatically jumps to HardFault_Handler. VERSION_FLASH_API_TREE is located in the 0x1301fe00 address of the boot rom, the flash erase api is located in address 0x1300413bU, and the flash program api is located in address 0x1300419dU (the corresponding program code is shown in figure 6). All above addresses are not security privilege. Figure 6        From the 7.5.3.1.2 TrustZone preset data chapter in user manual, after enabling the TrustZone configuration, users must configure the security level of the entire ROM address space to security priority (S-Priv) in order to ensure that the ROM area can be accessed normally by the security area code. Figure 7 Solution Below is the steps of how to resolve this issue. The demo is based on MCUXpresso SDK demo hello_world_s. Step 1: firstly we use the TEE tool integrated with MCUXpresso IDE to configure the security level of the Boot ROM address area, as shown in Figure 8, double-click the Boot-ROM area in the Memory attribution map window, and configure the sector’s security level in the corresponding Security access configuration window on the left. Figure 8 Step 2: Second, when operating Flash or other peripherals in the security area, users must configure the security level of correlative peripherals to the security priority(S-Priv).        When operating flash in the SDK TrustZone demo, the MCU uses two slave peripherals, so users must configure their security level to S-Priv. Figure 9 Please Note: From the usermanual, when operating flash, the system clock frequency cannot exceed 100MHZ. When using the function of FLASH_Program(), because the s_buffer is 512-byte aligned, the BUFFER_LEN is equal to 512/N.   The above configuration of the security level can be configured through the TEE tool integrated the MCUXpresso IDE. After completing configuration, click Update Code to automatically update the relevant code in the tzm_config.c file, as shown in Figure 10. Figure 10 The updated code is shown in Figure 11 below. It is obvious that the security level settings of boot rom memory and peripheral (FLASH, SYSCTRL) have changed. If you do not use the TEE tool, you can also manually modify tzm_config.c to configure the same security options. Figure 11 Third-party tools users: Because many users are accustomed to using third-party development tools such as Keil or IAR, but these IDEs do not integrate the TEE tool, users need to check the configuration requirements of related registers in user manual when modifying the security level of related areas and peripherals in TrusZone, and update the associated code in the tzm_config.c file (similar to Figure 11) to complete the related configuration. In addition, NXP released the MCUXpresso Config Tools, which integrates MCU-related configuration functions. Users can download and install this tool to perform configurations and update codes. The download link is as follows: https://www.nxp.com/design/software/development-software/mcuxpresso-software-and tools/mcuxpresso-config-tools-pins-clocks-peripherals:MCUXpresso-Config-Tools   Introduction of MCUXpresso Config Tools After the tool is installed, open the configuration tool, select Create a new configuration based on an SDK example or hello world project, click Next, as shown in Figure 12: Figure 12   In Start Development window, follow below steps to generate project. As shown in Figure 13. Figure 13 After the tzm_config.c file is updated, copy or import it to the corresponding folder of KEIL or IAR third-party development tools, and it can be used normally.          

The series of LPC540XX chips are flashless, only LPC54018JXM and LPC54S018JXM integrate internal QSPI Flash. The typical part numbers are LPC54018J2(4)M and LPC54S018J2(4)M. Some customers have questions about the concept of SPIFI interface and clock configuration when using this series of chips. This article mainly explains this. Introduction to SPIFI SPIFI (SPI Flash Interface) is an SPI Flash interface that can help microcontrollers replace large-size, high-cost parallel Flash with small-size, low-cost serial Flash. Using SPIFI technology, the external serial FLash can be mapped to microcontroller memory to achieve on-chip memory read effect, that is, cost can be optimized and Flash size can be increased while ensuring the operating speed. The electrical interface of SPIFI is as follows:   In the LPC540XX series of chips, if the part number includes M, QSPI Flash is integrated inside chip; if the part number does not include M, the QSPI Flash is externally connected to chip. The following picture shows the comparison of LPC54S018JXM and LPC54S018 in SPIFI structure:   SPIFI clock frequency description Taking LPC54S018J4M as an example, the SPIFI clock frequency is described below in the UserManual. SPIFI supports 1/2/4bit transmission mode. In 4bit transmission mode, the maximum transmission rate is SPIFI_CLK/2 bytes per second. The data transmission rate is up to 52Mbytes /s, that is, it takes two clock to transmit one byte. If you want to configure the SPIFI transmission rate to 52Mbytes /s, it needs to be in 4bit mode, so SPIFI_CLK is configured to 104M.     The SPIFI clock source is as follows in LPC54S018J4M Datasheet. By default, the SPIFI clock source is FRO96. For example, when the SPIFI clock is configured to 96M, in 4bit transmission mode, the transmission rate is 96/2=48Mbyte/s.   The LPC54S018J4M uses W25Q32JV-DTR as the internal SPIFI Flash. The figure below shows the maximum clock frequency it supports. In 4bit transmission mode, the maximum transmission rate is 133/2=66.5Mbyte/s, which is greater than SPIFI's maximum transmission rate of 52Mbyte/s. It shows that the maximum data transmission rate of W25Q32JV can meet the requirements of LPC54S018J4M QSPI Flash interface for communication rate.   3．Change SPIFI clock frequency The description of the SPIFI clock frequency in UserManual is as follows. In setup_lpc54s018m.c, the SPIFI clock frequency is defined on the address with an offset of 0X1C (the macro is defined as IMG_BAUDRATE), and the initial value is 0. According to the following table, when IMG_BAUDRATE=0, the SPIFI clock frequency is 24M. Since the default SPIFI clock source is the internal clock FRO96M, the SPIFI clock can be configured up to 96MHz in the following table by modifying the value of IMG_BAUDRATE.          There are two ways to modify the SPIFI clock.   3.1 Modify the SPIFI clock through IMG_BAUDRATE Before the main function runs, IMG_BAUDRATE is obtained by BOOT ROM to set the SPIFI clock frequency. If the requirement for the SPIFI clock rate is less than or equal to 96M, it is recommended to directly change the macro definition of IMG_BAUDRATE in setup_lpc54s018m.c to change the SPIFI clock frequency, as follows:   3.2 Modify the SPIFI clock through system config Another method is to modify the SPIFI clock frequency by changing the SPIFI frequency division coefficient in user code, as follows:   The result is as follows. The SPIFI clock frequency is set to 96M.   If you want to configure a higher SPIFI working clock, such as 104M, you must use a higher frequency external clock source to adjust the PLL coefficient and SPIFI frequency division coefficient in order to achieve the required clock frequency.

This document is an introduction to the Programmable Logic Unit (PLU) provided for the LPC804 MCU device. PLU is used to create small combinatorial and/or sequential logic networks including simple state machines. This allows to replace external components like the 74xx series, which are used for the glue logic with the microcontroller and external devices, making simple the PCB and saving design costs. Figure 1. LPC80x MCU families The PLU is comprised of an array of 26 inter-connectable, 5-input Look-up Table (LUT) elements, and 4 flip-flops.  Each LUT element contains a 32-bit truth table (look-up table) register and a 32:1 multiplexer. During operation, the five LUT inputs control the select lines of the multiplexer. This structure allows any desired logical combination of the five LUT inputs. Figure 2. PLU Features The PLU is used to create small combinatorial and/or sequential logic networks including simple state machines. The PLU is comprised of an array of 26 inter-connectable, 5-input Look-up Table (LUT) elements, and 4 flip-flops. Eight primary outputs can be selected using a multiplexer from among all of the LUT outputs and the 4 flip-flops. An external clock to drive the 4 flip-flops must be applied to the PLU_CLKIN pin if a sequential network is implemented. Programmable logic can be used to drive on-chip inputs/triggers through external pin-to-pin connections. A tool suite is provided to facilitate programming of the PLU to implement the logic network described in a Verilog RTL design.   Advantages Some advantages of the PLU are: Replace the combinational logic of the 7400 series. State machine design using Flip-flop. Address decoder. Pattern match. Low-power application. PLU works in deep-sleep and power-down mode. Programmable so PLU can be reprogrammed and reused. Seamless connection using SWM and PLU. Pin description There are up to six primary inputs into the PLU module, one clock input, and eight primary outputs. All the inputs are connected directly to the package pins via chip-level I/O multiplexing.  All these pins can be enabled by configuring the relevant SWM register (PINASSIGN_FIXED0). A particular logic network may not require all of the available inputs or outputs. The user can specify which inputs and outputs to use, and which package pins those inputs and outputs will connect to as part of the overall top-level IO configuration. Registers Programming the PLU to implement a particular logic network involves writing to the various Truth Table registers to specify the logic functions to be performed by each of the LUT elements, programming the Input multiplexer registers to select the five inputs presented to each LUT, and programming the Output multiplexer register to select the eight primary outputs from the PLU module. Programming of all of these registers is performed only during initialization. Table 1. PLU registers PLU Shield board with LPCXpresso804 The OM40001 package includes a shield board for use with the LPCXpresso804 board when prototyping programmable logic unit (PLU) designs. The PLU shield provides the following features to assist with this type of development: 5 slide switches to enable 5 possible PLU inputs to be connected to VDD (marked as VCC on the Shield) or GND through a resistor (to set those inputs to a logic 1 or zero). 8 LEDs with jumpers to connect/disconnect possible PLU outputs for visual status indication. Push button option for momentary / edge signal inputs. Low-frequency oscillator with 1024Hz and 8Hz outputs. The PLU shield also includes a test circuit that can be used to implement a simple continuity tester. Several signals from the LPC804 used on the PLU Shield are shared with other functions on the main LPCXpresso804 board. Please review jumper settings on the LPCXpresso804 board carefully before installing the PLU Shield. https://www.nxp.com/docs/en/user-guide/UM11083.pdf  Figure 3. LPCXpresso804 + PLU Shield = PLU demo board   PLU input options On/off switches S1 through S5 connect possible PLU inputs to VDD or GND via a resistor, enabling those inputs to be driven to a known, fixed state. PIO0_8 is connected to a push button (S6) and a 100kohm pull up to VDD; PIO0_8 will be grounded when the button is pressed. Table below shows these connections. Table 2. PLU input on/off switches. A digital oscillator circuit is also included on the Shield, with 1.024kHz and 8Hz outputs available. LPC804 signal PIO0_1 can be connected to these oscillator signals in order to provide a low-speed clock to the flip-flops in the PLU block. The center pin (2) of JP12 connects to PIO0_1, so a jumper can be placed onto JP12 to connect this signal to the required clock (see markings on the Shield silk screen.) An external clock can be provided to the PLU by connecting it to the center pin of JP12. PLU output options LEDs are used to monitor the PLU outputs. Due to the limited number of pins on the chip/board, some of the inputs and outputs are shared. Table 3. PLU shield LEDs. PLU examples You have two options to find a PLU example: Using the SDK for the LPCXpresso804. You can download the SDK for the LPCXpresso804 from Welcome | MCUXpresso SDK Builder The PLU project is a simple demonstration program of the SDK PLU driver. In this example, a number of switches are used act as PLU inputs and LEDs are used to monitor the PLU outputs to demonstrate the configuration and use of the Programmable Logic Unit (PLU). Using the LPC804 Example Code Bundle. Code Bundle, containing source code for drivers, example code and project files. You can download it from LPCXpresso804 board for LPC804 Microcontroller (MCU)|NXP  It is recommended to use the PLU configuration tool. Please check the following links for more details. PLU Tool Direct, LUT-based design: https://www.nxp.com/video/part-2-plu-tool-direct-lut-based-design:Part2-PLU-config-tool-verilog PLU Tool Schematic design: https://www.nxp.com/video/part-3-plu-tool-schematic-design:Part3-PLU-config-tool-schematic PLU Tool Importing Verilog files: https://www.nxp.com/video/part-4-plu-tool-importing-verilog-files:Part4-PLU-config-tool-directlut

Hello Community! This document is provided as a hands-on lab guide.  The intent of the lab is to demonstrate how to program the LPCXpresso804 board with the MCUXpresso IDE making use of the SDK examples and the PLU module drivers. The PLU configuration tool will be used to create a new schematic design that will be programmed to the PLU. Setup The following items need to be installed on your computer to complete the lab: Software: •    SDK_2.4.1_LPCXpresso804: -    Copy link into browser: https://mcuxpresso.nxp.com/en/select?device=LPCXpresso804 -    Select ‘MCUXpresso IDE’ or ‘All Toolchains’ in the Toolchain IDE drop-down -    Select ‘Download SDK’ •    MCUXpresso IDE version 10.2.1: -    Can be installed at following link: https://www.nxp.com/mcuxpresso/ide •    PLU configuration tool -    Can be installed at this link: https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1060-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1060?tab=Design_Tools_Tab   Hardware: •    LPCXpresso804 Development Board (OM40001): https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso804-for-the-lpc804-family-of-mcus:OM40001?tab=Design_Tools_Tab •    PLU Shield Board •    1 Micro USB cable Hope this guide is helpful! Any comments are welcome. Best Regards, Carlos Mendoza Technical Support Engineer

The following document contains a list of documents, questions and discussions that are relevant in the community based on the amount of views they are receiving each month. If you are having a problem, doubt or getting started in LPC or MCUXpresso you should check the following links to see if your doubt have been already solved in the following documents and discussions. MCUXpresso MCUXpresso Supported Devices Table  FAQ: MCUXpresso Software and Tools  How to create a new LPC project using LPCOpen and MCUXpresso IDE  Introducing MCUXpresso SDK v.2 for LPC54xxx Series  Generating a downloadable MCUXpresso SDK v.2 package  Using the MCUXpresso Pins Tool   MCUXpresso Config Tools is now available!   LPC55xx Multicore Applications with MCUXpresso IDE  LPC information LPC5460x MCU Family Overview  USB with NXP Microcontrollers LWIP memory requirements  LPC800 Four-Part Webinar Series!  The LPC804 Programmable Logic Unit (PLU)   LPC84x Technical Training - Now Available Guides and Examples Flashing and Installing the new firmware and drivers for LPC11U35 debug probes  Enabling debug output  USB FLASH download, programming, and security tool (DFUSec)  DMA Ping-Pong application  Getting start with LPCXpresso54608 &amp; emWin Graphics;  Capacitive Touch example using the LPC845 Breakout Board  OLED Display Application Example using LPC845 Breakout Board and SPI  Mixed-Signal Logic Analyzer &amp; Oscilloscope (Lab Tool) Solution  LPC FAQ How to calculate the value of crystal load capacitors? Can I send a message with X/Y/Z bits in the ID?  What is the difference between error active and error passive? What is the sample point for?  How can I verify the configured CAN bitrate, using an oscilloscope?