AnsweredAssumed Answered

HDMI resets LDB clock

Question asked by Dan MacDonald on Dec 12, 2017
Latest reply on Apr 16, 2018 by Dan MacDonald

Hi all,

 

I am working with the SOLO & two displays: lvds0 (primary), and hdmi (secondary). Ultimately I'd like to mirror lvds0 -> to HDMI, but currently my ldb clock is being reset when I plug in the HDMI.

 

I am using this exact display

https://boundarydevices.com/product/bd070lic2/ 

 

The summary of the observable issue is as follows:

  • Startup unit (without HDMI plugged in)
  • View the display (looks GOOD using cat image.raw > /dev/fb0 )
  • Measure the LVDS clock (68.15 MHz = GOOD)
  • Plug in HDMI
  • View the HDMI display (looks GOOD using cat image.raw > /dev/fb2)
  • LVDS display has a flickering (BAD)
  • Measure the LVDS clock (10.61 MHz = BAD)
  • unplug HDMI
  • Measure the LVDS clock (10.61 MHz = BAD, clock doesn't correct itself)

 

My device tree looks this:

&mxcfb1 
{
   disp_dev = "ldb";
   interface_pix_fmt = "RGB24";
   default_bpp = <24>;
   int_clk = <0>;
   late_init = <0>;
   mode_str ="tianma";
   status = "okay";
};

&mxcfb2
{
   disp_dev = "hdmi";
   interface_pix_fmt = "RGB24";
   mode_str ="1280x720M@60";
   default_bpp = <32>;
   int_clk = <0>;
   late_init = <0>;
   status = "okay";
};

&ldb
{
   status = "okay";
   lvds-channel@0
   {
      crtc = "ipu1-di1";
      ipu_id = <0>;
      disp_id = <1>;
      status = "okay";
      fsl,data-width = <24>;
      mode = "dul1";
     
      display-timings
      {
         native-mode = <&timing1>;
         timing1: tianma
         {
            clock-frequency = <68152388>;
            hactive = <1280>;
            vactive = <800>;
            hback-porch = <5>;
            hfront-porch = <63>;
            vback-porch = <2>;
            vfront-porch = <39>;
            hsync-len = <1>;
            vsync-len = <1>;
         }; //~timing1
      }; //~display-timings
   }; //~lvds-channel@0
};//~ldb

 

 

dmesg shows the ipu pixel clock is changing for the disp 1/disp0, but one is clearly affecting the other

 

# dmesg | grep pixel_clk -B2 -A2
[ 0.416858] mxc_sdc_fb fb.32: registered mxc display driver ldb
[ 0.422379] imx-ipuv3 2400000.ipu: use special clk parent
[ 0.428265] imx-ipuv3 2400000.ipu: disp=0, pixel_clk=68152000 68152386 parent=68152386 div=1
[ 0.428311] imx-ipuv3 2400000.ipu: IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7)
[ 0.461117] imx-ipuv3 2400000.ipu: use special clk parent
[ 0.466274] imx-ipuv3 2400000.ipu: disp=0, pixel_clk=68152000 68152386 parent=68152386 div=1
[ 0.476194] Console: switching to colour frame buffer device 160x50
[ 0.510073] mxc_hdmi 20e0000.hdmi_video: Detected HDMI controller 0x13:0x1a:0xa0:0xc1
--
[ 14.785571] NET: Registered protocol family 39
[ 15.082738] imx-ipuv3 2400000.ipu: use special clk parent
[ 15.088268] imx-ipuv3 2400000.ipu: disp=0, pixel_clk=68152000 68152386 parent=68152386 div=1
[ 15.180667] libphy: 2188000.ethernet:00 - Link is Up - 1000/Full
[ 16.386686] usb 2-1.1: new high-speed USB device number 4 using ci_hdrc
--
[ 115.237212] mxc_hdmi 20e0000.hdmi_video: mxc_hdmi_cable_connected reports HDMI mode
[ 115.245624] imx-ipuv3 2400000.ipu: try ipu internal clk
[ 115.253305] imx-ipuv3 2400000.ipu: disp=1, pixel_clk=74250000 74250000 parent=74250000 div=1
[ 115.305517] imx-ipuv3 2400000.ipu: try ipu internal clk
[ 115.311305] imx-ipuv3 2400000.ipu: disp=1, pixel_clk=74250000 74250000 parent=74250000 div=1

 

As you can see at 115.XXX that the HDMI is reported, and the pixel clock is updated, but the disp ID is different (as it should be)

 

What is happening to my clock? Am I missing something ?

 

Thanks,

Outcomes