i.MX8MP ENET_RXC/A25 Pinmux Clarification for MII Interface

[TS-Rameshkumar-PHYTEC]

We are developing a custom board using the PHYTEC phyCORE-i.MX8M Plus SOM and are reviewing the Ethernet pinmux for migration from the existing RGMII interface to MII. The PHYTEC SOM pin A25 is associated with the i.MX8M Plus ENET_RXC signal. In the i.MX8MP pinmux, ENET_RXC supports ALT0 = CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK and ALT1 = ENET_QOS_RX_ER. We need clarification regarding the correct pin assignment and interface requirements for the intended MII configuration. Specifically, is ENET_RXC required for the MII receive interface, or can the required RX_ER function be assigned to another suitable i.MX8M Plus pad/GPIO? If a different pad can be used, please provide the recommended pin mapping. We also need confirmation of whether the i.MX8M Plus ENET_QOS controller supports the intended MII interface and whether any IOMUX, MAC, device-tree, GPR, or PHY configuration changes are required. Please advise on the recommended Ethernet pin mapping and configuration for the i.MX8M Plus with the PHYTEC phyCORE SOM.

[JosephAtNXP · Accepted solution]

Hi,

Thank you for your interest in NXP Semiconductor products,

i.MX 8M Plus does not support MII, please refer to the following extract from RM:

Seamless interface to commercial ethernet PHY devices via one of the following:

• a 2-bit Reduced MII (RMII) operating at 50 MHz.
• a (double data rate) 4-bit Reduced GMII (RGMII) operating at 125 MHz.

For signal mapping, you can refer to i.MX 8M Plus DS.

Regards