Q: Does anyone have the Lauterbach script files for connecting to the mx53?  Also,  does anyone know of a converter to convert RealView scripts to Lauterbach? A: Please see below attach.cmm and load_simbols.cmm for i.MX53. attach.cmm ; ; Script to attach to a running system, halt the CPU, ; and display the ASM code ; screen.on ; Debugger Reset winpage.reset area.reset WINPOS 0. 26. 75. 8. 0. 0. W000 area print "resetting ICD..." System.Down Break.Delete MAP.RESet TASK.RESet sYmbol.RESet Data.PROLOG.RESet Data.EPILOG.RESet sYmbol.AutoLoad.CHECK OFF      ; disable dynamic autoloader sYmbol.AutoLoad.RESet          ; reset autoloader list MMU.RESet ; setup of ICD JTAG print "initializing JTAG..." SYStem.CPU CORTEXA8 SYStem.MultiCore IRPOST 0x0 SYStem.MultiCore IRPRE 0x0 SYStem.MultiCore DRPOST 0x0 SYStem.MultiCore DRPRE 0x0 SYStem.MultiCore DAPIRPOST 0x09 SYStem.MultiCore DAPIRPRE 0x0 SYStem.MultiCore DAPDRPOST 0x02 SYStem.MultiCore DAPDRPRE 0x0 SYStem.MultiCore MEMORYACCESSPORT 0 SYStem.MultiCore DEBUGACCESSPORT 1 SYStem.MultiCore COREBASE APB:0xC0008000 SYStem.Option DACR ON          ; give Debugger global write permissions TrOnchip.Set DABORT OFF        ; used by Linux OS for page miss! TrOnchip.Set PABORT OFF        ; used by Linux OS for page miss! TrOnchip.Set UNDEF OFF         ; let UNDEF be handled by Linux OS SYStem.Option MMU ON           ; enable space ids to virtual addresses SYStem.JtagClock 20.0MHz SETUP.IMASKASM ON              ; lock interrupts while single stepping ; Use on-chip breakpoints Break.SELect PROGRAM ONCHIP Break.SELect READ ONCHIP Break.SELect WRITE ONCHIP Break.SELect ALPHA ONCHIP Break.SELect BETA ONCHIP Break.SELect CHARLY ONCHIP Break.SELect DELTA ONCHIP Break.SELect ECHO ONCHIP SYStem.Option EnReset OFF SYS.m attach ; wait until reset is complete wait 2.s if run()     Break ; Open a Code Window -- we like to see something WINPOS 0. 0. 75. 20. Data.List enddo load.symbols.cmm ; ; Script to load the Linux kernel symbols into the debugger ; print "loading Linux kernel symbols..." &linuxpath="S:\git\kernel\linux-2.6-imx-0" &kbuildpath="build" sYmbol.SourcePATH.SET &linuxpath Data.LOAD.Elf &linuxpath\&kbuildpath\imx5\vmlinux /StripPART 3 /gnu /nocode ; Map the virtual kernel symbols to physical addresses ; to give the debugger access to it before CPU MMU is ; initialized print "setting system MMU..." MMU.FORMAT Linux swapper_pg_dir 0xc0000000--0xc1ffffff 0x70000000 MMU.Create 0xc0000000--0xc1ffffff 0x70000000 ; map kernel pages at RAM start MMU.COMMON 0xc0000000--0xffffffff            ; common area for kernel and processes ;MMU.TableWalk OFF   ; debugger uses a table walk to decode virtual addresses MMU.ON             ; switch on debugger(!) address translation ; Initialize Mutitasking Support print "initializing multitask support..." TASK.CONFIG ../linux       ; loads Linux awareness (linux.t32) MENU.ReProgram ../linux    ; loads Linux menu (linux.men) HELP.FILTER.Add rtoslinux  ; add linux awareness manual to help filter enddo This document was generated from the following discussion: Lauterbach CMM scripts for mx53

Q: Looking at the datasheet, why a 14.7KOhm pulldown and a 4.7KOhm pullup must be used? When useing 4.7KOhm resistors in series from an MCU to control the boot pins, pull up is ok, but pull down is not. The EIM boot pins only see 4.7KOhm and not 14.7KOhm as recommended in the design guide. How did we determine those resistor values? at boot there is a pull-up of 100KOhm in the pad if I understand well, 4.7KOhm would do the job as well as 14.7K. right? A: 4.7k will work fine for pull-up or pull-down. 10k pull-downs is to limit current drain while allowing use of simple SPST switches to configure boot-up. There are on-chip 100k pull resistors, so this limits max resistor size. This document was generated from the following discussion: EIM boot resistor value

Q: Does VIN have to be valid before we can talk to the PMIC over i2c? Can a valid voltage on LICELL and VDDIO work instead? The PF0100 datasheet says: ---------------------------------------------- To communicate with I2C, VIN must be valid and VDDIO, to which SDA and SCL are pulled up, must be powered by a 1.7 to 3.6V supply. VIN, or the coin cell voltage must be valid to maintain the contents of the registers. -------------------------------- A: VIN and VDDIO must be valid for communicating to the I2C block. Having LICELL and VDDIO will not work since a portion of the digital circuitry needed for accessing the registers is powered through VIN. This document was generated from the following discussion: Programming PMIC over i2c

Q: What is quality level of IBIS file? In chapter 8.6 in IMX6DQ6SDLHDG (Rev.0). It says the following about quality assurance. ===== All models (GPIO, DDR, LVDS, MLB) have passed the following checks: • IBISCHK without errors or unexplained warnings • Data for basic simulation checked • Data for timing analysis checked • Data for power analysis checked • Correlated against Spice simulations Validation reports can be provided upon demand. ==== A: In addition, please see http://www.vhdl.org/pub/ibis/quality_wip/checklist/Using_IQ_2.0_checklist.pdf. This document says about quality level. According to these information, the IBIS quality level is IQ4 (IQ3 + data for power  analysis checked) + "Correlated against Spice simulations". This document was generated from the following discussion: IBIS QUALITIY LEVEL

Q: What is latency figures for the VPU to decode Device: i.MX6Q OS: Linux Resolution:                         1920x1080(HD) Frame rate:                        30 FPS Function:                             Overlay messages. Input/Output:                   8 bit / YUV 4:2:0 / NAL stream Profile level:                      4.1. Constrained Baseline. I and P frames support. A: It depend on the syntax in H.264, includes num_reorder_frames,max_dec_frame_buffering,num_ref_frames,MaxDpbSize,etc. for start latency: it cover vpu driver loading, allocate buffers, init, decoding the first frame less than 100ms on iMX6/Linux. This document was generated from the following discussion: VPU Latency i.MX6

Computer On Module • Processor Freescale i.MX535,1GHz/i.MX536, 800MHz • RAM 512MB/1GB DDR3 SDRAM • ROM 4GB EMMC,up to 32GB • Power supply Single 3.1V to 5.5V • Size 54mm SO-DIMM • Temp.-Range -20°C..70°C   -40°C..120°C Key Features • 10/100Mbps Ethernet • Two High Speed USB 2.0 ports • LCD controller up to 1600 x 1200, 24bpp • OpenGL ES 2.0 and OpenVG 1.1 hardware accelerators • Multi-format HD 1080p video decoder and 720p video encoder hardware engine • Two Camera Interfaces • NEON SIMD media accelerator • Unified 256KB L2 cache • Vector Floating Point Unit • Several interfaces: 3x UART, 2x SDIO, 2x SSI/AC97/I2S, I2C, CSPI, Keypad, Ext. Memory I/F • 3.3V I/O OS Support     • Linux     • Android Application:Smart mobile devices,Smart Display,Automotive Infotainment,Digital Signage, Telemedicine,Retail POS Terminal,Security,Barcode Scanner,Visual IP Phone,Patient Monitors,Surveillance Cameras,building control, factory / home automation, HMI For more information, please see Attachment We can provide a complete solution

Computer On Module • Processor i.MX25, 400 MHz • RAM 64/128 MB mDDR • ROM up to 2 GB NAND Flash • Power supply Single 3.0V to 5.5V • Size 42.2mm SO-DIMM200 • Temp.-Range -40°C..85°C Key Features • 10/100Mbps Ethernet • High-Speed USB 2.0 OTG • Full-Speed USB 2.0 Host • LCD controller • Still-picture camera interface • Several peripheral interfaces: UART, SD-CARD, I2C, PWM, 1-wire, Keypad, Digital Audio (AC97/I2S), Configurable serial peripheral interface, 4 wire Touchscreen, CAN OS Support • Windows Embedded CE 6.0 • Linux 2.6.35 Application：POS, handheld terminals, building security, anti-theft devices for e-commerce, smart meters and access control For more information, please see Attachment We can provide a complete solution

Computer On Module • Processor Freescale i.MX287, 454 MHz • RAM 128MB DDR2-400 SDRAM • ROM 128MB NAND Flash • Power supply Single 3.1V to 5.5V • Size 40mmX35mm • Temp.-Range -40°C..85°C Key Features • Two 10/100Mbps Ethernet ports with IEEE1588 support • Two High-Speed USB 2.0 ports • One colour LCD controller • Two CAN interfaces • 4 wire Touchscreen interface • Several peripheral interfaces: UART, SD-CARD, I2C, PWM, Serial Audio, SPI • Power management optimized for long battery life • 3.3V I/O OS Support • Windows Embedded CE 6.0 • Linux 2.6.35 Application：Building control, factory automation, printers and security panels, HMI, industrial control media gateways / accessories, portable medical devices, energy-saving Energy Gateway / Meter For more information, please see Attachment We can provide a complete solution

Computer On Module • Processor Freescale i.MX 6Quad, 1GHz • RAM 1GB DDR3 SDRAM 64-bit • ROM 4GB NAND Flash UP to 16GB • ROM 2M SPI Nor Flash ! • Power supply Single 5V • Size 40mm SO-DIMM • Temp.-Range          0 to + 95C (Consumer)         -20 to + 105C (Extended Consumer)         -40 to +105C (Industrial)         -40 to + 125C (Automotive) Key Features • 10/100Mbps Ethernet • One High Speed USB 2.0 ports • Full HD LCD controller, 24bpp • OpenGL ES 2.0 and OpenVG 1.1 hardware accelerators • Multi-format HD 1080p60 video decoder and 1080p30 encoder hardware engine • Two Camera Interfaces • NEON MPE coprocessor — SIMD Media Processing Architecture — dual, single-precision floating point execute pipeline • Unified 1MB L2 cache • Several interfaces: 5x UART, 2x SDIO, 1x SSI/AC97/I2S, 3x I2C, 2xCSPI • 3.3V I/O • 2x Controller Area Network (FlexCAN) • PCIe 2.0 (1-lane) OS Support     • Linux 3.0     • Android 4.2 Application:Media Tablet,Education Tablet PC,EBook,Automotive Infotainment,Aviation Infotainment,HMI,Portable Medical Instruments,IPTV,IP Phone,Smart Energy Systems,Intelligent industrial control systems For more information, please see Attachment We can provide a complete solution

In Chinese Twitter: Sino Weibo, one famous distributor mentioned “i.MX28 is the best choice in ARM9 core-based processor, no ‘one of’”. With high integration of analog module and digital module, i.MX28 is attracting more and more engineers in various applications. Despite its advantage, there are some mistakes one may commit or issues they may meet. The note records a number of issues/mistakes. Each case in the note comes from a real story. I hope the note will help you in your development work. And It is definitely welcomed for everyone to add your own content to the note.The more you share, the more you get.

Q: When trying to mount his SDIO WiFi module (an Azurewave module containing a Marvel 88W8790)  in 4 bit mode, and got error wifi module on iMX6 Smart SD dev board using the alpha kernel (3.5.7+3285970). mwifiex_sdio mmc0:0001:1: WLAN FW is active mwifiex_sdio mmc0:0001:1: mwifiex_cmd_timeout_func: Timeout cmd id (2004.239824) = 0xa9, act = 0x0 mwifiex_sdio mmc0:0001:1: num_data_h2c_failure = 0 mwifiex_sdio mmc0:0001:1: num_cmd_h2c_failure = 0 mwifiex_sdio mmc0:0001:1: num_cmd_timeout = 1 mwifiex_sdio mmc0:0001:1: num_tx_timeout = 0 mwifiex_sdio mmc0:0001:1: last_cmd_index = 1 mwifiex_sdio mmc0:0001:1: last_cmd_resp_index = 0 mwifiex_sdio mmc0:0001:1: last_event_index = 0 mwifiex_sdio mmc0:0001:1: data_sent=1 cmd_sent=1 mwifiex_sdio mmc0:0001:1: ps_mode=1 ps_state=0 +++++++++++++++++++++++ There are only two known issues with the SDHC driver as noted in the release notes and these don't seem to match.  The Linux Reference Manual states the operation of the SDIO was veriifed usign the AR6003.  My assumption is that this is the Silex module we have standardized on.  Was 4 bit mode verified using this module? Does anyone have any idea what could be happening here? A: L3.5.7 is an alpha release, and WiFi function is not stable. The test report shows that open WiFi issue exists. Wifi module sometime can't work on mx6q_smd. After insmod ath, ath6kl_core and ath6kl_sdio. Insert the wifi card, sometime(50%) will display -------------------------- ath6kl: unable to read RX_LOOKAHEAD_VALID                                      ath6kl: Unable to recv target info: -84                                        ath6kl: Failed to init ath6kl core                                             ath6kl_sdio: probe of mmc0:0001:1 failed with error -84    -------------------------- reinsert the wifi card may solve the problem. when execute "udhcpc -i wlan0", sometime (30%) will cause program exception. Sometime can't get the wlan0 ip(program hang). Environment(OS,Platform,Driver, etc): HW: MX6Q_SMD Num014 and Num017 MX6Q_ARD don't have this problem SW: Kernel 3.5.7-1.0.0 GNU/Linux Case ID: TGE-LV-WIFI-0043 Reproduce Steps: #modprobe ath #modprobe ath6kl_core #modprobe ath6kl_sdio insert the wifi card # iwconfig wlan0 mode managed # iwlist wlan0 scanning | grep MAD-wifi #iwconfig wlan0 key 00112233445566778899123456 #iwconfig wlan0 essid MAD-wifi #udhcpc -i wlan0 Attached MX6 ARD WiFi issue also. [Kernel3.5.7_MX6QARD]Wifi:wifi card can't work during suspend and resume. 100% -- Bug detailed description: With wifi card inserted in the board. doing system suspend and resume test. wifi card can't work well after the system suspend and resume. Always report : ath6kl: Unable to decrement the command credit count register: -84             ath6kl: Unable to write to the device: -84                                     ath6kl: bmi_write_memory for uart debug failed                                 ath6kl: Failed to boot hw in resume: -5          Environment(OS,Platform,Driver, etc): HW: MX6QARD -023 Only tried on this platform SW: root@imx6qsabreauto:~# uname -a                                                Linux imx6qsabreauto 3.5.7-1.0.0+3285970 #1 SMP PREEMPT Sat Jun 29 10:20:45 CDT 2013 armv7l GNU/Linux Case ID:  TGE-LV-WIFI-1060 and TGE-LV-WIFI-1062 Reproduce Steps: 1. boot the kernel with wif card inserted 2. doing wifi stress test 3. doing suspend and resume

Q: Can OpenGL/OpenVG work on any of our boards with a 16-bit DDR bus? Here is GPU state dump when run some of the GPU SDK tutorials on their imx6 solo board with a 16-bit DDR bus: Mounting rootfs VFS: Mounted root (nfs filesystem) readonly on device 0:12. Freeing init memory: 156K Starting init GPU[0]: ************************** ***   GPU STATE DUMP   *** **************************   axi      = 0x000000B1   idle     = 0x7FFFFF86     FE not idle     SH not idle     PA not idle     SE not idle     RA not idle   DMA appears to be stuck at this address:     0x1882F230   dmaLow   = 0x08010583   dmaHigh  = 0x80003400   dmaState = 0x00000904     command state       = 4 (PAR_ADR1_ST)     command DMA state   = 1 (CMD_START_ST)     command fetch state = 2 (FET_VALID_ST)     DMA request state   = 0 (REQ_IDLE_ST)     cal state           = 0 (CAL_IDLE_ST)     VE request state    = 0 (VER_IDLE_ST)   RA debug registers:     [0x00] 0x0108C378     [0x01] 0x0042FB12     [0x02] 0x0042FB11     [0x03] 0x0000022C     [0x04] 0x10220033     [0x05] 0x0885C800     [0x06] 0xC054CBFE     [0x07] 0x68100000     [0x08] 0x00000000     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x12344321     [0x0D] 0x12344321     [0x0E] 0x12344321     [0x0F] 0x12344321     signature = 0x12344321 (1 read attempt(s))   TX debug registers:     [0x00] 0x00000000     [0x01] 0x00000000     [0x02] 0x00000000     [0x03] 0x00000000     [0x04] 0x00000000     [0x05] 0x00000000     [0x06] 0x00000000     [0x07] 0x00000000     [0x08] 0x00000000     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0x00000000     [0x0E] 0x00000000     [0x0F] 0x00000000     failed to obtain the signature (read 0x00000000).   FE debug registers:     [0x00] 0x1882F450     [0x01] 0x08010594     [0x02] 0x00000001     [0x03] 0x00000256     [0x04] 0x00080049     [0x05] 0x0000000D     [0x06] 0x00009571     [0x07] 0x00007445     [0x08] 0x00000004     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0xA3105D67     [0x0E] 0x000000D0     [0x0F] 0xBABEF00D     signature = 0xBABEF00D (1 read attempt(s))   PE debug registers:     [0x00] 0x0108C369     [0x01] 0x00000000     [0x02] 0x0108C369     [0x03] 0x00000000     [0x04] 0xA0000000     [0x05] 0xABC00000     [0x06] 0xBC000000     [0x07] 0xCDE00000     [0x08] 0xD04045C0     [0x09] 0x204045C0     [0x0A] 0x0D863084     [0x0B] 0x00000000     [0x0C] 0xBABEF00D     [0x0D] 0xBABEF00D     [0x0E] 0xBABEF00D     [0x0F] 0xBABEF00D     signature = 0xBABEF00D (1 read attempt(s))   DE debug registers:     [0x00] 0x00000000     [0x01] 0x00000000     [0x02] 0x00000000     [0x03] 0x00000000     [0x04] 0x00000000     [0x05] 0x00000000     [0x06] 0x00000000     [0x07] 0x00000000     [0x08] 0x00000000     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0x00000000     [0x0E] 0x00000000     [0x0F] 0x00000000     failed to obtain the signature (read 0x00000000).   SH debug registers:     [0x00] 0x0049AB4C     [0x01] 0x0000000B     [0x02] 0x00000411     [0x03] 0x00020A95     [0x04] 0x00000000     [0x05] 0x000F024E     [0x06] 0x000F424C     [0x07] 0x010BEC30     [0x08] 0x0108C368     [0x09] 0x000020DF     [0x0A] 0x00000693     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0x00000000     [0x0E] 0x00000000     [0x0F] 0xDEADBEEF     signature = 0xDEADBEEF (1 read attempt(s))   PA debug registers:     [0x00] 0x640006FE     [0x01] 0x64000000     [0x02] 0x00000810     [0x03] 0x00000690     [0x04] 0x00000230     [0x05] 0x0000022D     [0x06] 0x00000000     [0x07] 0x00000000     [0x08] 0x00000003     [0x09] 0x0000AAAA     [0x0A] 0x0000AAAA     [0x0B] 0x0000AAAA     [0x0C] 0x0000AAAA     [0x0D] 0x0000AAAA     [0x0E] 0x0000AAAA     [0x0F] 0x0000AAAA     signature = 0x0000AAAA (1 read attempt(s))   SE debug registers:     [0x00] 0x00000000     [0x01] 0x00000000     [0x02] 0x00000000     [0x03] 0x00000000     [0x04] 0x00000000     [0x05] 0x00000000     [0x06] 0x00000000     [0x07] 0x00000000     [0x08] 0x00000000     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0x00000000     [0x0E] 0x00000000     [0x0F] 0x00000000     failed to obtain the signature (read 0x00000000).   MC debug registers:     [0x00] 0x00000000     [0x01] 0x00000000     [0x02] 0x00000000     [0x03] 0x00000000     [0x04] 0x12345678     [0x05] 0x12345678     [0x06] 0x12345678     [0x07] 0x12345678     [0x08] 0x12345678     [0x09] 0x12345678     [0x0A] 0x12345678     [0x0B] 0x12345678     [0x0C] 0x12345678     [0x0D] 0x12345678     [0x0E] 0x12345678     [0x0F] 0x12345678     signature = 0x12345678 (1 read attempt(s))   HI debug registers:     [0x00] 0x0000F719     [0x01] 0x19C020C8     [0x02] 0x1EBC2426     [0x03] 0xAAAAAAAA     [0x04] 0xAAAAAAAA     [0x05] 0xAAAAAAAA     [0x06] 0xAAAAAAAA     [0x07] 0xAAAAAAAA     [0x08] 0xAAAAAAAA     [0x09] 0xAAAAAAAA     [0x0A] 0xAAAAAAAA     [0x0B] 0xAAAAAAAA     [0x0C] 0xAAAAAAAA     [0x0D] 0xAAAAAAAA     [0x0E] 0xAAAAAAAA     [0x0F] 0xAAAAAAAA     signature = 0xAAAAAAAA (1 read attempt(s))   Other Registers:     [0x0040] 0x00924A66     [0x0044] 0x06F47370     [0x004C] 0x06F47370     [0x0050] 0x00DE8E6E     [0x0054] 0x00DE8E6E     [0x0058] 0x00924A66     [0x005C] 0x001254D6     [0x0060] 0x001254D6     [0x043C] 0x00000000     [0x0440] 0x00000000     [0x0444] 0x00000000     [0x0414] 0x3C000000 [<8003b21c>] (unwind_backtrace+0x0/0xfc) from [<80308114>] (_DumpGPUState+0x4ec/0x6b4) [<80308114>] (_DumpGPUState+0x4ec/0x6b4) from [<80308324>] (gckOS_Broadcast+0x38/0xe8) [<80308324>] (gckOS_Broadcast+0x38/0xe8) from [<80311008>] (gckEVENT_GetEvent+0x184/0x1b4) [<80311008>] (gckEVENT_GetEvent+0x184/0x1b4) from [<80311294>] (gckEVENT_Submit+0x8c/0x328) [<80311294>] (gckEVENT_Submit+0x8c/0x328) from [<8030dedc>] (gckCOMMAND_Commit+0x4d4/0xa28) [<8030dedc>] (gckCOMMAND_Commit+0x4d4/0xa28) from [<8030c1d0>] (gckKERNEL_Dispatch+0x4b4/0x112c) [<8030c1d0>] (gckKERNEL_Dispatch+0x4b4/0x112c) from [<80306580>] (drv_ioctl+0x108/0x250) [<80306580>] (drv_ioctl+0x108/0x250) from [<800ed704>] (do_vfs_ioctl+0x80/0x5e0) [<800ed704>] (do_vfs_ioctl+0x80/0x5e0) from [<800edc9c>] (sys_ioctl+0x38/0x60) [<800edc9c>] (sys_ioctl+0x38/0x60) from [<80035580>] (ret_fast_syscall+0x0/0x30) A: This GPU driver stack dump indicates GPU stuck when VDDPU_CAP was under spec values (1.2V) so GPU was not correctly powered. Was fixed by adjusting PMU_REG_CORE[REG1_TARG]. AFAIK, GPU drivers have some DDR bank configuration, so you may see a different problem though.

Q: MX53 u-boot doc to enable the splash screen and went through Re: MX53 u-boot Splash Screen support but I can't seem to get the splash working on the VGA output.  A: FSL do not have solution / recommendations for VGA splash screen under U-boot. Only LVDS is supported. Typically, the Uboot bootloader does not interact with any display interface and does not have a splash screen displaying capability. To add this feature to Uboot on i.MX5 platform, the IPU driver should be included into the Uboot code. Looks like we do not have ready to use solution for the LCD. As an example for LCD configuring it makes sense to use LCD settings from Linux driver. Another approach - to use Linux (Penguin) logo (assuming Linux is booted quickly after U-boot) - at least, Linux supports more display drivers and its logo using is specified. follow up question is since the Tux the penguin logo is only 80x80 is it possible to make a larger image for the Linux start up logo? yes, you should configure kernel for the new image on make menuconfig That doesn’t help this H/W guy, but I think this may - https://community.freescale.com/thread/304300    look for  “#To change the splash screen of linux kernel (small penguine on top left corner)..“

Q: ”We noticed that the specified risetime of this signal is max 5nS, while the Sable board schematic shows it driven from open collector/drain using only the 100k haulup provided in the chip. This will have risetimes of 10‘s (if not 100‘s!) of ns. The worrying thing is that the latest datasheet update specifically clarifies this rise time spec, so presumably it‘s considered important. Which is right? If the rise time spec needs to be met, we need a small haul up resistor or an active drive. In that case what rail should be used to haul/drive POR_B high?” It appears to be correct, and what is interesting I checked the PFUZE timing in the datasheet ”tr4 Rise time of RESETBMCU - 0.2 ms” Device: i.MX6Q OS: Linux Dev Board: i.MX6Q SDB A: The 5ns rise/fall time requirement does not apply to i.MX6. This was probably carried over from the i.MX53 where it was required. This will be removed from the datasheet but it will likely not be until the September time frame. We're not doing an update to any of the electrical parameters of the datasheet right now.

Q: How to setup camera under Android? helping a customer (RTX) debug some issues with camera. They're using i.MX 6Solo and Android 13.4-GA on custom hardware. They added a new camera driver which seems to work when using small console capture program (no gui, no preview), so the route from camera to /dev/video0 seems to work. However, when they try to use camera from Android, entire system freezes. They located the crash to following line in ipu_common.c which basically enables camera CSI0: ipu_cm_write(ipu, reg | IPU_CONF_CSI0_EN, IPU_CONF); While investigating IPU setup, we noticed that CPMEM setup for IDMAC channel 0 is "off": ch 0 word 0 - 00000000 25800000 00000000 E0000000 00077C4F ch 0 word 1 - 01B086B0 00394EC0 0087C000 00009FC0 0000027F As seen from above, EBA0 points to 0x0D843580 and EBA1 to 0x0E53B000, which is in EIM memory space, not DDR memory space, which probably causes issues. We're not sure what could be causing this as camera driver doesn't provide any such address and mostly just handles communication to camera chip. But something gets off in Android framework and we could use any hints about what to look for. A: You can reference to the "i.MXAndroidR13.4GAAdvancedUserGuide.html" "3 Camera&Video Recorder customization" for how to change the camera in Android. Another thing needs be checked is the camera sensor driver, you can reference to "kernel_imx\drivers\media\video\mxc\capture\ov5642.c", "static struct v4l2_int_ioctl_desc ov5642_ioctl_desc", did you implemented the same v4l2_int_ioctl_desc functions? Customer HW is set up so that DDR memory space starts at 0x80000000. This causes problems in myandroid/hardware/imx/mx6/libcamera/CamerHAL.cpp when obtaining buffer addresses where camera should store data. GPU will only return OFFSET into 2GB memory space it can address, so it will return an address below 0x80000000. This needs to be adjusted before passing onto V4L2 when starting capturing.

Q: What is the Min LPDDR2 clock frequency allowed by the i.MX6? The Jedec Spec for LPDDR2 allows for a min tck period of 100ns. Are there any required relashionship between the DDR clock frequency and other clocks in the i.MX6? A: The JEDEC maximum period for the MX6 is 100nS as per the LPDDR2 specification.  There is a minimum period during boot, before everything is configured and fully up to speed of 18nS. Are you saying the imx6 memory controller can operatate down to the min frequecies specified in the LPDDR2 JEDEC spec? Given that there is no limit specified in the data sheet, it should operate that slowly, provided the clocking can be set for it to operate so slowly. I would imagine that the core will need to be running slowly as well, since it does not make sense to slow the memory bus without slowing the core down as well.

Q: What is i.Mx6 ECSPI max frequency? https://community.freescale.com/message/338305 But in the RM we clearly state 60 MHz is the default config while Boot from SPI. I cannot measure it because I have no board where I can boot from SPI Nor. Also if I look at clocking, PLL  is 480MHz divided by 8 is fixed thus we get 60 MHz. Next divider can be either 1, thus ECSPI_CLK_ROOT  = 60MHz or 2, thus ECSPI_CLK_ROOT = 30 MHz. A: From i.MX6 Datasheet (IMX6DQCEC, Rev. 2.3, 07/2013), Table 52 (ECSPI Master Mode Timing Parameters) : ECSPIx_SCLK Cycle Time–Read • Slow group                                        55 ns • Fast group                                        40 ns         ECSPIx_SCLK Cycle Time–Write          15 ns So, only for writing we can get ~60 MHz.

Q: Q&A: Where to find IBIS Models on the web? A: In the first figure (FSL driving 100 ohm), the processor is DC coupled to a transmission line and terminated at the far end with a 100-ohm resistor. The results look pretty normal for this. In the other figure, the processor is dc coupled to a transmission line, then ac coupled to another transmission line segment (0.1u) with 50-ohm resistors to ground, and then drives the inputs of an HCSL clock buffer. The results are pretty un remarkable. The top red signal in the trace is one of the IMX6 clock outputs, the first green signal is the other clock output, and the last green signal (from top to bottom that is) is the differential signal seen by the clock buffer. The customer is concerned about the asymmetrical drive of the processor. It looks like LVDS clock outputs do not like to be AC coupled. This simulation resembles the way the clock is handled in the Smart Device schematics where the clock is AC coupled to the reference clock inputs on the PCIE connector. The ibis files were downloaded from the web (21x21_imx6q, consumer variant). So a few updates: I had the customer download the latest duallite IBIS models. Previously they were apparently using the quad/dual models. They are going to update HyperLynx and are going to run a simulation and let me know if they still see the same issue. He said he's using "linesim". Meanwhile he noticed a different problem with the duallite/solo IBIS models. Although the datasheet says LVDDR3 (1.35V) is supported, there is no model for DDR3_L either as input or output. The same model existed in the quad/dual models. Do you know why this option is not in the duallite IBIS models? Thanks! A ctm of mine would like to get the IBIS model with LVDDR3 support on the i.MX6 DL. For mx6-duallite IBIS models for DDR3L memory (1.35V). It'd be great if the models matched the quad version. Please find the new updated IBIS file in website. http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6DL&nodeId=018rH3ZrDRB24A&fpsp=1&tab=Design_Tools_Tab

It is suggested to create a layer when creating or modifying any metadata file (recipe, configuration file or class). The main reason is simple: modularity. Follow these steps 1. To have access to Yocto scripts, setup the enviroment from the BASE folder fsl-community-bsp $ . setup-environment build 2. Move to the place you want to create your layer and choose a name (e.g. `fsl-custom`) sources $ yocto-layer create fsl-custom # Answer the questions. Make sure the priority is set correctly (higher numbers, # higher priorities). Set the priority equal to the lowest already present, except # when you have introduce a new recipe with the same name as other and want to shadow # the original one. 3. Add any metadata content. Suggestion: Version the layer with Git and upload your local git repo to a server 4. Edit and add the layer to the `build/conf/bblayers.conf` file 5. To verify that your layer is *seen* by BitBake, run the following command under the build folder build $ bitbake-layers show-layers This document was generated from the following discussion: i.MX Yocto Proyect: How can I create a new Layer?

Q: Some background; this instrument has one display connected to the LVDS output of the i.MX6Solo and the SVGA monitor is using the IPU port with an external Analog Devices ADV7125 DAC to actually drive the monitor (or projector).  From Tektronix: We got our kernel logo to show up on an external SVGA monitor as well as on the internal LVDS display so we now at least know that the hardware is functional. However, when our application starts running and writing to the fb0 (background) and fb1 (foreground/overlay) frame buffers, the external monitor (fb2 frame buffer) doesn't get updated. We need to know how to get the same data going to the external monitor as goes to the internal LVDS display.  the external monitor is 800x600 and the internal is 800x480 so we'd further like those 480 lines to show up centered in the 600 line monitor. We are also hoping that this can be down without having to write/DMA all of the data twice. The answer given is SR #1122663812 was "If the customer is using Linux, fb2 should also be drawed by their application."  This was considered in adequate and Tek replied: I would like to know if they are saying that the IPU absolutely cannot automatically do what we want and if not, why not?  I would like to have some detailed information to at least convince us that they've looked into this and it really isn't possible. A: In our Linux BSP we don't support such feature. And in android BSP it was already supported. The customer must draw the fb2 by their application, ipu doesn't have the feature that combining the fb0 and overlay fb1, then resize it to fb2 automatically. The customer application can drawing their UI into a memory, then use v4l2 output to draw this buffer to both fb0 and fb2, in this case, resizing will be implemented in V4l2 output driver with IPU hardware. And if the customer needs overlay on fb2, they must combine the two layer into memory with IPU task first, then using V4l2 output to render it to display fb2. For how to use IPU task, the customer can reference to BSP unit test code: imx-test-1.1.0\test\mxc_ipudev_test The summary: for dual display case, the fb0 and fb2 are just two framebuffer memory, they must be filled before rendering to display, on iMX6S/DL, only the fb0 has the hardware overlay (fb1); if the customer wants to show same contents on two displays in Linux, their application must draw the two framebuffers, but we had some hardware method to improve the performace, using GPU or IPU task. In Android, the application will not draw frame buffer directly, it will use Android surface flinger middleware to draw, so this feature was implemnted in surface flinger; but in Linux, there is no such middleware, and application draws the framebuffer directly, so the application should handle it. This document was generated from the following discussion: i.MX6Solo LDB/LVDS &amp; LCD Ports Active Simultaneously