[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343761 

From iMX 3.1x kernel, all kernel debug messages will be print to debug serial port after UART driver loaded, so if the kernel hang up before tty console driver ready, there will be no kernel boot up messages.   The attached patch can be used to enable the iMX serial debug console in early time, then kernel will not buffer the debug messages.   Note: the default patch is for UART1 (tty0) as the debug port, if you need use other debug port, please modify the code "early_console_setup()" with correct UART port base address.   L3.10.53-Add-early-console-for-debug-message.patch This patch is based on L3.10.53_GA1.1.0 release, it can support iMX6S/DL/D/Q.   L3.14.52-Add-early-console-for-debug-message.patch This patch is based on L3.14.52_GA1.1.0 release, it can support iMX6S/DL/D/Q, iMX6SL, iMX6SX, iMX6UL and iMX7.  

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-344336 

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-342833 

                For the SPI NOR booting on fuse steps. 1.      Please boot your PCB on uboot and type below command for fuse boot setting. MX6Q SABRESD-MFG U-Boot > imxotp blow --force 5 0x0a000030 MX6Q SABRESD-MFG U-Boot > imxotp read 5 Reading fuse at index: 0x5 Fuse at (index: 0x5) value: 0xA000030 MX6Q SABRESD-MFG U-Boot > imxotp read 6 Reading fuse at index: 0x6 Fuse at (index: 0x6) value: 0x0 MX6Q SABRESD-MFG U-Boot > imxotp blow --force 6 0x10 Current fuse at (index: 0x6) value: 0x0 Blowing fuse at index: 0x6, value: 0x10 Reloading shadow registers... Operation succeeded fuse at (index: 0x6) value: 0x10 MX6Q SABRESD-MFG U-Boot > imxotp read 6 Reading fuse at index: 0x6 Fuse at (index: 0x6) value: 0x10 MX6Q SABRESD-MFG U-Boot > 2.      Set the boot mode for 00 as Boot from fuses 3.      You could see the SPI clock on scope after re power on.

Hi everyone, Can I stream video at some different resolutions at the same time using I.Mx6? Thank you.

ESAI module in i.MX6D/I.MX6D/I.MX6DL/I.MX6S supports several RESET funtions: Reset ESAI Core, Reset both Transmitter and Receiver, Reset Transmitter individually, Reset Receiver individually, Reset Transmitter FIFO and Reset Receiver FIFO. Below is a simple diagram for these RESET functions, which shows reset object and related register configurations. 1.Reset ESAI Core After setting ESAI_ECT ERST bit to be 1, ESAI core and configuration registers will be reset, but Transmitter and Recevier FIFOs can't be reset by the operation. 2. Reset both Transmitter and Receiver After setting ESAI_PCRC & ESAI_PRRC to be 0x000, Transmitter and Receiver can both be reset, The RESET is also called "Personal Reset" in it's reference manual. About PCRC & PRRC bits functionality, we can see the table: From the table, ESAI_PCRC=0x000 and ESAI_PRRC=0x000 will make ESAI disconnet external ESAI pins, and ESAI's Tranmitter and Receiver can't communicate with external audio codec.  See ESAI_PCRC and ESAI_PRRC register below: ---ESAI_PCRC register ---ESAI_PRRC register There are 12 bits in each register to contorl "DISCONNECTION" OR "CONNECTION" with ESAI pins. So for normal operations of ESAI, these 2 registers can't be changed. 3.Reset Transmitter & Receiver individually By setting ESAI_TCR[TPR]=1, Transmitter can be reset individually, and not affect Receiver. By setting ESAI_RCR[RPR]=1, Receiver can be reset individually, and not affect Transmitter . In reference manual, the reset is called "personal reset / individual reset", actually they means the same thing: --Reset Transmitter individually. --Reset Receiver individually. 4.Reset Transmitter FIFO and Reset Receiver FIFO ---By setting ESAI_TFCR[TFR]=1, Tranmitter FIFIO can be reset. ---By setting ESAI_RFCR[RFR]=1, Receiver FIFO can be reset. The Reset requires ESAI is operational, which means at least one pin is defined as an ESAI pin. NXP TIC team Weidong Sun

Question: Two boards are used and practically identical - one using the i.MX6Solo, the other is using a Dual. The sw settings in both cases are identical (except IOMUX addresses). On the i.MX6Solo they do not see any packet loss, on the i.MX6Dual they do. I recommended modifying the MTU size, but this also did not help. So here my two questions: 1)      is there still some hw difference between the Ethernet block on the Solo and the Dual/Quad? 2)      They run the AHB at only 100MHz. Could that be a problem? If not, why do the two chips behave so differently? To increase the AHB clock to 133 MHz.appears to solve the packet corruption issue. Is the 100 MHz AHB clock really the root cause. Answer: The DualLite/Solo and SoloLite contain different ethernet controllers. The DL/S has a 1000M controller which requires the AHB bus to be greater than 125MHz, while the SL has a 100M controller. As the question was about the Solo and the Dual and both use the Gigabit Ethernet block I assume that both will require a minimum AHB clock of 125MHz.

Attached is the Kernel needed to construct the following image: i.MX 6Dual/6Quad Power Consumption Measurement Linux Image

Attached is the Kernel image needed to construct the Linux Image i.MX 6Dual/6Quad Power Consumption Measurement Linux Image

Sometime need standalone compile device tree. Only Linux headers and device tree directory are needed.         

Question: What does it means by depending on load? Is there a value? This is  related with i.MX6D Answer: The comment about the "load" means the total system load on the 2.5V rail. We understand that people design systems, not just MX6 devices. The documentation confusion stems from the design team changing from allowing customers to use the LDOs to power system devices back to just using the LDOs to power the MX6. Reasons - thermals, and also concern for uncontrolled system noise injection into the MX6 and causing failures.