How to Understand "Several Reset Functions" Of i.MX6Q ESAI Module

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How to Understand "Several Reset Functions" Of i.MX6Q ESAI Module

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How to Understand "Several Reset Functions" Of i.MX6Q ESAI Module

ESAI module in i.MX6D/I.MX6D/I.MX6DL/I.MX6S supports several RESET funtions: Reset ESAI Core, Reset both Transmitter and Receiver, Reset Transmitter individually, Reset Receiver individually, Reset Transmitter FIFO and Reset Receiver FIFO. Below is a simple diagram for these RESET functions, which shows reset object and related register configurations.

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1.Reset ESAI Core

After setting ESAI_ECT ERST bit to be 1, ESAI core and configuration registers will be reset, but Transmitter and Recevier FIFOs can't be reset by the operation.

2. Reset both Transmitter and Receiver

After setting ESAI_PCRC & ESAI_PRRC to be 0x000, Transmitter and Receiver can both be reset, The RESET is also called "Personal Reset" in it's reference manual. About PCRC & PRRC bits functionality, we can see the table:

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From the table, ESAI_PCRC=0x000 and ESAI_PRRC=0x000 will make ESAI disconnet external ESAI pins, and ESAI's Tranmitter and Receiver can't communicate with external audio codec.  See ESAI_PCRC and ESAI_PRRC register below:

---ESAI_PCRC register

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---ESAI_PRRC register

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There are 12 bits in each register to contorl "DISCONNECTION" OR "CONNECTION" with ESAI pins.

So for normal operations of ESAI, these 2 registers can't be changed.

3.Reset Transmitter & Receiver individually

By setting ESAI_TCR[TPR]=1, Transmitter can be reset individually, and not affect Receiver.

By setting ESAI_RCR[RPR]=1, Receiver can be reset individually, and not affect Transmitter .

In reference manual, the reset is called "personal reset / individual reset", actually they means the same thing:

--Reset Transmitter individually.

--Reset Receiver individually.

4.Reset Transmitter FIFO and Reset Receiver FIFO

---By setting ESAI_TFCR[TFR]=1, Tranmitter FIFIO can be reset.

---By setting ESAI_RFCR[RFR]=1, Receiver FIFO can be reset.

The Reset requires ESAI is operational, which means at least one pin is defined as an
ESAI pin.

NXP TIC team

Weidong Sun

Version history
Revision #:
1 of 1
Last update:
‎03-05-2019 12:44 AM
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