All mentioned clock signals belong to the OVDD(OVDD1) domain - refer to the QorIQ T2080 Data Sheet, Table 1. Pinout list by bus.
OVDD(OVDD1) could be only 1.8V – refer to the QorIQ T2080 Data Sheet, Table 3. Recommended operating conditions.
So SYSCLK, DDRCLK and USBCLK have to have 1.8V amplitude.
> DIFF_SYS_CLK p and n can be supplied with a 3.3V input oscillator?
No.
Refer to the QorIQ T2080 Data Sheet, 3.6.6.1 Differential System clock DC timing specifications.