QorIQ T1040 DIFF_SYSCLK input specifications

[fdm]

Hi,

According to T1040 Family Design Checklist, DIFF_SYSCLK input is "LVDS type clock buffer with AC/DC characteristics identical to the SerDes reference clock inputs which are HCSL-compatible".

Section 3.6.6.1 of T1040 DS "Differential System clock DC timing specifications" says "For DC timing specification, see (3.22.2.3) DC-level requirement for SerDes reference clocks".

Section 3.22.2.3 constrains input CM voltage between 100 mV and 400 mV for an external DC-coupled connection based on the assumption of maximum average current allowed for each input pin (8 mA).

Is this constraint applicable to the DIFF_SYSCLK input (it seems very doubtful)?

Is there an internal biasing circuit at the DIFF_SYSCLK input or it should be added externally in the case of AC coupling?

BR,

   Denis

[r8070z]

Have a great day,

Yes the section 3.22.2.3 constrains applicable to the DIFF_SYSCLK input for an external DC-coupled connection. Table 34 of the design checklist shows recommended external DC-coupled connections to different clock source types.

In case of AC coupling input external biasing circuit is not required at the DIFF_SYSCLK input. Recommended  AC-coupled connections you can find in Freescale application note AN3411 “SerDes Reference Clock Interfacing and HSSI Measurements Recommendations”

https://www.freescale.com/webapp/Download?colCode=AN4311

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[fdm]

Hi Serguei,

What range of the CM voltage is allowed at the DIFF_SYSCLK input?

BR,

   Denis

[r8070z · Accepted solution]

I was informed from SOC design that there is no internal AC coupling in the DIFF_SYSCLK clock receiver. So AN3411  cannot be directly applied to this inputs. 

The data sheet specifies the input common mode voltage range as 50mv - 1570 mV.