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QorIQ T1040 DIFF_SYSCLK input specifications

Question asked by fdm on Sep 22, 2015
Latest reply on Nov 3, 2016 by Serguei Podiatchev

Hi,

 

According to T1040 Family Design Checklist, DIFF_SYSCLK input is "LVDS type clock buffer with AC/DC characteristics identical to the SerDes reference clock inputs which are HCSL-compatible".

Section 3.6.6.1 of T1040 DS "Differential System clock DC timing specifications" says "For DC timing specification, see (3.22.2.3) DC-level requirement for SerDes reference clocks".

Section 3.22.2.3 constrains input CM voltage between 100 mV and 400 mV for an external DC-coupled connection based on the assumption of maximum average current allowed for each input pin (8 mA).

Is this constraint applicable to the DIFF_SYSCLK input (it seems very doubtful)?

Is there an internal biasing circuit at the DIFF_SYSCLK input or it should be added externally in the case of AC coupling?

 

BR,

   Denis

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