I am using a T1040 processor. The clock signals to the chip, DIFF_SYS_CLK p and n can be supplied with a 3.3V input oscillator or do we need to give 1.8V itself. Do these pins have internal pull ups?
Could you help me with the voltage levels of the other clocks as well namely.
1. DDR Clock
2. System Clock
3. USB clock
All mentioned clock signals belong to the OVDD(OVDD1) domain - refer to the QorIQ T2080 Data Sheet, Table 1. Pinout list by bus.
OVDD(OVDD1) could be only 1.8V – refer to the QorIQ T2080 Data Sheet, Table 3. Recommended operating conditions.
So SYSCLK, DDRCLK and USBCLK have to have 1.8V amplitude.
> DIFF_SYS_CLK p and n can be supplied with a 3.3V input oscillator?
Refer to the QorIQ T2080 Data Sheet, 18.104.22.168 Differential System clock DC timing specifications.
Could you suggest apart number for the Differential system clock 100 MHz. I am unable to find one that suffice the requirements given in table 14 of the datasheet. The swing shwn is 1.08V to 1.8v right ?
For the DDR clock of the chip, I am unable to find a part. te reference schematic sgiven do not have a part specified either. Do you have any recommendations for the same that falls within the specified swing of 1.08 to 1.8v.