Would you confirm that the DIFF_SYSCLK inputs in LS1021A and T1040 have different DC characteristics?
Both processors' datasheets describe this input as LVDS receiver with internal 100 Ohm terminator and direct coupling (Fig.11 in T1040 DS and Fig.10 in LS1021A DS).
Both processors' design checklists say: "Although it is a LVDS type clock driver but it has AC/DC characteristics identical to the SerDes reference clock inputs which are HCSL-compatible".
Preliminary revision of LS1021A datasheet and current revision of T1040 datasheet both say: "For DC timing specification, see DC-level requirement for SerDes reference clocks". These SerDes reference clock inputs have an internal AC-coupling, and consequently they can tolerate zero CM voltage in the case of an external AC-coupling.
But, in contrast, current revision of LS1021A datasheet have a separate table with DC characteristics for DIFF_SYSCLK, and the input common mode voltage of (50...1570)mV is specified.
Does LS1021A support an external AC coupling at DIFF_SYSCLK input? Should an external biasing be implemented in this case and what is the recommended schematic for the such biasing?
Does LS1021A really support DC-coupled connection of LVPECL driver (Vcm=2.0V) as it shown at Figure 27 of the Design Checklist? What should be the missing value of the R2 resistors in this case?
(P.S. There is the discussion of T1040 DIFF_SYSCLK input)